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tegra_timer.c revision 1.1.2.2 
      1 /* $NetBSD: tegra_timer.c,v 1.1.2.2 2015/06/06 14:39:56 skrll Exp $ */
      2 
      3 /*-
      4  * Copyright (c) 2015 Jared D. McNeill <jmcneill (at) invisible.ca>
      5  * All rights reserved.
      6  *
      7  * Redistribution and use in source and binary forms, with or without
      8  * modification, are permitted provided that the following conditions
      9  * are met:
     10  * 1. Redistributions of source code must retain the above copyright
     11  *    notice, this list of conditions and the following disclaimer.
     12  * 2. Redistributions in binary form must reproduce the above copyright
     13  *    notice, this list of conditions and the following disclaimer in the
     14  *    documentation and/or other materials provided with the distribution.
     15  *
     16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
     17  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
     18  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     19  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
     20  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
     21  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
     22  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
     23  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
     24  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
     25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
     26  * SUCH DAMAGE.
     27  */
     28 
     29 #include <sys/cdefs.h>
     30 __KERNEL_RCSID(0, "$NetBSD: tegra_timer.c,v 1.1.2.2 2015/06/06 14:39:56 skrll Exp $");
     31 
     32 #include <sys/param.h>
     33 #include <sys/bus.h>
     34 #include <sys/device.h>
     35 #include <sys/intr.h>
     36 #include <sys/systm.h>
     37 #include <sys/kernel.h>
     38 #include <sys/wdog.h>
     39 
     40 #include <dev/sysmon/sysmonvar.h>
     41 
     42 #include <arm/nvidia/tegra_reg.h>
     43 #include <arm/nvidia/tegra_timerreg.h>
     44 #include <arm/nvidia/tegra_var.h>
     45 
     46 #define TEGRA_TIMER_WDOG_PERIOD_DEFAULT	10
     47 
     48 static int	tegra_timer_match(device_t, cfdata_t, void *);
     49 static void	tegra_timer_attach(device_t, device_t, void *);
     50 
     51 struct tegra_timer_softc {
     52 	device_t		sc_dev;
     53 	bus_space_tag_t		sc_bst;
     54 	bus_space_handle_t	sc_bsh;
     55 
     56 	struct sysmon_wdog	sc_smw;
     57 };
     58 
     59 static int	tegra_timer_wdt_setmode(struct sysmon_wdog *);
     60 static int	tegra_timer_wdt_tickle(struct sysmon_wdog *);
     61 
     62 CFATTACH_DECL_NEW(tegra_timer, sizeof(struct tegra_timer_softc),
     63 	tegra_timer_match, tegra_timer_attach, NULL, NULL);
     64 
     65 #define TIMER_READ(sc, reg)			\
     66     bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))
     67 #define TIMER_WRITE(sc, reg, val)		\
     68     bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))
     69 #define TIMER_SET_CLEAR(sc, reg, set, clr)	\
     70     tegra_reg_set_clear((sc)->sc_bst, (sc)->sc_bsh, (reg), (set), (clr))
     71 
     72 static int
     73 tegra_timer_match(device_t parent, cfdata_t cf, void *aux)
     74 {
     75 	return 1;
     76 }
     77 
     78 static void
     79 tegra_timer_attach(device_t parent, device_t self, void *aux)
     80 {
     81 	struct tegra_timer_softc * const sc = device_private(self);
     82 	struct tegraio_attach_args * const tio = aux;
     83 	const struct tegra_locators * const loc = &tio->tio_loc;
     84 
     85 	sc->sc_dev = self;
     86 	sc->sc_bst = tio->tio_bst;
     87 	bus_space_subregion(tio->tio_bst, tio->tio_bsh,
     88 	    loc->loc_offset, loc->loc_size, &sc->sc_bsh);
     89 
     90 	aprint_naive("\n");
     91 	aprint_normal(": Timers\n");
     92 
     93 	sc->sc_smw.smw_name = device_xname(self);
     94 	sc->sc_smw.smw_cookie = sc;
     95 	sc->sc_smw.smw_setmode = tegra_timer_wdt_setmode;
     96 	sc->sc_smw.smw_tickle = tegra_timer_wdt_tickle;
     97 	sc->sc_smw.smw_period = TEGRA_TIMER_WDOG_PERIOD_DEFAULT;
     98 
     99 	aprint_normal_dev(self, "default watchdog period is %u seconds\n",
    100 	    sc->sc_smw.smw_period);
    101 
    102 	if (sysmon_wdog_register(&sc->sc_smw) != 0)
    103 		aprint_error_dev(self, "couldn't register with sysmon\n");
    104 }
    105 
    106 static int
    107 tegra_timer_wdt_setmode(struct sysmon_wdog *smw)
    108 {
    109 	struct tegra_timer_softc * const sc = smw->smw_cookie;
    110 
    111 	if ((smw->smw_mode & WDOG_MODE_MASK) == WDOG_MODE_DISARMED) {
    112 		TIMER_SET_CLEAR(sc, TMR1_PTV_REG, 0, TMR_PTV_EN);
    113 		tegra_car_wdt_enable(1, false);
    114 	} else {
    115 		if (smw->smw_period == WDOG_PERIOD_DEFAULT) {
    116 			sc->sc_smw.smw_period = TEGRA_TIMER_WDOG_PERIOD_DEFAULT;
    117 		} else if (smw->smw_period == 0 || smw->smw_period > 1000) {
    118 			return EINVAL;
    119 		} else {
    120 			sc->sc_smw.smw_period = smw->smw_period;
    121 		}
    122 		u_int tval = (sc->sc_smw.smw_period * 1000000) / 2;
    123 		TIMER_WRITE(sc, TMR1_PTV_REG,
    124 		    TMR_PTV_EN | TMR_PTV_PER | __SHIFTIN(tval, TMR_PTV_VAL));
    125 		TIMER_WRITE(sc, TMR1_PCR_REG, TMR_PCR_INTR_CLR);
    126 		tegra_car_wdt_enable(1, true);
    127 	}
    128 
    129 	return 0;
    130 }
    131 
    132 static int
    133 tegra_timer_wdt_tickle(struct sysmon_wdog *smw)
    134 {
    135 	struct tegra_timer_softc * const sc = smw->smw_cookie;
    136 
    137 	TIMER_WRITE(sc, TMR1_PCR_REG, TMR_PCR_INTR_CLR);
    138 
    139 	return 0;
    140 }
    141