tegra_timer.c revision 1.4.2.1
1 /* $NetBSD: tegra_timer.c,v 1.4.2.1 2017/04/26 02:53:01 pgoyette Exp $ */ 2 3 /*- 4 * Copyright (c) 2015 Jared D. McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: tegra_timer.c,v 1.4.2.1 2017/04/26 02:53:01 pgoyette Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/bus.h> 34 #include <sys/device.h> 35 #include <sys/intr.h> 36 #include <sys/systm.h> 37 #include <sys/kernel.h> 38 #include <sys/wdog.h> 39 40 #include <dev/sysmon/sysmonvar.h> 41 42 #include <arm/nvidia/tegra_reg.h> 43 #include <arm/nvidia/tegra_timerreg.h> 44 #include <arm/nvidia/tegra_var.h> 45 46 #include <dev/fdt/fdtvar.h> 47 48 #define TEGRA_TIMER_WDOG_PERIOD_DEFAULT 10 49 50 static int tegra_timer_match(device_t, cfdata_t, void *); 51 static void tegra_timer_attach(device_t, device_t, void *); 52 53 struct tegra_timer_softc { 54 device_t sc_dev; 55 bus_space_tag_t sc_bst; 56 bus_space_handle_t sc_bsh; 57 58 struct sysmon_wdog sc_smw; 59 }; 60 61 static int tegra_timer_wdt_setmode(struct sysmon_wdog *); 62 static int tegra_timer_wdt_tickle(struct sysmon_wdog *); 63 64 CFATTACH_DECL_NEW(tegra_timer, sizeof(struct tegra_timer_softc), 65 tegra_timer_match, tegra_timer_attach, NULL, NULL); 66 67 #define TIMER_READ(sc, reg) \ 68 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg)) 69 #define TIMER_WRITE(sc, reg, val) \ 70 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)) 71 #define TIMER_SET_CLEAR(sc, reg, set, clr) \ 72 tegra_reg_set_clear((sc)->sc_bst, (sc)->sc_bsh, (reg), (set), (clr)) 73 74 static int 75 tegra_timer_match(device_t parent, cfdata_t cf, void *aux) 76 { 77 const char * const compatible[] = { "nvidia,tegra124-timer", NULL }; 78 struct fdt_attach_args * const faa = aux; 79 80 return of_match_compatible(faa->faa_phandle, compatible); 81 } 82 83 static void 84 tegra_timer_attach(device_t parent, device_t self, void *aux) 85 { 86 struct tegra_timer_softc * const sc = device_private(self); 87 struct fdt_attach_args * const faa = aux; 88 bus_addr_t addr; 89 bus_size_t size; 90 int error; 91 92 if (fdtbus_get_reg(faa->faa_phandle, 0, &addr, &size) != 0) { 93 aprint_error(": couldn't get registers\n"); 94 return; 95 } 96 97 sc->sc_dev = self; 98 sc->sc_bst = faa->faa_bst; 99 error = bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh); 100 if (error) { 101 aprint_error(": couldn't map %#llx: %d", (uint64_t)addr, error); 102 return; 103 } 104 105 aprint_naive("\n"); 106 aprint_normal(": Timers\n"); 107 108 sc->sc_smw.smw_name = device_xname(self); 109 sc->sc_smw.smw_cookie = sc; 110 sc->sc_smw.smw_setmode = tegra_timer_wdt_setmode; 111 sc->sc_smw.smw_tickle = tegra_timer_wdt_tickle; 112 sc->sc_smw.smw_period = TEGRA_TIMER_WDOG_PERIOD_DEFAULT; 113 114 aprint_normal_dev(self, 115 "default watchdog period is %u seconds\n", 116 sc->sc_smw.smw_period); 117 118 if (sysmon_wdog_register(&sc->sc_smw) != 0) { 119 aprint_error_dev(self, 120 "couldn't register with sysmon\n"); 121 } 122 } 123 124 static int 125 tegra_timer_wdt_setmode(struct sysmon_wdog *smw) 126 { 127 struct tegra_timer_softc * const sc = smw->smw_cookie; 128 129 if ((smw->smw_mode & WDOG_MODE_MASK) == WDOG_MODE_DISARMED) { 130 TIMER_SET_CLEAR(sc, TMR1_PTV_REG, 0, TMR_PTV_EN); 131 } else { 132 if (smw->smw_period == WDOG_PERIOD_DEFAULT) { 133 sc->sc_smw.smw_period = TEGRA_TIMER_WDOG_PERIOD_DEFAULT; 134 } else if (smw->smw_period == 0 || smw->smw_period > 1000) { 135 return EINVAL; 136 } else { 137 sc->sc_smw.smw_period = smw->smw_period; 138 } 139 u_int tval = (sc->sc_smw.smw_period * 1000000) / 2; 140 TIMER_WRITE(sc, TMR1_PTV_REG, 141 TMR_PTV_EN | TMR_PTV_PER | __SHIFTIN(tval, TMR_PTV_VAL)); 142 TIMER_WRITE(sc, TMR1_PCR_REG, TMR_PCR_INTR_CLR); 143 } 144 145 return 0; 146 } 147 148 static int 149 tegra_timer_wdt_tickle(struct sysmon_wdog *smw) 150 { 151 struct tegra_timer_softc * const sc = smw->smw_cookie; 152 153 TIMER_WRITE(sc, TMR1_PCR_REG, TMR_PCR_INTR_CLR); 154 155 return 0; 156 } 157 158 void 159 delay(u_int us) 160 { 161 static bool timerus_configured = false; 162 bus_space_tag_t bst = &armv7_generic_bs_tag; 163 bus_space_handle_t bsh; 164 165 bus_space_subregion(bst, tegra_ppsb_bsh, TEGRA_TIMER_OFFSET, 166 TEGRA_TIMER_SIZE, &bsh); 167 168 if (__predict_false(timerus_configured == false)) { 169 /* clk_m frequency 12 MHz */ 170 bus_space_write_4(bst, bsh, TMRUS_USEC_CFG_REG, 0xb); 171 timerus_configured = true; 172 } 173 174 u_int nus = 0; 175 u_int us_prev = bus_space_read_4(bst, bsh, TMRUS_CNTR_1US_REG); 176 177 while (nus < us) { 178 const u_int us_cur = bus_space_read_4(bst, bsh, 179 TMRUS_CNTR_1US_REG); 180 if (us_cur < us_prev) { 181 nus += (0xffffffff - us_prev) + us_cur; 182 } else { 183 nus += (us_cur - us_prev); 184 } 185 us_prev = us_cur; 186 } 187 } 188
Indexes created Tue Sep 30 17:09:57 GMT 2025