tegra_usbreg.h revision 1.1.2.3
1 1.1.2.3 skrll /* $NetBSD: tegra_usbreg.h,v 1.1.2.3 2017/02/05 13:40:04 skrll Exp $ */ 2 1.1.2.2 skrll 3 1.1.2.2 skrll /*- 4 1.1.2.2 skrll * Copyright (c) 2015 Jared D. McNeill <jmcneill (at) invisible.ca> 5 1.1.2.2 skrll * All rights reserved. 6 1.1.2.2 skrll * 7 1.1.2.2 skrll * Redistribution and use in source and binary forms, with or without 8 1.1.2.2 skrll * modification, are permitted provided that the following conditions 9 1.1.2.2 skrll * are met: 10 1.1.2.2 skrll * 1. Redistributions of source code must retain the above copyright 11 1.1.2.2 skrll * notice, this list of conditions and the following disclaimer. 12 1.1.2.2 skrll * 2. Redistributions in binary form must reproduce the above copyright 13 1.1.2.2 skrll * notice, this list of conditions and the following disclaimer in the 14 1.1.2.2 skrll * documentation and/or other materials provided with the distribution. 15 1.1.2.2 skrll * 16 1.1.2.2 skrll * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 1.1.2.2 skrll * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 1.1.2.2 skrll * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 1.1.2.2 skrll * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 1.1.2.2 skrll * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 1.1.2.2 skrll * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 1.1.2.2 skrll * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 1.1.2.2 skrll * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 1.1.2.2 skrll * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 1.1.2.2 skrll * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 1.1.2.2 skrll * SUCH DAMAGE. 27 1.1.2.2 skrll */ 28 1.1.2.2 skrll 29 1.1.2.2 skrll #ifndef _ARM_TEGRA_USBREG_H 30 1.1.2.2 skrll #define _ARM_TEGRA_USBREG_H 31 1.1.2.2 skrll 32 1.1.2.2 skrll #define TEGRA_EHCI_TXFILLTUNING_REG 0x154 33 1.1.2.2 skrll #define TEGRA_EHCI_TXFILLTUNING_TXFIFOTHRES __BITS(21,16) 34 1.1.2.2 skrll 35 1.1.2.2 skrll #define TEGRA_EHCI_ICUSB_CTRL_REG 0x15c 36 1.1.2.2 skrll #define TEGRA_EHCI_ICUSB_CTRL_ENB1 __BIT(3) 37 1.1.2.2 skrll #define TEGRA_EHCI_ICUSB_CTRL_VDD1 __BITS(2,0) 38 1.1.2.2 skrll 39 1.1.2.2 skrll #define TEGRA_EHCI_HOSTPC1_DEVLC_REG 0x1b4 40 1.1.2.2 skrll #define TEGRA_EHCI_HOSTPC1_DEVLC_PTS __BITS(31,29) 41 1.1.2.2 skrll #define TEGRA_EHCI_HOSTPC1_DEVLC_PTS_UTMI 0 42 1.1.2.2 skrll #define TEGRA_EHCI_HOSTPC1_DEVLC_PTS_ULPI 2 43 1.1.2.2 skrll #define TEGRA_EHCI_HOSTPC1_DEVLC_PTS_ICUSB_SER 3 44 1.1.2.2 skrll #define TEGRA_EHCI_HOSTPC1_DEVLC_STS __BIT(28) 45 1.1.2.2 skrll #define TEGRA_EHCI_HOSTPC1_DEVLC_PTW __BIT(27) 46 1.1.2.2 skrll #define TEGRA_EHCI_HOSTPC1_DEVLC_PSPD __BITS(26,25) 47 1.1.2.2 skrll #define TEGRA_EHCI_HOSTPC1_DEVLC_PSPD_FS 0 48 1.1.2.2 skrll #define TEGRA_EHCI_HOSTPC1_DEVLC_PSPD_LS 1 49 1.1.2.2 skrll #define TEGRA_EHCI_HOSTPC1_DEVLC_PSPD_HS 2 50 1.1.2.2 skrll #define TEGRA_EHCI_HOSTPC1_DEVLC_ALPD __BIT(24) 51 1.1.2.2 skrll #define TEGRA_EHCI_HOSTPC1_DEVLC_PFSC __BIT(23) 52 1.1.2.2 skrll #define TEGRA_EHCI_HOSTPC1_DEVLC_PHCD __BIT(22) 53 1.1.2.2 skrll #define TEGRA_EHCI_HOSTPC1_DEVLC_H_LPMX __BITS(21,20) 54 1.1.2.2 skrll #define TEGRA_EHCI_HOSTPC1_DEVLC_H_EPLPM __BITS(19,16) 55 1.1.2.2 skrll #define TEGRA_EHCI_HOSTPC1_DEVLC_H_LPMFRM __BITS(15,12) 56 1.1.2.2 skrll #define TEGRA_EHCI_HOSTPC1_DEVLC_D_ASUS __BIT(17) 57 1.1.2.2 skrll #define TEGRA_EHCI_HOSTPC1_DEVLC_D_STL __BIT(16) 58 1.1.2.2 skrll #define TEGRA_EHCI_HOSTPC1_DEVLC_BA __BITS(11,1) 59 1.1.2.2 skrll 60 1.1.2.2 skrll #define TEGRA_EHCI_USBMODE_REG 0x1f8 61 1.1.2.2 skrll #define TEGRA_EHCI_USBMODE_CM __BITS(1,0) 62 1.1.2.2 skrll #define TEGRA_EHCI_USBMODE_CM_IDLE 0 63 1.1.2.2 skrll #define TEGRA_EHCI_USBMODE_CM_DEVICE 2 64 1.1.2.2 skrll #define TEGRA_EHCI_USBMODE_CM_HOST 3 65 1.1.2.2 skrll 66 1.1.2.2 skrll #define TEGRA_EHCI_SUSP_CTRL_REG 0x400 67 1.1.2.2 skrll #define TEGRA_EHCI_SUSP_CTRL_UHSIC_RESET __BIT(14) 68 1.1.2.2 skrll #define TEGRA_EHCI_SUSP_CTRL_ULPI_PHY_ENB __BIT(13) 69 1.1.2.2 skrll #define TEGRA_EHCI_SUSP_CTRL_UTMIP_PHY_ENB __BIT(12) 70 1.1.2.2 skrll #define TEGRA_EHCI_SUSP_CTRL_UTMIP_RESET __BIT(11) 71 1.1.2.2 skrll #define TEGRA_EHCI_SUSP_CTRL_PHY_CLK_VALID __BIT(7) 72 1.1.2.2 skrll 73 1.1.2.2 skrll #define TEGRA_EHCI_PHY_VBUS_SENSORS_REG 0x404 74 1.1.2.2 skrll #define TEGRA_EHCI_PHY_VBUS_SENSORS_A_VBUS_VLD_STS __BIT(26) 75 1.1.2.2 skrll #define TEGRA_EHCI_PHY_VBUS_SENSORS_B_VLD_SW_VALUE __BIT(12) 76 1.1.2.2 skrll #define TEGRA_EHCI_PHY_VBUS_SENSORS_B_VLD_SW_EN __BIT(11) 77 1.1.2.2 skrll 78 1.1.2.3 skrll #define TEGRA_EHCI_PHY_VBUS_WAKEUP_ID_REG 0x408 79 1.1.2.3 skrll #define TEGRA_EHCI_PHY_VBUS_WAKEUP_ID_ID_PU __BIT(6) 80 1.1.2.3 skrll #define TEGRA_EHCI_PHY_VBUS_WAKEUP_ID_ID_DEB_SEL_B __BIT(5) 81 1.1.2.3 skrll #define TEGRA_EHCI_PHY_VBUS_WAKEUP_ID_ID_SW_VALUE __BIT(4) 82 1.1.2.3 skrll #define TEGRA_EHCI_PHY_VBUS_WAKEUP_ID_ID_SW_EN __BIT(3) 83 1.1.2.3 skrll #define TEGRA_EHCI_PHY_VBUS_WAKEUP_ID_ID_STS __BIT(2) 84 1.1.2.3 skrll #define TEGRA_EHCI_PHY_VBUS_WAKEUP_ID_ID_CHG_DET __BIT(1) 85 1.1.2.3 skrll #define TEGRA_EHCI_PHY_VBUS_WAKEUP_ID_ID_INT_EN __BIT(0) 86 1.1.2.3 skrll 87 1.1.2.2 skrll #define TEGRA_EHCI_UTMIP_XCVR_CFG0_REG 0x808 88 1.1.2.2 skrll #define TEGRA_EHCI_UTMIP_XCVR_CFG0_HSSLEW_MSB __BITS(31,25) 89 1.1.2.2 skrll #define TEGRA_EHCI_UTMIP_XCVR_CFG0_SETUP_MSB __BITS(24,22) 90 1.1.2.2 skrll #define TEGRA_EHCI_UTMIP_XCVR_CFG0_LSBIAS_SEL __BIT(21) 91 1.1.2.2 skrll #define TEGRA_EHCI_UTMIP_XCVR_CFG0_SETUP __BITS(3,0) 92 1.1.2.2 skrll #define TEGRA_EHCI_UTMIP_XCVR_CFG0_PDZI_POWERDOWN __BIT(18) 93 1.1.2.2 skrll #define TEGRA_EHCI_UTMIP_XCVR_CFG0_PD2_POWERDOWN __BIT(16) 94 1.1.2.2 skrll #define TEGRA_EHCI_UTMIP_XCVR_CFG0_PD_POWERDOWN __BIT(14) 95 1.1.2.2 skrll 96 1.1.2.2 skrll #define TEGRA_EHCI_UTMIP_BIAS_CFG0_REG 0x80c 97 1.1.2.2 skrll #define TEGRA_EHCI_UTMIP_BIAS_CFG0_HSDISCON_LEVEL_MSB __BIT(24) 98 1.1.2.2 skrll #define TEGRA_EHCI_UTMIP_BIAS_CFG0_BIASPD __BIT(10) 99 1.1.2.2 skrll #define TEGRA_EHCI_UTMIP_BIAS_CFG0_HSDISCON_LEVEL __BITS(3,2) 100 1.1.2.2 skrll 101 1.1.2.2 skrll #define TEGRA_EHCI_UTMIP_TX_CFG0_REG 0x820 102 1.1.2.2 skrll #define TEGRA_EHCI_UTMIP_TX_CFG0_FS_PREAMBLE_J __BIT(19) 103 1.1.2.2 skrll 104 1.1.2.2 skrll #define TEGRA_EHCI_UTMIP_MISC_CFG0_REG 0x824 105 1.1.2.2 skrll #define TEGRA_EHCI_UTMIP_MISC_CFG0_SUSPEND_EXIT_ON_EDGE __BIT(22) 106 1.1.2.2 skrll 107 1.1.2.2 skrll #define TEGRA_EHCI_UTMIP_MISC_CFG1_REG 0x828 108 1.1.2.2 skrll #define TEGRA_EHCI_UTMIP_MISC_CFG1_PHY_XTAL_CLOCKEN __BIT(30) 109 1.1.2.2 skrll 110 1.1.2.2 skrll #define TEGRA_EHCI_UTMIP_DEBOUNCE_CFG0_REG 0x82c 111 1.1.2.2 skrll #define TEGRA_EHCI_UTMIP_DEBOUNCE_CFG0_B __BITS(31,16) 112 1.1.2.2 skrll #define TEGRA_EHCI_UTMIP_DEBOUNCE_CFG0_A __BITS(15,0) 113 1.1.2.2 skrll 114 1.1.2.2 skrll #define TEGRA_EHCI_UTMIP_BAT_CHRG_CFG0_REG 0x830 115 1.1.2.2 skrll #define TEGRA_EHCI_UTMIP_BAT_CHRG_CFG0_PD_CHRG __BIT(0) 116 1.1.2.2 skrll 117 1.1.2.2 skrll #define TEGRA_EHCI_UTMIP_SPARE_CFG0_REG 0x834 118 1.1.2.2 skrll 119 1.1.2.2 skrll #define TEGRA_EHCI_UTMIP_XCVR_CFG1_REG 0x838 120 1.1.2.2 skrll #define TEGRA_EHCI_UTMIP_XCVR_CFG1_TERM_RANGE_ADJ __BITS(21,18) 121 1.1.2.2 skrll #define TEGRA_EHCI_UTMIP_XCVR_CFG1_PDDR_POWERDOWN __BIT(4) 122 1.1.2.2 skrll #define TEGRA_EHCI_UTMIP_XCVR_CFG1_PDCHRP_POWERDOWN __BIT(2) 123 1.1.2.2 skrll #define TEGRA_EHCI_UTMIP_XCVR_CFG1_PDDISC_POWERDOWN __BIT(0) 124 1.1.2.2 skrll 125 1.1.2.2 skrll #define TEGRA_EHCI_UTMIP_BIAS_CFG1_REG 0x83c 126 1.1.2.2 skrll #define TEGRA_EHCI_UTMIP_BIAS_CFG1_PDTRK_COUNT __BITS(7,3) 127 1.1.2.2 skrll #define TEGRA_EHCI_UTMIP_BIAS_CFG1_PDTRK_POWERDOWN __BIT(0) 128 1.1.2.2 skrll 129 1.1.2.2 skrll #define TEGRA_EHCI_UTMIP_HSRX_CFG0_REG 0xc08 130 1.1.2.2 skrll #define TEGRA_EHCI_UTMIP_HSRX_CFG0_IDLE_WAIT __BITS(19,15) 131 1.1.2.2 skrll #define TEGRA_EHCI_UTMIP_HSRX_CFG0_ELASTIC_LIMIT __BITS(14,10) 132 1.1.2.2 skrll 133 1.1.2.2 skrll #define TEGRA_EHCI_UTMIP_HSRX_CFG1_REG 0xc0c 134 1.1.2.2 skrll #define TEGRA_EHCI_UTMIP_HSRX_CFG1_SYNC_START_DLY __BITS(5,1) 135 1.1.2.2 skrll 136 1.1.2.2 skrll #endif /* _ARM_TEGRA_USBREG_H */ 137
Indexes created Mon Oct 20 20:10:13 GMT 2025