tegra_xusb.c revision 1.1
1 /* $NetBSD: tegra_xusb.c,v 1.1 2016/09/26 20:05:03 jakllsch Exp $ */ 2 3 /* 4 * Copyright (c) 2016 Jonathan A. Kollasch 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR 20 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 21 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 22 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 23 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 25 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 26 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include "locators.h" 30 #include "opt_tegra.h" 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: tegra_xusb.c,v 1.1 2016/09/26 20:05:03 jakllsch Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/bus.h> 37 #include <sys/device.h> 38 #include <sys/intr.h> 39 #include <sys/systm.h> 40 #include <sys/kernel.h> 41 42 #include <arm/nvidia/tegra_reg.h> 43 #include <arm/nvidia/tegra_var.h> 44 45 #include <arm/nvidia/tegra_xusbreg.h> 46 #include <dev/pci/pcireg.h> 47 48 #include <dev/fdt/fdtvar.h> 49 50 #include <dev/firmload.h> 51 52 #include <dev/usb/usb.h> 53 #include <dev/usb/usbdi.h> 54 #include <dev/usb/usbdivar.h> 55 #include <dev/usb/usb_mem.h> 56 57 #include <dev/usb/xhcireg.h> 58 #include <dev/usb/xhcivar.h> 59 60 static int tegra_xusb_match(device_t, cfdata_t, void *); 61 static void tegra_xusb_attach(device_t, device_t, void *); 62 static void tegra_xusb_mountroot(device_t); 63 64 static int tegra_xusb_intr_mbox(void *); 65 66 #ifdef TEGRA124_XUSB_BIN_STATIC 67 extern const char _binary_tegra124_xusb_bin_size[]; 68 extern const char _binary_tegra124_xusb_bin_start[]; 69 #endif 70 71 struct fw_dma { 72 bus_dmamap_t map; 73 void * addr; 74 bus_dma_segment_t segs[1]; 75 int nsegs; 76 size_t size; 77 }; 78 79 struct tegra_xusb_softc { 80 struct xhci_softc sc_xhci; 81 int sc_phandle; 82 bus_space_handle_t sc_bsh_xhci; 83 bus_space_handle_t sc_bsh_fpci; 84 bus_space_handle_t sc_bsh_ipfs; 85 void *sc_ih; 86 void *sc_ih_mbox; 87 struct fw_dma sc_fw_dma; 88 struct clk *sc_clk_ss_src; 89 }; 90 91 static uint32_t csb_read_4(struct tegra_xusb_softc * const, bus_size_t); 92 static void csb_write_4(struct tegra_xusb_softc * const, bus_size_t, 93 uint32_t); 94 95 static void tegra_xusb_init(struct tegra_xusb_softc * const); 96 static void tegra_xusb_load_fw(struct tegra_xusb_softc * const); 97 98 static int xusb_mailbox_send(struct tegra_xusb_softc * const, uint32_t); 99 100 CFATTACH_DECL_NEW(tegra_xusb, sizeof(struct tegra_xusb_softc), 101 tegra_xusb_match, tegra_xusb_attach, NULL, NULL); 102 103 static int 104 tegra_xusb_match(device_t parent, cfdata_t cf, void *aux) 105 { 106 const char * const compatible[] = { "nvidia,tegra124-xusb", NULL }; 107 struct fdt_attach_args * const faa = aux; 108 109 return of_match_compatible(faa->faa_phandle, compatible); 110 } 111 112 static void 113 tegra_xusb_attach(device_t parent, device_t self, void *aux) 114 { 115 struct tegra_xusb_softc * const psc = device_private(self); 116 struct xhci_softc * const sc = &psc->sc_xhci; 117 struct fdt_attach_args * const faa = aux; 118 char intrstr[128]; 119 bus_addr_t addr; 120 bus_size_t size; 121 int error; 122 struct clk *clk; 123 uint32_t rate; 124 struct fdtbus_reset *rst; 125 126 aprint_naive("\n"); 127 aprint_normal(": XUSB\n"); 128 129 sc->sc_dev = self; 130 sc->sc_iot = faa->faa_bst; 131 sc->sc_bus.ub_hcpriv = sc; 132 sc->sc_bus.ub_dmatag = faa->faa_dmat; 133 psc->sc_phandle = faa->faa_phandle; 134 135 if (fdtbus_get_reg(faa->faa_phandle, 0, &addr, &size) != 0) { 136 aprint_error(": couldn't get registers\n"); 137 return; 138 } 139 error = bus_space_map(sc->sc_iot, addr, size, 0, &sc->sc_ioh); 140 if (error) { 141 aprint_error(": couldn't map %#llx: %d", (uint64_t)addr, error); 142 return; 143 } 144 printf("mapped %#llx\n", (uint64_t)addr); 145 146 if (fdtbus_get_reg(faa->faa_phandle, 1, &addr, &size) != 0) { 147 aprint_error(": couldn't get registers\n"); 148 return; 149 } 150 error = bus_space_map(sc->sc_iot, addr, size, 0, &psc->sc_bsh_fpci); 151 if (error) { 152 aprint_error(": couldn't map %#llx: %d", (uint64_t)addr, error); 153 return; 154 } 155 printf("mapped %#llx\n", (uint64_t)addr); 156 157 if (fdtbus_get_reg(faa->faa_phandle, 2, &addr, &size) != 0) { 158 aprint_error(": couldn't get registers\n"); 159 return; 160 } 161 error = bus_space_map(sc->sc_iot, addr, size, 0, &psc->sc_bsh_ipfs); 162 if (error) { 163 aprint_error(": couldn't map %#llx: %d", (uint64_t)addr, error); 164 return; 165 } 166 printf("mapped %#llx\n", (uint64_t)addr); 167 168 if (!fdtbus_intr_str(faa->faa_phandle, 0, intrstr, sizeof(intrstr))) { 169 aprint_error_dev(self, "failed to decode interrupt\n"); 170 return; 171 } 172 173 psc->sc_ih = fdtbus_intr_establish(faa->faa_phandle, 0, IPL_USB, 174 0, xhci_intr, sc); 175 if (psc->sc_ih == NULL) { 176 aprint_error_dev(self, "failed to establish interrupt on %s\n", 177 intrstr); 178 return; 179 } 180 aprint_normal_dev(self, "interrupting on %s\n", intrstr); 181 182 if (!fdtbus_intr_str(faa->faa_phandle, 1, intrstr, sizeof(intrstr))) { 183 aprint_error_dev(self, "failed to decode interrupt\n"); 184 return; 185 } 186 187 psc->sc_ih_mbox = fdtbus_intr_establish(faa->faa_phandle, 1, IPL_VM, 188 0, tegra_xusb_intr_mbox, psc); 189 if (psc->sc_ih_mbox == NULL) { 190 aprint_error_dev(self, "failed to establish interrupt on %s\n", 191 intrstr); 192 return; 193 } 194 aprint_normal_dev(self, "interrupting on %s\n", intrstr); 195 196 struct clk * const pll_p_out0 = clk_get("pll_p_out0"); 197 KASSERT(pll_p_out0 != NULL); 198 199 struct clk * const pll_u_48 = clk_get("pll_u_48"); 200 KASSERT(pll_u_48 != NULL); 201 202 struct clk * const pll_u_480 = clk_get("pll_u_480"); 203 KASSERT(pll_u_480 != NULL); 204 205 clk = fdtbus_clock_get(faa->faa_phandle, "pll_e"); 206 rate = clk_get_rate(clk); 207 error = clk_enable(clk); /* XXX set frequency */ 208 device_printf(sc->sc_dev, "rate %u error %d\n", rate, error); 209 210 clk = fdtbus_clock_get(faa->faa_phandle, "xusb_host_src"); 211 error = clk_set_parent(clk, pll_p_out0); 212 rate = clk_get_rate(clk); 213 device_printf(sc->sc_dev, "rate %u error %d\n", rate, error); 214 error = clk_set_rate(clk, 102000000); 215 rate = clk_get_rate(clk); 216 error = clk_enable(clk); /* XXX set frequency */ 217 device_printf(sc->sc_dev, "rate %u error %d\n", rate, error); 218 219 clk = fdtbus_clock_get(faa->faa_phandle, "xusb_falcon_src"); 220 error = clk_set_parent(clk, pll_p_out0); 221 rate = clk_get_rate(clk); 222 device_printf(sc->sc_dev, "rate %u error %d\n", rate, error); 223 error = clk_set_rate(clk, 204000000); 224 rate = clk_get_rate(clk); 225 error = clk_enable(clk); 226 device_printf(sc->sc_dev, "rate %u error %d\n", rate, error); 227 228 clk = fdtbus_clock_get(faa->faa_phandle, "xusb_host"); 229 rate = clk_get_rate(clk); 230 error = clk_enable(clk); /* XXX set frequency */ 231 device_printf(sc->sc_dev, "rate %u error %d\n", rate, error); 232 233 clk = fdtbus_clock_get(faa->faa_phandle, "xusb_ss"); 234 rate = clk_get_rate(clk); 235 error = clk_enable(clk); /* XXX set frequency */ 236 device_printf(sc->sc_dev, "xusb_ss rate %u error %d\n", rate, error); 237 238 psc->sc_clk_ss_src = fdtbus_clock_get(faa->faa_phandle, "xusb_ss_src"); 239 if (psc->sc_clk_ss_src == NULL) { 240 printf("psc->sc_clk_ss_src %p\n", psc->sc_clk_ss_src); 241 Debugger(); 242 } 243 error = 0; 244 rate = clk_get_rate(psc->sc_clk_ss_src); 245 device_printf(sc->sc_dev, "xusb_ss_src rate %u error %d\n", rate, 246 error); 247 248 error = clk_set_rate(psc->sc_clk_ss_src, 2000000); 249 rate = clk_get_rate(psc->sc_clk_ss_src); 250 device_printf(sc->sc_dev, "xusb_ss_src rate %u error %d\n", rate, 251 error); 252 253 error = clk_set_parent(psc->sc_clk_ss_src, pll_u_480); 254 rate = clk_get_rate(psc->sc_clk_ss_src); 255 device_printf(sc->sc_dev, "ss_src rate %u error %d\n", rate, error); 256 257 error = clk_set_rate(psc->sc_clk_ss_src, 120000000); 258 rate = clk_get_rate(psc->sc_clk_ss_src); 259 device_printf(sc->sc_dev, "ss_src rate %u error %d\n", rate, error); 260 261 error = clk_enable(psc->sc_clk_ss_src); 262 device_printf(sc->sc_dev, "ss_src rate %u error %d\n", rate, error); 263 264 #if 0 265 clk = fdtbus_clock_get(faa->faa_phandle, "xusb_hs_src"); 266 error = 0; 267 rate = clk_get_rate(clk); 268 device_printf(sc->sc_dev, "rate %u error %d\n", rate, error); 269 #endif 270 271 clk = fdtbus_clock_get(faa->faa_phandle, "xusb_fs_src"); 272 error = clk_set_parent(clk, pll_u_48); 273 rate = clk_get_rate(clk); 274 error = clk_enable(clk); /* XXX set frequency */ 275 device_printf(sc->sc_dev, "rate %u error %d\n", rate, error); 276 277 rst = fdtbus_reset_get(faa->faa_phandle, "xusb_host"); 278 fdtbus_reset_deassert(rst); 279 280 rst = fdtbus_reset_get(faa->faa_phandle, "xusb_src"); 281 fdtbus_reset_deassert(rst); 282 283 rst = fdtbus_reset_get(faa->faa_phandle, "xusb_ss"); 284 fdtbus_reset_deassert(rst); 285 286 DELAY(1); 287 288 tegra_xusb_init(psc); 289 290 #if defined(TEGRA124_XUSB_BIN_STATIC) 291 tegra_xusb_mountroot(sc->sc_dev); 292 #else 293 config_mountroot(sc->sc_dev, tegra_xusb_mountroot); 294 #endif 295 } 296 297 static void 298 tegra_xusb_mountroot(device_t self) 299 { 300 struct tegra_xusb_softc * const psc = device_private(self); 301 struct xhci_softc * const sc = &psc->sc_xhci; 302 const bus_space_tag_t bst = sc->sc_iot; 303 const bus_space_handle_t ipfsh = psc->sc_bsh_ipfs; 304 struct clk *clk; 305 struct fdtbus_reset *rst; 306 uint32_t rate; 307 uint32_t val; 308 int error; 309 310 device_printf(sc->sc_dev, "%s()\n", __func__); 311 312 val = bus_space_read_4(bst, ipfsh, 0x0); 313 device_printf(sc->sc_dev, "%s ipfs 0x0 = 0x%x\n", __func__, val); 314 315 tegra_xusb_load_fw(psc); 316 device_printf(sc->sc_dev, "post fw\n"); 317 318 clk = fdtbus_clock_get(psc->sc_phandle, "xusb_falcon_src"); 319 rate = clk_get_rate(clk); 320 error = clk_enable(clk); 321 device_printf(sc->sc_dev, "rate %u error %d\n", rate, error); 322 323 clk = fdtbus_clock_get(psc->sc_phandle, "xusb_host_src"); 324 rate = clk_get_rate(clk); 325 error = clk_enable(clk); 326 device_printf(sc->sc_dev, "rate %u error %d\n", rate, error); 327 328 val = bus_space_read_4(bst, ipfsh, 0x0); 329 device_printf(sc->sc_dev, "%s ipfs 0x0 = 0x%x\n", __func__, val); 330 331 rst = fdtbus_reset_get(psc->sc_phandle, "xusb_host"); 332 fdtbus_reset_deassert(rst); 333 334 rst = fdtbus_reset_get(psc->sc_phandle, "xusb_src"); 335 fdtbus_reset_deassert(rst); 336 337 rst = fdtbus_reset_get(psc->sc_phandle, "xusb_ss"); 338 fdtbus_reset_deassert(rst); 339 340 val = csb_read_4(psc, XUSB_CSB_FALCON_CPUCTL_REG); 341 device_printf(sc->sc_dev, "XUSB_FALC_CPUCTL 0x%x\n", val); 342 343 344 error = xhci_init(sc); 345 if (error) { 346 aprint_error_dev(self, "init failed, error=%d\n", error); 347 return; 348 } 349 350 sc->sc_child = config_found(self, &sc->sc_bus, usbctlprint); 351 352 error = xusb_mailbox_send(psc, 0x01000000); 353 if (error) { 354 aprint_error_dev(self, "send failed, error=%d\n", error); 355 } 356 } 357 358 static int 359 tegra_xusb_intr_mbox(void *v) 360 { 361 struct tegra_xusb_softc * const psc = v; 362 struct xhci_softc * const sc = &psc->sc_xhci; 363 const bus_space_tag_t bst = sc->sc_iot; 364 const bus_space_handle_t fpcih = psc->sc_bsh_fpci; 365 uint32_t val; 366 uint32_t irv; 367 uint32_t msg; 368 int error; 369 370 device_printf(sc->sc_dev, "%s()\n", __func__); 371 372 irv = bus_space_read_4(bst, fpcih, T_XUSB_CFG_ARU_SMI_INTR_REG); 373 device_printf(sc->sc_dev, "XUSB_CFG_ARU_SMI_INTR 0x%x\n", irv); 374 bus_space_write_4(bst, fpcih, T_XUSB_CFG_ARU_SMI_INTR_REG, irv); 375 376 if (irv & T_XUSB_CFG_ARU_SMI_INTR_FW_HANG) 377 device_printf(sc->sc_dev, "firmware hang\n"); 378 379 msg = bus_space_read_4(bst, fpcih, T_XUSB_CFG_ARU_MAILBOX_DATA_OUT_REG); 380 device_printf(sc->sc_dev, "XUSB_CFG_ARU_MBOX_DATA_OUT 0x%x\n", msg); 381 382 val = bus_space_read_4(bst, fpcih, T_XUSB_CFG_ARU_MAILBOX_CMD_REG); 383 device_printf(sc->sc_dev, "XUSB_CFG_ARU_MBOX_CMD 0x%x\n", val); 384 val &= ~T_XUSB_CFG_ARU_MAILBOX_CMD_DEST_SMI; 385 bus_space_write_4(bst, fpcih, T_XUSB_CFG_ARU_MAILBOX_CMD_REG, val); 386 387 bool sendresp = true; 388 u_int rate; 389 390 const uint32_t data = __SHIFTOUT(msg, MAILBOX_DATA_DATA); 391 const uint8_t type = __SHIFTOUT(msg, MAILBOX_DATA_TYPE); 392 393 switch (type) { 394 case 2: 395 case 3: 396 device_printf(sc->sc_dev, "FALC_CLOCK %u\n", data * 1000); 397 break; 398 case 4: 399 case 5: 400 device_printf(sc->sc_dev, "SSPI_CLOCK %u\n", data * 1000); 401 rate = clk_get_rate(psc->sc_clk_ss_src); 402 device_printf(sc->sc_dev, "rate of psc->sc_clk_ss_src %u\n", 403 rate); 404 error = clk_set_rate(psc->sc_clk_ss_src, data * 1000); 405 if (error != 0) 406 goto clk_fail; 407 rate = clk_get_rate(psc->sc_clk_ss_src); 408 device_printf(sc->sc_dev, 409 "rate of psc->sc_clk_ss_src %u after\n", rate); 410 if (data == (rate / 1000)) { 411 msg = __SHIFTIN(128, MAILBOX_DATA_TYPE) | 412 __SHIFTIN(rate / 1000, MAILBOX_DATA_DATA); 413 } else 414 clk_fail: 415 msg = __SHIFTIN(129, MAILBOX_DATA_TYPE) | 416 __SHIFTIN(rate / 1000, MAILBOX_DATA_DATA); 417 xusb_mailbox_send(psc, msg); 418 break; 419 case 9: 420 msg = __SHIFTIN(data, MAILBOX_DATA_DATA) | 421 __SHIFTIN(128, MAILBOX_DATA_TYPE); 422 xusb_mailbox_send(psc, msg); 423 break; 424 case 6: 425 case 128: 426 case 129: 427 sendresp = false; 428 break; 429 default: 430 sendresp = false; 431 break; 432 } 433 434 if (sendresp == false) 435 bus_space_write_4(bst, fpcih, T_XUSB_CFG_ARU_MAILBOX_OWNER_REG, 436 MAILBOX_OWNER_NONE); 437 438 return irv; 439 } 440 441 static void 442 tegra_xusb_init(struct tegra_xusb_softc * const psc) 443 { 444 struct xhci_softc * const sc = &psc->sc_xhci; 445 const bus_space_tag_t bst = sc->sc_iot; 446 const bus_space_handle_t ipfsh = psc->sc_bsh_ipfs; 447 const bus_space_handle_t fpcih = psc->sc_bsh_fpci; 448 449 device_printf(sc->sc_dev, "%s()\n", __func__); 450 451 device_printf(sc->sc_dev, "%s ipfs 0x0 = 0x%x\n", __func__, 452 bus_space_read_4(bst, ipfsh, 0x0)); 453 454 device_printf(sc->sc_dev, "%s ipfs 0x40 = 0x%x\n", __func__, 455 bus_space_read_4(bst, ipfsh, 0x40)); 456 457 device_printf(sc->sc_dev, "%s ipfs 0x80 = 0x%x\n", __func__, 458 bus_space_read_4(bst, ipfsh, 0x80)); 459 /* FPCI_BAR0_START and FPCI_BAR0_ACCESS_TYPE */ 460 bus_space_write_4(bst, ipfsh, 0x80, 0x00100000); 461 device_printf(sc->sc_dev, "%s ipfs 0x80 = 0x%x\n", __func__, 462 bus_space_read_4(bst, ipfsh, 0x80)); 463 464 device_printf(sc->sc_dev, "%s ipfs 0x180 = 0x%x\n", __func__, 465 bus_space_read_4(bst, ipfsh, 0x180)); 466 /* EN_FPCI */ 467 tegra_reg_set_clear(bst, ipfsh, 0x180, 1, 0); 468 device_printf(sc->sc_dev, "%s ipfs 0x180 = 0x%x\n", __func__, 469 bus_space_read_4(bst, ipfsh, 0x180)); 470 471 device_printf(sc->sc_dev, "%s fpci PCI_COMMAND_STATUS_REG = 0x%x\n", 472 __func__, bus_space_read_4(bst, fpcih, PCI_COMMAND_STATUS_REG)); 473 tegra_reg_set_clear(bst, fpcih, PCI_COMMAND_STATUS_REG, 474 PCI_COMMAND_MASTER_ENABLE|PCI_COMMAND_MEM_ENABLE, 0x0); 475 device_printf(sc->sc_dev, "%s fpci PCI_COMMAND_STATUS_REG = 0x%x\n", 476 __func__, bus_space_read_4(bst, fpcih, PCI_COMMAND_STATUS_REG)); 477 478 device_printf(sc->sc_dev, "%s fpci PCI_BAR0 = 0x%x\n", __func__, 479 bus_space_read_4(bst, fpcih, PCI_BAR0)); 480 /* match FPCI BAR0 to above */ 481 bus_space_write_4(bst, fpcih, PCI_BAR0, 0x10000000); 482 device_printf(sc->sc_dev, "%s fpci PCI_BAR0 = 0x%x\n", __func__, 483 bus_space_read_4(bst, fpcih, PCI_BAR0)); 484 485 device_printf(sc->sc_dev, "%s ipfs 0x188 = 0x%x\n", __func__, 486 bus_space_read_4(bst, ipfsh, 0x188)); 487 tegra_reg_set_clear(bst, ipfsh, 0x188, __BIT(16), 0); 488 device_printf(sc->sc_dev, "%s ipfs 0x188 = 0x%x\n", __func__, 489 bus_space_read_4(bst, ipfsh, 0x188)); 490 491 device_printf(sc->sc_dev, "%s fpci 0x1bc = 0x%x\n", __func__, 492 bus_space_read_4(bst, fpcih, 0x1bc)); 493 bus_space_write_4(bst, fpcih, 0x1bc, 0x80); 494 device_printf(sc->sc_dev, "%s fpci 0x1bc = 0x%x\n", __func__, 495 bus_space_read_4(bst, fpcih, 0x1bc)); 496 } 497 498 static int 499 fw_dma_alloc(struct tegra_xusb_softc * const psc, size_t size, size_t align, 500 struct fw_dma * const p) 501 { 502 struct xhci_softc * const sc = &psc->sc_xhci; 503 const bus_dma_tag_t dmat = sc->sc_bus.ub_dmatag; 504 int err; 505 506 p->size = size; 507 err = bus_dmamem_alloc(dmat, p->size, align, 0, p->segs, 508 sizeof(p->segs) / sizeof(p->segs[0]), &p->nsegs, BUS_DMA_NOWAIT); 509 if (err) 510 return err; 511 err = bus_dmamem_map(dmat, p->segs, p->nsegs, p->size, &p->addr, 512 BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 513 if (err) 514 goto free; 515 err = bus_dmamap_create(dmat, p->size, 1, p->size, 0, BUS_DMA_NOWAIT, 516 &p->map); 517 if (err) 518 goto unmap; 519 err = bus_dmamap_load(dmat, p->map, p->addr, p->size, NULL, 520 BUS_DMA_NOWAIT); 521 if (err) 522 goto destroy; 523 524 return 0; 525 526 destroy: 527 bus_dmamap_destroy(dmat, p->map); 528 unmap: 529 bus_dmamem_unmap(dmat, p->addr, p->size); 530 free: 531 bus_dmamem_free(dmat, p->segs, p->nsegs); 532 533 return err; 534 } 535 536 #if !defined(TEGRA124_XUSB_BIN_STATIC) 537 static void 538 fw_dma_free(struct tegra_xusb_softc * const psc, struct fw_dma * const p) 539 { 540 const struct xhci_softc * const sc = &psc->sc_xhci; 541 const bus_dma_tag_t dmat = sc->sc_bus.ub_dmatag; 542 543 bus_dmamap_unload(dmat, p->map); 544 bus_dmamap_destroy(dmat, p->map); 545 bus_dmamem_unmap(dmat, p->addr, p->size); 546 bus_dmamem_free(dmat, p->segs, p->nsegs); 547 } 548 #endif 549 550 #define FWHEADER_BOOT_CODETAG 8 551 #define FWHEADER_BOOT_CODESIZE 12 552 #define FWHEADER_FWIMG_LEN 100 553 #define FWHEADER__LEN 256 554 555 static void 556 tegra_xusb_load_fw(struct tegra_xusb_softc * const psc) 557 { 558 struct xhci_softc * const sc = &psc->sc_xhci; 559 #if !defined(TEGRA124_XUSB_BIN_STATIC) 560 firmware_handle_t fw; 561 #endif 562 int error; 563 size_t firmware_size; 564 void * firmware_image; 565 const uint8_t *header; 566 567 #if defined(TEGRA124_XUSB_BIN_STATIC) 568 firmware_size = (uintptr_t)&_binary_tegra124_xusb_bin_size; 569 #else 570 if ((error = firmware_open("nvidia/tegra124", "xusb.bin", &fw)) != 0) { 571 aprint_error_dev(sc->sc_dev, 572 "could not open firmware file %s: %d\n", "xusb.bin", error); 573 return; 574 } 575 firmware_size = firmware_get_size(fw); 576 #endif 577 578 error = fw_dma_alloc(psc, firmware_size, PAGE_SIZE, &psc->sc_fw_dma); 579 if (error != 0) { 580 #if !defined(TEGRA124_XUSB_BIN_STATIC) 581 firmware_close(fw); 582 #endif 583 return; 584 } 585 586 firmware_image = psc->sc_fw_dma.addr; 587 device_printf(sc->sc_dev, "blob %p len %zu\n", firmware_image, 588 firmware_size); 589 590 #if defined(TEGRA124_XUSB_BIN_STATIC) 591 memcpy(firmware_image, _binary_tegra124_xusb_bin_start, firmware_size); 592 #else 593 error = firmware_read(fw, 0, firmware_image, firmware_size); 594 if (error != 0) { 595 fw_dma_free(psc, &psc->sc_fw_dma); 596 firmware_close(fw); 597 return; 598 } 599 firmware_close(fw); 600 #endif 601 602 header = firmware_image; 603 604 const uint32_t fwimg_len = le32dec(&header[FWHEADER_FWIMG_LEN]); 605 const uint32_t boot_codetag = le32dec(&header[FWHEADER_BOOT_CODETAG]); 606 const uint32_t boot_codesize = le32dec(&header[FWHEADER_BOOT_CODESIZE]); 607 608 if (fwimg_len != firmware_size) 609 device_printf(sc->sc_dev, "fwimg_len mismatch %u != %zu\n", 610 fwimg_len, firmware_size); 611 612 bus_dmamap_sync(sc->sc_bus.ub_dmatag, psc->sc_fw_dma.map, 0, 613 firmware_size, BUS_DMASYNC_PREWRITE); 614 615 device_printf(sc->sc_dev, "XUSB_FALC_CPUCTL 0x%x\n", 616 csb_read_4(psc, XUSB_CSB_FALCON_CPUCTL_REG)); 617 device_printf(sc->sc_dev, "XUSB_CSB_MP_ILOAD_BASE_LO 0x%x\n", 618 csb_read_4(psc, XUSB_CSB_MEMPOOL_ILOAD_BASE_LO_REG)); 619 620 device_printf(sc->sc_dev, "XUSB_CSB_MP_ILOAD_ATTR 0x%x\n", 621 csb_read_4(psc, XUSB_CSB_MEMPOOL_ILOAD_ATTR_REG)); 622 csb_write_4(psc, XUSB_CSB_MEMPOOL_ILOAD_ATTR_REG, 623 fwimg_len); 624 device_printf(sc->sc_dev, "XUSB_CSB_MP_ILOAD_ATTR 0x%x\n", 625 csb_read_4(psc, XUSB_CSB_MEMPOOL_ILOAD_ATTR_REG)); 626 627 const uint64_t fwbase = psc->sc_fw_dma.map->dm_segs[0].ds_addr + 628 FWHEADER__LEN; 629 630 csb_write_4(psc, XUSB_CSB_MEMPOOL_ILOAD_BASE_HI_REG, fwbase >> 32); 631 csb_write_4(psc, XUSB_CSB_MEMPOOL_ILOAD_BASE_LO_REG, fwbase); 632 device_printf(sc->sc_dev, "XUSB_CSB_MP_ILOAD_BASE_LO 0x%x\n", 633 csb_read_4(psc, XUSB_CSB_MEMPOOL_ILOAD_BASE_LO_REG)); 634 device_printf(sc->sc_dev, "XUSB_CSB_MP_ILOAD_BASE_HI 0x%x\n", 635 csb_read_4(psc, XUSB_CSB_MEMPOOL_ILOAD_BASE_HI_REG)); 636 637 device_printf(sc->sc_dev, "XUSB_CSB_MP_APMAP 0x%x\n", 638 csb_read_4(psc, XUSB_CSB_MEMPOOL_APMAP_REG)); 639 csb_write_4(psc, XUSB_CSB_MEMPOOL_APMAP_REG, 640 XUSB_CSB_MEMPOOL_APMAP_BOOTPATH); 641 device_printf(sc->sc_dev, "XUSB_CSB_MP_APMAP 0x%x\n", 642 csb_read_4(psc, XUSB_CSB_MEMPOOL_APMAP_REG)); 643 644 device_printf(sc->sc_dev, "XUSB_CSB_MP_L2IMEMOP_TRIG 0x%x\n", 645 csb_read_4(psc, XUSB_CSB_MEMPOOL_L2IMEMOP_TRIG_REG)); 646 csb_write_4(psc, XUSB_CSB_MEMPOOL_L2IMEMOP_TRIG_REG, 647 __SHIFTIN(ACTION_L2IMEM_INVALIDATE_ALL, 648 XUSB_CSB_MEMPOOL_L2IMEMOP_TRIG_ACTION)); 649 device_printf(sc->sc_dev, "XUSB_CSB_MP_L2IMEMOP_TRIG 0x%x\n", 650 csb_read_4(psc, XUSB_CSB_MEMPOOL_L2IMEMOP_TRIG_REG)); 651 652 const u_int code_tag_blocks = 653 howmany(boot_codetag, IMEM_BLOCK_SIZE); 654 const u_int code_size_blocks = 655 howmany(boot_codesize, IMEM_BLOCK_SIZE); 656 const u_int code_blocks = code_tag_blocks + code_size_blocks; 657 658 device_printf(sc->sc_dev, "XUSB_CSB_MP_L2IMEMOP_SIZE 0x%x\n", 659 csb_read_4(psc, XUSB_CSB_MEMPOOL_L2IMEMOP_SIZE_REG)); 660 csb_write_4(psc, XUSB_CSB_MEMPOOL_L2IMEMOP_SIZE_REG, 661 __SHIFTIN(code_tag_blocks, 662 XUSB_CSB_MEMPOOL_L2IMEMOP_SIZE_SRC_OFFSET) | 663 __SHIFTIN(code_size_blocks, 664 XUSB_CSB_MEMPOOL_L2IMEMOP_SIZE_SRC_COUNT)); 665 device_printf(sc->sc_dev, "XUSB_CSB_MP_L2IMEMOP_SIZE 0x%x\n", 666 csb_read_4(psc, XUSB_CSB_MEMPOOL_L2IMEMOP_SIZE_REG)); 667 668 device_printf(sc->sc_dev, "XUSB_CSB_MP_L2IMEMOP_TRIG 0x%x\n", 669 csb_read_4(psc, XUSB_CSB_MEMPOOL_L2IMEMOP_TRIG_REG)); 670 csb_write_4(psc, XUSB_CSB_MEMPOOL_L2IMEMOP_TRIG_REG, 671 __SHIFTIN(ACTION_L2IMEM_LOAD_LOCKED_RESULT, 672 XUSB_CSB_MEMPOOL_L2IMEMOP_TRIG_ACTION)); 673 device_printf(sc->sc_dev, "XUSB_CSB_MP_L2IMEMOP_TRIG 0x%x\n", 674 csb_read_4(psc, XUSB_CSB_MEMPOOL_L2IMEMOP_TRIG_REG)); 675 676 device_printf(sc->sc_dev, "XUSB_FALC_IMFILLCTL 0x%x\n", 677 csb_read_4(psc, XUSB_CSB_FALCON_IMFILLCTL_REG)); 678 csb_write_4(psc, XUSB_CSB_FALCON_IMFILLCTL_REG, code_size_blocks); 679 device_printf(sc->sc_dev, "XUSB_FALC_IMFILLCTL 0x%x\n", 680 csb_read_4(psc, XUSB_CSB_FALCON_IMFILLCTL_REG)); 681 682 device_printf(sc->sc_dev, "XUSB_FALC_IMFILLRNG1 0x%x\n", 683 csb_read_4(psc, XUSB_CSB_FALCON_IMFILLRNG1_REG)); 684 csb_write_4(psc, XUSB_CSB_FALCON_IMFILLRNG1_REG, 685 __SHIFTIN(code_tag_blocks, XUSB_CSB_FALCON_IMFILLRNG1_TAG_LO) | 686 __SHIFTIN(code_blocks, XUSB_CSB_FALCON_IMFILLRNG1_TAG_HI)); 687 device_printf(sc->sc_dev, "XUSB_FALC_IMFILLRNG1 0x%x\n", 688 csb_read_4(psc, XUSB_CSB_FALCON_IMFILLRNG1_REG)); 689 690 device_printf(sc->sc_dev, "XUSB_FALC_DMACTL 0x%x\n", 691 csb_read_4(psc, XUSB_CSB_FALCON_DMACTL_REG)); 692 csb_write_4(psc, XUSB_CSB_FALCON_DMACTL_REG, 0); 693 device_printf(sc->sc_dev, "XUSB_FALC_DMACTL 0x%x\n", 694 csb_read_4(psc, XUSB_CSB_FALCON_DMACTL_REG)); 695 696 device_printf(sc->sc_dev, "XUSB_FALC_BOOTVEC 0x%x\n", 697 csb_read_4(psc, XUSB_CSB_FALCON_BOOTVEC_REG)); 698 csb_write_4(psc, XUSB_CSB_FALCON_BOOTVEC_REG, 699 boot_codetag); 700 device_printf(sc->sc_dev, "XUSB_FALC_BOOTVEC 0x%x\n", 701 csb_read_4(psc, XUSB_CSB_FALCON_BOOTVEC_REG)); 702 703 device_printf(sc->sc_dev, "XUSB_FALC_CPUCTL 0x%x\n", 704 csb_read_4(psc, XUSB_CSB_FALCON_CPUCTL_REG)); 705 csb_write_4(psc, XUSB_CSB_FALCON_CPUCTL_REG, 706 XUSB_CSB_FALCON_CPUCTL_STARTCPU); 707 device_printf(sc->sc_dev, "XUSB_FALC_CPUCTL 0x%x\n", 708 csb_read_4(psc, XUSB_CSB_FALCON_CPUCTL_REG)); 709 } 710 711 static uint32_t 712 csb_read_4(struct tegra_xusb_softc * const psc, bus_size_t csb_offset) 713 { 714 const uint32_t range = __SHIFTOUT(csb_offset, XUSB_CSB_RANGE); 715 const bus_size_t offset = __SHIFTOUT(csb_offset, XUSB_CSB_OFFSET); 716 const bus_space_tag_t bst = psc->sc_xhci.sc_iot; 717 const bus_space_handle_t fpcih = psc->sc_bsh_fpci; 718 719 bus_space_write_4(bst, fpcih, T_XUSB_CFG_ARU_C11_CSBRANGE_REG, range); 720 return bus_space_read_4(bst, fpcih, T_XUSB_CFG_CSB_BASE_ADDR + offset); 721 } 722 723 static void 724 csb_write_4(struct tegra_xusb_softc * const psc, bus_size_t csb_offset, 725 uint32_t value) 726 { 727 const uint32_t range = __SHIFTOUT(csb_offset, XUSB_CSB_RANGE); 728 const bus_size_t offset = __SHIFTOUT(csb_offset, XUSB_CSB_OFFSET); 729 const bus_space_tag_t bst = psc->sc_xhci.sc_iot; 730 const bus_space_handle_t fpcih = psc->sc_bsh_fpci; 731 732 bus_space_write_4(bst, fpcih, T_XUSB_CFG_ARU_C11_CSBRANGE_REG, range); 733 bus_space_write_4(bst, fpcih, T_XUSB_CFG_CSB_BASE_ADDR + offset, value); 734 } 735 736 static int 737 xusb_mailbox_send(struct tegra_xusb_softc * const psc, uint32_t msg) 738 { 739 struct xhci_softc * const sc = &psc->sc_xhci; 740 const bus_space_tag_t bst = psc->sc_xhci.sc_iot; 741 const bus_space_handle_t fpcih = psc->sc_bsh_fpci; 742 uint32_t val; 743 bool wait = false; 744 745 const uint8_t type = __SHIFTOUT(msg, MAILBOX_DATA_TYPE); 746 747 if (!(type == 128 || type == 129)) { 748 val = bus_space_read_4(bst, fpcih, 749 T_XUSB_CFG_ARU_MAILBOX_OWNER_REG); 750 device_printf(sc->sc_dev, "XUSB_CFG_ARU_MBOX_OWNER 0x%x\n", 751 val); 752 if (val != MAILBOX_OWNER_NONE) { 753 return EBUSY; 754 } 755 756 bus_space_write_4(bst, fpcih, T_XUSB_CFG_ARU_MAILBOX_OWNER_REG, 757 MAILBOX_OWNER_SW); 758 759 val = bus_space_read_4(bst, fpcih, 760 T_XUSB_CFG_ARU_MAILBOX_OWNER_REG); 761 device_printf(sc->sc_dev, "XUSB_CFG_ARU_MBOX_OWNER 0x%x\n", 762 val); 763 if (val != MAILBOX_OWNER_SW) { 764 return EBUSY; 765 } 766 767 wait = true; 768 } 769 770 bus_space_write_4(bst, fpcih, T_XUSB_CFG_ARU_MAILBOX_DATA_IN_REG, msg); 771 772 tegra_reg_set_clear(bst, fpcih, T_XUSB_CFG_ARU_MAILBOX_CMD_REG, 773 T_XUSB_CFG_ARU_MAILBOX_CMD_INT_EN | 774 T_XUSB_CFG_ARU_MAILBOX_CMD_DEST_FALCON, 0); 775 776 if (wait) { 777 778 for (u_int i = 0; i < 2500; i++) { 779 val = bus_space_read_4(bst, fpcih, 780 T_XUSB_CFG_ARU_MAILBOX_OWNER_REG); 781 device_printf(sc->sc_dev, 782 "XUSB_CFG_ARU_MBOX_OWNER 0x%x\n", val); 783 if (val == MAILBOX_OWNER_NONE) { 784 break; 785 } 786 DELAY(10); 787 } 788 789 val = bus_space_read_4(bst, fpcih, 790 T_XUSB_CFG_ARU_MAILBOX_OWNER_REG); 791 device_printf(sc->sc_dev, 792 "XUSB_CFG_ARU_MBOX_OWNER 0x%x\n", val); 793 if (val != MAILBOX_OWNER_NONE) { 794 device_printf(sc->sc_dev, 795 "timeout, XUSB_CFG_ARU_MBOX_OWNER 0x%x\n", val); 796 } 797 } 798 799 return 0; 800 } 801
Indexes created Fri Sep 26 20:09:58 GMT 2025