tegra_xusb.c revision 1.10
1 /* $NetBSD: tegra_xusb.c,v 1.10 2017/09/24 20:09:22 jmcneill Exp $ */ 2 3 /* 4 * Copyright (c) 2016 Jonathan A. Kollasch 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR 20 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 21 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 22 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 23 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 25 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 26 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include "locators.h" 30 #include "opt_tegra.h" 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: tegra_xusb.c,v 1.10 2017/09/24 20:09:22 jmcneill Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/bus.h> 37 #include <sys/device.h> 38 #include <sys/intr.h> 39 #include <sys/systm.h> 40 #include <sys/kernel.h> 41 42 #include <arm/nvidia/tegra_reg.h> 43 #include <arm/nvidia/tegra_var.h> 44 #include <arm/nvidia/tegra_xusbpad.h> 45 #include <arm/nvidia/tegra_xusbreg.h> 46 #include <arm/nvidia/tegra_pmcreg.h> 47 48 #include <dev/pci/pcireg.h> 49 50 #include <dev/fdt/fdtvar.h> 51 52 #include <dev/firmload.h> 53 54 #include <dev/usb/usb.h> 55 #include <dev/usb/usbdi.h> 56 #include <dev/usb/usbdivar.h> 57 #include <dev/usb/usb_mem.h> 58 59 #include <dev/usb/xhcireg.h> 60 #include <dev/usb/xhcivar.h> 61 62 #ifdef TEGRA_XUSB_DEBUG 63 int tegra_xusb_debug = 1; 64 #else 65 int tegra_xusb_debug = 0; 66 #endif 67 68 #define DPRINTF(...) if (tegra_xusb_debug) device_printf(__VA_ARGS__) 69 70 static int tegra_xusb_match(device_t, cfdata_t, void *); 71 static void tegra_xusb_attach(device_t, device_t, void *); 72 static void tegra_xusb_mountroot(device_t); 73 74 static int tegra_xusb_intr_mbox(void *); 75 76 #ifdef TEGRA124_XUSB_BIN_STATIC 77 extern const char _binary_tegra124_xusb_bin_size[]; 78 extern const char _binary_tegra124_xusb_bin_start[]; 79 #endif 80 81 #ifdef TEGRA210_XUSB_BIN_STATIC 82 extern const char _binary_tegra210_xusb_bin_size[]; 83 extern const char _binary_tegra210_xusb_bin_start[]; 84 #endif 85 86 enum xusb_type { 87 XUSB_T124 = 1, 88 XUSB_T210 89 }; 90 91 static const struct of_compat_data compat_data[] = { 92 { "nvidia,tegra124-xusb", XUSB_T124 }, 93 { "nvidia,tegra210-xusb", XUSB_T210 }, 94 { NULL } 95 }; 96 97 struct fw_dma { 98 bus_dmamap_t map; 99 void * addr; 100 bus_dma_segment_t segs[1]; 101 int nsegs; 102 size_t size; 103 }; 104 105 struct tegra_xusb_softc { 106 struct xhci_softc sc_xhci; 107 int sc_phandle; 108 bus_space_handle_t sc_bsh_xhci; 109 bus_space_handle_t sc_bsh_fpci; 110 bus_space_handle_t sc_bsh_ipfs; 111 void *sc_ih; 112 void *sc_ih_mbox; 113 struct fw_dma sc_fw_dma; 114 struct clk *sc_clk_ss_src; 115 enum xusb_type sc_type; 116 }; 117 118 static uint32_t csb_read_4(struct tegra_xusb_softc * const, bus_size_t); 119 static void csb_write_4(struct tegra_xusb_softc * const, bus_size_t, 120 uint32_t); 121 122 static void tegra_xusb_init(struct tegra_xusb_softc * const); 123 static int tegra_xusb_open_fw(struct tegra_xusb_softc * const); 124 static int tegra_xusb_load_fw(struct tegra_xusb_softc * const, void *, 125 size_t); 126 static void tegra_xusb_init_regulators(struct tegra_xusb_softc * const); 127 128 static int xusb_mailbox_send(struct tegra_xusb_softc * const, uint32_t); 129 130 CFATTACH_DECL_NEW(tegra_xusb, sizeof(struct tegra_xusb_softc), 131 tegra_xusb_match, tegra_xusb_attach, NULL, NULL); 132 133 static int 134 tegra_xusb_match(device_t parent, cfdata_t cf, void *aux) 135 { 136 struct fdt_attach_args * const faa = aux; 137 138 return of_match_compat_data(faa->faa_phandle, compat_data); 139 } 140 141 #define tegra_xusb_attach_check(sc, cond, fmt, ...) \ 142 do { \ 143 if (cond) { \ 144 aprint_error_dev(sc->sc_dev, fmt, ## __VA_ARGS__); \ 145 return; \ 146 } \ 147 } while (0) 148 149 static void 150 tegra_xusb_attach(device_t parent, device_t self, void *aux) 151 { 152 struct tegra_xusb_softc * const psc = device_private(self); 153 struct xhci_softc * const sc = &psc->sc_xhci; 154 struct fdt_attach_args * const faa = aux; 155 bool wait_for_root = true; 156 char intrstr[128]; 157 bus_addr_t addr; 158 bus_size_t size; 159 struct fdtbus_reset *rst; 160 struct clk *clk; 161 uint32_t rate; 162 int error; 163 164 aprint_naive("\n"); 165 aprint_normal(": XUSB\n"); 166 167 sc->sc_dev = self; 168 sc->sc_iot = faa->faa_bst; 169 sc->sc_bus.ub_hcpriv = sc; 170 sc->sc_bus.ub_dmatag = faa->faa_dmat; 171 psc->sc_phandle = faa->faa_phandle; 172 psc->sc_type = of_search_compatible(faa->faa_phandle, compat_data)->data; 173 174 if (fdtbus_get_reg(faa->faa_phandle, 0, &addr, &size) != 0) { 175 aprint_error(": couldn't get registers\n"); 176 return; 177 } 178 error = bus_space_map(sc->sc_iot, addr, size, 0, &sc->sc_ioh); 179 if (error) { 180 aprint_error(": couldn't map %#llx: %d", (uint64_t)addr, error); 181 return; 182 } 183 DPRINTF(sc->sc_dev, "mapped %#llx\n", (uint64_t)addr); 184 185 if (fdtbus_get_reg(faa->faa_phandle, 1, &addr, &size) != 0) { 186 aprint_error(": couldn't get registers\n"); 187 return; 188 } 189 error = bus_space_map(sc->sc_iot, addr, size, 0, &psc->sc_bsh_fpci); 190 if (error) { 191 aprint_error(": couldn't map %#llx: %d", (uint64_t)addr, error); 192 return; 193 } 194 DPRINTF(sc->sc_dev, "mapped %#llx\n", (uint64_t)addr); 195 196 if (fdtbus_get_reg(faa->faa_phandle, 2, &addr, &size) != 0) { 197 aprint_error(": couldn't get registers\n"); 198 return; 199 } 200 error = bus_space_map(sc->sc_iot, addr, size, 0, &psc->sc_bsh_ipfs); 201 if (error) { 202 aprint_error(": couldn't map %#llx: %d", (uint64_t)addr, error); 203 return; 204 } 205 DPRINTF(sc->sc_dev, "mapped %#llx\n", (uint64_t)addr); 206 207 if (!fdtbus_intr_str(faa->faa_phandle, 0, intrstr, sizeof(intrstr))) { 208 aprint_error_dev(self, "failed to decode interrupt\n"); 209 return; 210 } 211 212 psc->sc_ih = fdtbus_intr_establish(faa->faa_phandle, 0, IPL_USB, 213 0, xhci_intr, sc); 214 if (psc->sc_ih == NULL) { 215 aprint_error_dev(self, "failed to establish interrupt on %s\n", 216 intrstr); 217 return; 218 } 219 aprint_normal_dev(self, "interrupting on %s\n", intrstr); 220 221 if (!fdtbus_intr_str(faa->faa_phandle, 1, intrstr, sizeof(intrstr))) { 222 aprint_error_dev(self, "failed to decode interrupt\n"); 223 return; 224 } 225 226 psc->sc_ih_mbox = fdtbus_intr_establish(faa->faa_phandle, 1, IPL_VM, 227 0, tegra_xusb_intr_mbox, psc); 228 if (psc->sc_ih_mbox == NULL) { 229 aprint_error_dev(self, "failed to establish interrupt on %s\n", 230 intrstr); 231 return; 232 } 233 aprint_normal_dev(self, "interrupting on %s\n", intrstr); 234 235 /* Enable XUSB power rails */ 236 237 tegra_pmc_power(PMC_PARTID_XUSBC, true); /* Host/USB2.0 */ 238 tegra_pmc_power(PMC_PARTID_XUSBA, true); /* SuperSpeed */ 239 240 /* Enable XUSB clocks */ 241 242 clk = fdtbus_clock_get(faa->faa_phandle, "pll_e"); 243 rate = clk_get_rate(clk); 244 error = clk_enable(clk); /* XXX set frequency */ 245 DPRINTF(sc->sc_dev, "rate %u error %d\n", rate, error); 246 tegra_xusb_attach_check(sc, error, "failed to enable pll_e clock"); 247 248 clk = fdtbus_clock_get(faa->faa_phandle, "xusb_host_src"); 249 rate = clk_get_rate(clk); 250 DPRINTF(sc->sc_dev, "rate %u error %d\n", rate, error); 251 error = clk_set_rate(clk, 102000000); 252 tegra_xusb_attach_check(sc, error, "failed to set xusb_host_src clock rate"); 253 254 rate = clk_get_rate(clk); 255 error = clk_enable(clk); /* XXX set frequency */ 256 DPRINTF(sc->sc_dev, "rate %u error %d\n", rate, error); 257 tegra_xusb_attach_check(sc, error, "failed to enable xusb_host_src clock"); 258 259 clk = fdtbus_clock_get(faa->faa_phandle, "xusb_falcon_src"); 260 rate = clk_get_rate(clk); 261 DPRINTF(sc->sc_dev, "rate %u error %d\n", rate, error); 262 error = clk_set_rate(clk, 204000000); 263 tegra_xusb_attach_check(sc, error, "failed to set xusb_falcon_src clock rate"); 264 265 rate = clk_get_rate(clk); 266 error = clk_enable(clk); 267 DPRINTF(sc->sc_dev, "rate %u error %d\n", rate, error); 268 tegra_xusb_attach_check(sc, error, "failed to enable xusb_falcon_src clock"); 269 270 clk = fdtbus_clock_get(faa->faa_phandle, "xusb_host"); 271 rate = clk_get_rate(clk); 272 error = clk_enable(clk); /* XXX set frequency */ 273 DPRINTF(sc->sc_dev, "rate %u error %d\n", rate, error); 274 275 clk = fdtbus_clock_get(faa->faa_phandle, "xusb_ss"); 276 rate = clk_get_rate(clk); 277 error = clk_enable(clk); /* XXX set frequency */ 278 DPRINTF(sc->sc_dev, "xusb_ss rate %u error %d\n", rate, error); 279 tegra_xusb_attach_check(sc, error, "failed to enable xusb_ss clock"); 280 281 psc->sc_clk_ss_src = fdtbus_clock_get(faa->faa_phandle, "xusb_ss_src"); 282 tegra_xusb_attach_check(sc, psc->sc_clk_ss_src == NULL, 283 "failed to get xusb_ss_src clock"); 284 285 if (psc->sc_type == XUSB_T124) { 286 rate = clk_get_rate(psc->sc_clk_ss_src); 287 DPRINTF(sc->sc_dev, "xusb_ss_src rate %u\n", rate); 288 error = clk_set_rate(psc->sc_clk_ss_src, 2000000); 289 rate = clk_get_rate(psc->sc_clk_ss_src); 290 DPRINTF(sc->sc_dev, "xusb_ss_src rate %u error %d\n", rate, error); 291 tegra_xusb_attach_check(sc, error, "failed to get xusb_ss_src clock rate"); 292 293 rate = clk_get_rate(psc->sc_clk_ss_src); 294 DPRINTF(sc->sc_dev, "ss_src rate %u\n", rate); 295 tegra_xusb_attach_check(sc, error, "failed to set xusb_ss_src clock rate"); 296 297 error = clk_set_rate(psc->sc_clk_ss_src, 120000000); 298 rate = clk_get_rate(psc->sc_clk_ss_src); 299 DPRINTF(sc->sc_dev, "ss_src rate %u error %d\n", rate, error); 300 tegra_xusb_attach_check(sc, error, "failed to get xusb_ss_src clock rate"); 301 } 302 303 rate = clk_get_rate(psc->sc_clk_ss_src); 304 error = clk_enable(psc->sc_clk_ss_src); 305 DPRINTF(sc->sc_dev, "ss_src rate %u error %d\n", rate, error); 306 tegra_xusb_attach_check(sc, error, "failed to enable xusb_ss_src clock"); 307 308 #if 0 309 clk = fdtbus_clock_get(faa->faa_phandle, "xusb_hs_src"); 310 error = 0; 311 rate = clk_get_rate(clk); 312 DPRINTF(sc->sc_dev, "rate %u error %d\n", rate, error); 313 #endif 314 315 clk = fdtbus_clock_get(faa->faa_phandle, "xusb_fs_src"); 316 rate = clk_get_rate(clk); 317 error = clk_enable(clk); /* XXX set frequency */ 318 DPRINTF(sc->sc_dev, "rate %u error %d\n", rate, error); 319 tegra_xusb_attach_check(sc, error, "failed to enable xusb_fs_src clock"); 320 321 rst = fdtbus_reset_get(faa->faa_phandle, "xusb_host"); 322 fdtbus_reset_deassert(rst); 323 324 rst = fdtbus_reset_get(faa->faa_phandle, "xusb_src"); 325 fdtbus_reset_deassert(rst); 326 327 rst = fdtbus_reset_get(faa->faa_phandle, "xusb_ss"); 328 fdtbus_reset_deassert(rst); 329 330 DELAY(1); 331 332 tegra_xusb_init_regulators(psc); 333 334 tegra_xusb_init(psc); 335 336 #if defined(TEGRA124_XUSB_BIN_STATIC) 337 if (psc->sc_type == XUSB_T124) 338 wait_for_root = false; 339 #endif 340 #if defined(TEGRA210_XUSB_BIN_STATIC) 341 if (psc->sc_type == XUSB_T210) 342 wait_for_root = false; 343 #endif 344 345 if (wait_for_root) 346 config_mountroot(sc->sc_dev, tegra_xusb_mountroot); 347 else 348 tegra_xusb_mountroot(sc->sc_dev); 349 } 350 351 static void 352 tegra_xusb_mountroot(device_t self) 353 { 354 struct tegra_xusb_softc * const psc = device_private(self); 355 struct xhci_softc * const sc = &psc->sc_xhci; 356 const bus_space_tag_t bst = sc->sc_iot; 357 const bus_space_handle_t ipfsh = psc->sc_bsh_ipfs; 358 struct clk *clk; 359 struct fdtbus_reset *rst; 360 uint32_t rate; 361 uint32_t val; 362 int error; 363 364 DPRINTF(sc->sc_dev, "%s()\n", __func__); 365 366 val = bus_space_read_4(bst, ipfsh, 0x0); 367 DPRINTF(sc->sc_dev, "%s ipfs 0x0 = 0x%x\n", __func__, val); 368 369 if (tegra_xusb_open_fw(psc) != 0) 370 return; 371 DPRINTF(sc->sc_dev, "post fw\n"); 372 373 tegra_xusbpad_xhci_enable(); 374 375 clk = fdtbus_clock_get(psc->sc_phandle, "xusb_falcon_src"); 376 rate = clk_get_rate(clk); 377 error = clk_enable(clk); 378 DPRINTF(sc->sc_dev, "rate %u error %d\n", rate, error); 379 380 clk = fdtbus_clock_get(psc->sc_phandle, "xusb_host_src"); 381 rate = clk_get_rate(clk); 382 error = clk_enable(clk); 383 DPRINTF(sc->sc_dev, "rate %u error %d\n", rate, error); 384 385 val = bus_space_read_4(bst, ipfsh, 0x0); 386 DPRINTF(sc->sc_dev, "%s ipfs 0x0 = 0x%x\n", __func__, val); 387 388 rst = fdtbus_reset_get(psc->sc_phandle, "xusb_host"); 389 fdtbus_reset_deassert(rst); 390 391 rst = fdtbus_reset_get(psc->sc_phandle, "xusb_src"); 392 fdtbus_reset_deassert(rst); 393 394 rst = fdtbus_reset_get(psc->sc_phandle, "xusb_ss"); 395 fdtbus_reset_deassert(rst); 396 397 val = csb_read_4(psc, XUSB_CSB_FALCON_CPUCTL_REG); 398 DPRINTF(sc->sc_dev, "XUSB_FALC_CPUCTL 0x%x\n", val); 399 400 401 error = xhci_init(sc); 402 if (error) { 403 aprint_error_dev(self, "init failed, error=%d\n", error); 404 return; 405 } 406 407 sc->sc_child = config_found(self, &sc->sc_bus, usbctlprint); 408 409 sc->sc_child2 = config_found(self, &sc->sc_bus2, usbctlprint); 410 411 error = xusb_mailbox_send(psc, 0x01000000); 412 if (error) { 413 aprint_error_dev(self, "send failed, error=%d\n", error); 414 } 415 } 416 417 static int 418 tegra_xusb_intr_mbox(void *v) 419 { 420 struct tegra_xusb_softc * const psc = v; 421 struct xhci_softc * const sc = &psc->sc_xhci; 422 const bus_space_tag_t bst = sc->sc_iot; 423 const bus_space_handle_t fpcih = psc->sc_bsh_fpci; 424 uint32_t val; 425 uint32_t irv; 426 uint32_t msg; 427 int error; 428 429 DPRINTF(sc->sc_dev, "%s()\n", __func__); 430 431 irv = bus_space_read_4(bst, fpcih, T_XUSB_CFG_ARU_SMI_INTR_REG); 432 DPRINTF(sc->sc_dev, "XUSB_CFG_ARU_SMI_INTR 0x%x\n", irv); 433 bus_space_write_4(bst, fpcih, T_XUSB_CFG_ARU_SMI_INTR_REG, irv); 434 435 if (irv & T_XUSB_CFG_ARU_SMI_INTR_FW_HANG) 436 aprint_error_dev(sc->sc_dev, "firmware hang\n"); 437 438 msg = bus_space_read_4(bst, fpcih, T_XUSB_CFG_ARU_MAILBOX_DATA_OUT_REG); 439 DPRINTF(sc->sc_dev, "XUSB_CFG_ARU_MBOX_DATA_OUT 0x%x\n", msg); 440 441 val = bus_space_read_4(bst, fpcih, T_XUSB_CFG_ARU_MAILBOX_CMD_REG); 442 DPRINTF(sc->sc_dev, "XUSB_CFG_ARU_MBOX_CMD 0x%x\n", val); 443 val &= ~T_XUSB_CFG_ARU_MAILBOX_CMD_DEST_SMI; 444 bus_space_write_4(bst, fpcih, T_XUSB_CFG_ARU_MAILBOX_CMD_REG, val); 445 446 bool sendresp = true; 447 u_int rate; 448 449 const uint32_t data = __SHIFTOUT(msg, MAILBOX_DATA_DATA); 450 const uint8_t type = __SHIFTOUT(msg, MAILBOX_DATA_TYPE); 451 452 switch (type) { 453 case 2: 454 case 3: 455 DPRINTF(sc->sc_dev, "FALC_CLOCK %u\n", data * 1000); 456 break; 457 case 4: 458 case 5: 459 DPRINTF(sc->sc_dev, "SSPI_CLOCK %u\n", data * 1000); 460 rate = clk_get_rate(psc->sc_clk_ss_src); 461 DPRINTF(sc->sc_dev, "rate of psc->sc_clk_ss_src %u\n", 462 rate); 463 error = clk_set_rate(psc->sc_clk_ss_src, data * 1000); 464 if (error != 0) 465 goto clk_fail; 466 rate = clk_get_rate(psc->sc_clk_ss_src); 467 DPRINTF(sc->sc_dev, 468 "rate of psc->sc_clk_ss_src %u after\n", rate); 469 if (data == (rate / 1000)) { 470 msg = __SHIFTIN(128, MAILBOX_DATA_TYPE) | 471 __SHIFTIN(rate / 1000, MAILBOX_DATA_DATA); 472 } else 473 clk_fail: 474 msg = __SHIFTIN(129, MAILBOX_DATA_TYPE) | 475 __SHIFTIN(rate / 1000, MAILBOX_DATA_DATA); 476 xusb_mailbox_send(psc, msg); 477 break; 478 case 9: 479 msg = __SHIFTIN(data, MAILBOX_DATA_DATA) | 480 __SHIFTIN(128, MAILBOX_DATA_TYPE); 481 xusb_mailbox_send(psc, msg); 482 break; 483 case 6: 484 case 128: 485 case 129: 486 sendresp = false; 487 break; 488 default: 489 sendresp = false; 490 break; 491 } 492 493 if (sendresp == false) 494 bus_space_write_4(bst, fpcih, T_XUSB_CFG_ARU_MAILBOX_OWNER_REG, 495 MAILBOX_OWNER_NONE); 496 497 return irv; 498 } 499 500 static void 501 tegra_xusb_init_regulators(struct tegra_xusb_softc * const psc) 502 { 503 const char * supply_names[] = { 504 "dvddio-pex-supply", 505 "hvddio-pex-supply", 506 "avdd-usb-supply", 507 "avdd-pll-utmip-supply", 508 "avdd-pll-uerefe-supply", 509 "dvdd-usb-ss-pll-supply", 510 "hvdd-usb-ss-pll-e-supply" 511 }; 512 device_t dev = psc->sc_xhci.sc_dev; 513 const int phandle = psc->sc_phandle; 514 struct fdtbus_regulator *reg; 515 int n, error; 516 517 for (n = 0; n < __arraycount(supply_names); n++) { 518 if (!of_hasprop(phandle, supply_names[n])) 519 continue; 520 reg = fdtbus_regulator_acquire(phandle, supply_names[n]); 521 if (reg == NULL) { 522 aprint_error_dev(dev, "couldn't acquire supply '%s'\n", 523 supply_names[n]); 524 continue; 525 } 526 error = fdtbus_regulator_enable(reg); 527 if (error != 0) 528 aprint_error_dev(dev, "couldn't enable supply '%s': %d\n", 529 supply_names[n], error); 530 } 531 } 532 533 static void 534 tegra_xusb_init(struct tegra_xusb_softc * const psc) 535 { 536 struct xhci_softc * const sc = &psc->sc_xhci; 537 const bus_space_tag_t bst = sc->sc_iot; 538 const bus_space_handle_t ipfsh = psc->sc_bsh_ipfs; 539 const bus_space_handle_t fpcih = psc->sc_bsh_fpci; 540 541 DPRINTF(sc->sc_dev, "%s()\n", __func__); 542 543 DPRINTF(sc->sc_dev, "%s ipfs 0x0 = 0x%x\n", __func__, 544 bus_space_read_4(bst, ipfsh, 0x0)); 545 546 DPRINTF(sc->sc_dev, "%s ipfs 0x40 = 0x%x\n", __func__, 547 bus_space_read_4(bst, ipfsh, 0x40)); 548 549 DPRINTF(sc->sc_dev, "%s ipfs 0x80 = 0x%x\n", __func__, 550 bus_space_read_4(bst, ipfsh, 0x80)); 551 /* FPCI_BAR0_START and FPCI_BAR0_ACCESS_TYPE */ 552 bus_space_write_4(bst, ipfsh, 0x80, 0x00100000); 553 DPRINTF(sc->sc_dev, "%s ipfs 0x80 = 0x%x\n", __func__, 554 bus_space_read_4(bst, ipfsh, 0x80)); 555 556 DPRINTF(sc->sc_dev, "%s ipfs 0x180 = 0x%x\n", __func__, 557 bus_space_read_4(bst, ipfsh, 0x180)); 558 /* EN_FPCI */ 559 tegra_reg_set_clear(bst, ipfsh, 0x180, 1, 0); 560 DPRINTF(sc->sc_dev, "%s ipfs 0x180 = 0x%x\n", __func__, 561 bus_space_read_4(bst, ipfsh, 0x180)); 562 563 DPRINTF(sc->sc_dev, "%s fpci PCI_COMMAND_STATUS_REG = 0x%x\n", 564 __func__, bus_space_read_4(bst, fpcih, PCI_COMMAND_STATUS_REG)); 565 tegra_reg_set_clear(bst, fpcih, PCI_COMMAND_STATUS_REG, 566 PCI_COMMAND_MASTER_ENABLE|PCI_COMMAND_MEM_ENABLE, 0x0); 567 DPRINTF(sc->sc_dev, "%s fpci PCI_COMMAND_STATUS_REG = 0x%x\n", 568 __func__, bus_space_read_4(bst, fpcih, PCI_COMMAND_STATUS_REG)); 569 570 DPRINTF(sc->sc_dev, "%s fpci PCI_BAR0 = 0x%x\n", __func__, 571 bus_space_read_4(bst, fpcih, PCI_BAR0)); 572 /* match FPCI BAR0 to above */ 573 bus_space_write_4(bst, fpcih, PCI_BAR0, 0x10000000); 574 DPRINTF(sc->sc_dev, "%s fpci PCI_BAR0 = 0x%x\n", __func__, 575 bus_space_read_4(bst, fpcih, PCI_BAR0)); 576 577 DPRINTF(sc->sc_dev, "%s ipfs 0x188 = 0x%x\n", __func__, 578 bus_space_read_4(bst, ipfsh, 0x188)); 579 tegra_reg_set_clear(bst, ipfsh, 0x188, __BIT(16), 0); 580 DPRINTF(sc->sc_dev, "%s ipfs 0x188 = 0x%x\n", __func__, 581 bus_space_read_4(bst, ipfsh, 0x188)); 582 583 DPRINTF(sc->sc_dev, "%s fpci 0x1bc = 0x%x\n", __func__, 584 bus_space_read_4(bst, fpcih, 0x1bc)); 585 bus_space_write_4(bst, fpcih, 0x1bc, 0x80); 586 DPRINTF(sc->sc_dev, "%s fpci 0x1bc = 0x%x\n", __func__, 587 bus_space_read_4(bst, fpcih, 0x1bc)); 588 } 589 590 static int 591 fw_dma_alloc(struct tegra_xusb_softc * const psc, size_t size, size_t align, 592 struct fw_dma * const p) 593 { 594 struct xhci_softc * const sc = &psc->sc_xhci; 595 const bus_dma_tag_t dmat = sc->sc_bus.ub_dmatag; 596 int err; 597 598 p->size = size; 599 err = bus_dmamem_alloc(dmat, p->size, align, 0, p->segs, 600 sizeof(p->segs) / sizeof(p->segs[0]), &p->nsegs, BUS_DMA_NOWAIT); 601 if (err) 602 return err; 603 err = bus_dmamem_map(dmat, p->segs, p->nsegs, p->size, &p->addr, 604 BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 605 if (err) 606 goto free; 607 err = bus_dmamap_create(dmat, p->size, 1, p->size, 0, BUS_DMA_NOWAIT, 608 &p->map); 609 if (err) 610 goto unmap; 611 err = bus_dmamap_load(dmat, p->map, p->addr, p->size, NULL, 612 BUS_DMA_NOWAIT); 613 if (err) 614 goto destroy; 615 616 return 0; 617 618 destroy: 619 bus_dmamap_destroy(dmat, p->map); 620 unmap: 621 bus_dmamem_unmap(dmat, p->addr, p->size); 622 free: 623 bus_dmamem_free(dmat, p->segs, p->nsegs); 624 625 return err; 626 } 627 628 #if !defined(TEGRA124_XUSB_BIN_STATIC) 629 static void 630 fw_dma_free(struct tegra_xusb_softc * const psc, struct fw_dma * const p) 631 { 632 const struct xhci_softc * const sc = &psc->sc_xhci; 633 const bus_dma_tag_t dmat = sc->sc_bus.ub_dmatag; 634 635 bus_dmamap_unload(dmat, p->map); 636 bus_dmamap_destroy(dmat, p->map); 637 bus_dmamem_unmap(dmat, p->addr, p->size); 638 bus_dmamem_free(dmat, p->segs, p->nsegs); 639 } 640 #endif 641 642 #define FWHEADER_BOOT_CODETAG 8 643 #define FWHEADER_BOOT_CODESIZE 12 644 #define FWHEADER_FWIMG_LEN 100 645 #define FWHEADER__LEN 256 646 647 static int 648 tegra_xusb_open_fw(struct tegra_xusb_softc * const psc) 649 { 650 struct xhci_softc * const sc = &psc->sc_xhci; 651 firmware_handle_t fw; 652 size_t firmware_size = 0; 653 void *firmware_image; 654 const char *fw_path = NULL; 655 void *fw_static = NULL; 656 int error; 657 658 switch (psc->sc_type) { 659 case XUSB_T124: 660 #if defined(TEGRA124_XUSB_BIN_STATIC) 661 firmware_size = (uintptr_t)&_binary_tegra124_xusb_bin_size; 662 fw_static = _binary_tegra124_xusb_bin_start; 663 #else 664 fw_path = "nvidia/tegra124"; 665 #endif 666 break; 667 case XUSB_T210: 668 #if defined(TEGRA210_XUSB_BIN_STATIC) 669 firmware_size = (uintptr_t)&_binary_tegra210_xusb_bin_size; 670 fw_static = _binary_tegra210_xusb_bin_start; 671 #else 672 fw_path = "nvidia/tegra210"; 673 #endif 674 break; 675 default: 676 return EINVAL; 677 } 678 679 if (fw_path != NULL) { 680 error = firmware_open(fw_path, "xusb.bin", &fw); 681 if (error != 0) { 682 aprint_error_dev(sc->sc_dev, 683 "couldn't load firmware from %s/xusb.bin: %d\n", 684 fw_path, error); 685 return error; 686 } 687 firmware_size = firmware_get_size(fw); 688 } 689 690 error = fw_dma_alloc(psc, firmware_size, PAGE_SIZE, 691 &psc->sc_fw_dma); 692 if (error != 0) 693 return error; 694 firmware_image = psc->sc_fw_dma.addr; 695 696 if (fw_path != NULL) { 697 error = firmware_read(fw, 0, firmware_image, firmware_size); 698 if (error != 0) { 699 fw_dma_free(psc, &psc->sc_fw_dma); 700 firmware_close(fw); 701 return error; 702 } 703 firmware_close(fw); 704 } else { 705 memcpy(firmware_image, fw_static, firmware_size); 706 } 707 708 return tegra_xusb_load_fw(psc, firmware_image, firmware_size); 709 } 710 711 static int 712 tegra_xusb_load_fw(struct tegra_xusb_softc * const psc, void *firmware_image, 713 size_t firmware_size) 714 { 715 struct xhci_softc * const sc = &psc->sc_xhci; 716 const uint8_t *header; 717 718 header = firmware_image; 719 720 const uint32_t fwimg_len = le32dec(&header[FWHEADER_FWIMG_LEN]); 721 const uint32_t boot_codetag = le32dec(&header[FWHEADER_BOOT_CODETAG]); 722 const uint32_t boot_codesize = le32dec(&header[FWHEADER_BOOT_CODESIZE]); 723 724 if (fwimg_len != firmware_size) 725 aprint_error_dev(sc->sc_dev, "fwimg_len mismatch %u != %zu\n", 726 fwimg_len, firmware_size); 727 728 bus_dmamap_sync(sc->sc_bus.ub_dmatag, psc->sc_fw_dma.map, 0, 729 firmware_size, BUS_DMASYNC_PREWRITE); 730 731 DPRINTF(sc->sc_dev, "XUSB_FALC_CPUCTL 0x%x\n", 732 csb_read_4(psc, XUSB_CSB_FALCON_CPUCTL_REG)); 733 DPRINTF(sc->sc_dev, "XUSB_CSB_MP_ILOAD_BASE_LO 0x%x\n", 734 csb_read_4(psc, XUSB_CSB_MEMPOOL_ILOAD_BASE_LO_REG)); 735 736 DPRINTF(sc->sc_dev, "XUSB_CSB_MP_ILOAD_ATTR 0x%x\n", 737 csb_read_4(psc, XUSB_CSB_MEMPOOL_ILOAD_ATTR_REG)); 738 csb_write_4(psc, XUSB_CSB_MEMPOOL_ILOAD_ATTR_REG, 739 fwimg_len); 740 DPRINTF(sc->sc_dev, "XUSB_CSB_MP_ILOAD_ATTR 0x%x\n", 741 csb_read_4(psc, XUSB_CSB_MEMPOOL_ILOAD_ATTR_REG)); 742 743 const uint64_t fwbase = psc->sc_fw_dma.map->dm_segs[0].ds_addr + 744 FWHEADER__LEN; 745 746 csb_write_4(psc, XUSB_CSB_MEMPOOL_ILOAD_BASE_HI_REG, fwbase >> 32); 747 csb_write_4(psc, XUSB_CSB_MEMPOOL_ILOAD_BASE_LO_REG, fwbase); 748 DPRINTF(sc->sc_dev, "XUSB_CSB_MP_ILOAD_BASE_LO 0x%x\n", 749 csb_read_4(psc, XUSB_CSB_MEMPOOL_ILOAD_BASE_LO_REG)); 750 DPRINTF(sc->sc_dev, "XUSB_CSB_MP_ILOAD_BASE_HI 0x%x\n", 751 csb_read_4(psc, XUSB_CSB_MEMPOOL_ILOAD_BASE_HI_REG)); 752 753 DPRINTF(sc->sc_dev, "XUSB_CSB_MP_APMAP 0x%x\n", 754 csb_read_4(psc, XUSB_CSB_MEMPOOL_APMAP_REG)); 755 csb_write_4(psc, XUSB_CSB_MEMPOOL_APMAP_REG, 756 XUSB_CSB_MEMPOOL_APMAP_BOOTPATH); 757 DPRINTF(sc->sc_dev, "XUSB_CSB_MP_APMAP 0x%x\n", 758 csb_read_4(psc, XUSB_CSB_MEMPOOL_APMAP_REG)); 759 760 DPRINTF(sc->sc_dev, "XUSB_CSB_MP_L2IMEMOP_TRIG 0x%x\n", 761 csb_read_4(psc, XUSB_CSB_MEMPOOL_L2IMEMOP_TRIG_REG)); 762 csb_write_4(psc, XUSB_CSB_MEMPOOL_L2IMEMOP_TRIG_REG, 763 __SHIFTIN(ACTION_L2IMEM_INVALIDATE_ALL, 764 XUSB_CSB_MEMPOOL_L2IMEMOP_TRIG_ACTION)); 765 DPRINTF(sc->sc_dev, "XUSB_CSB_MP_L2IMEMOP_TRIG 0x%x\n", 766 csb_read_4(psc, XUSB_CSB_MEMPOOL_L2IMEMOP_TRIG_REG)); 767 768 const u_int code_tag_blocks = 769 howmany(boot_codetag, IMEM_BLOCK_SIZE); 770 const u_int code_size_blocks = 771 howmany(boot_codesize, IMEM_BLOCK_SIZE); 772 const u_int code_blocks = code_tag_blocks + code_size_blocks; 773 774 DPRINTF(sc->sc_dev, "XUSB_CSB_MP_L2IMEMOP_SIZE 0x%x\n", 775 csb_read_4(psc, XUSB_CSB_MEMPOOL_L2IMEMOP_SIZE_REG)); 776 csb_write_4(psc, XUSB_CSB_MEMPOOL_L2IMEMOP_SIZE_REG, 777 __SHIFTIN(code_tag_blocks, 778 XUSB_CSB_MEMPOOL_L2IMEMOP_SIZE_SRC_OFFSET) | 779 __SHIFTIN(code_size_blocks, 780 XUSB_CSB_MEMPOOL_L2IMEMOP_SIZE_SRC_COUNT)); 781 DPRINTF(sc->sc_dev, "XUSB_CSB_MP_L2IMEMOP_SIZE 0x%x\n", 782 csb_read_4(psc, XUSB_CSB_MEMPOOL_L2IMEMOP_SIZE_REG)); 783 784 DPRINTF(sc->sc_dev, "XUSB_CSB_MP_L2IMEMOP_TRIG 0x%x\n", 785 csb_read_4(psc, XUSB_CSB_MEMPOOL_L2IMEMOP_TRIG_REG)); 786 csb_write_4(psc, XUSB_CSB_MEMPOOL_L2IMEMOP_TRIG_REG, 787 __SHIFTIN(ACTION_L2IMEM_LOAD_LOCKED_RESULT, 788 XUSB_CSB_MEMPOOL_L2IMEMOP_TRIG_ACTION)); 789 DPRINTF(sc->sc_dev, "XUSB_CSB_MP_L2IMEMOP_TRIG 0x%x\n", 790 csb_read_4(psc, XUSB_CSB_MEMPOOL_L2IMEMOP_TRIG_REG)); 791 792 DPRINTF(sc->sc_dev, "XUSB_FALC_IMFILLCTL 0x%x\n", 793 csb_read_4(psc, XUSB_CSB_FALCON_IMFILLCTL_REG)); 794 csb_write_4(psc, XUSB_CSB_FALCON_IMFILLCTL_REG, code_size_blocks); 795 DPRINTF(sc->sc_dev, "XUSB_FALC_IMFILLCTL 0x%x\n", 796 csb_read_4(psc, XUSB_CSB_FALCON_IMFILLCTL_REG)); 797 798 DPRINTF(sc->sc_dev, "XUSB_FALC_IMFILLRNG1 0x%x\n", 799 csb_read_4(psc, XUSB_CSB_FALCON_IMFILLRNG1_REG)); 800 csb_write_4(psc, XUSB_CSB_FALCON_IMFILLRNG1_REG, 801 __SHIFTIN(code_tag_blocks, XUSB_CSB_FALCON_IMFILLRNG1_TAG_LO) | 802 __SHIFTIN(code_blocks, XUSB_CSB_FALCON_IMFILLRNG1_TAG_HI)); 803 DPRINTF(sc->sc_dev, "XUSB_FALC_IMFILLRNG1 0x%x\n", 804 csb_read_4(psc, XUSB_CSB_FALCON_IMFILLRNG1_REG)); 805 806 DPRINTF(sc->sc_dev, "XUSB_FALC_DMACTL 0x%x\n", 807 csb_read_4(psc, XUSB_CSB_FALCON_DMACTL_REG)); 808 csb_write_4(psc, XUSB_CSB_FALCON_DMACTL_REG, 0); 809 DPRINTF(sc->sc_dev, "XUSB_FALC_DMACTL 0x%x\n", 810 csb_read_4(psc, XUSB_CSB_FALCON_DMACTL_REG)); 811 812 DPRINTF(sc->sc_dev, "XUSB_FALC_BOOTVEC 0x%x\n", 813 csb_read_4(psc, XUSB_CSB_FALCON_BOOTVEC_REG)); 814 csb_write_4(psc, XUSB_CSB_FALCON_BOOTVEC_REG, 815 boot_codetag); 816 DPRINTF(sc->sc_dev, "XUSB_FALC_BOOTVEC 0x%x\n", 817 csb_read_4(psc, XUSB_CSB_FALCON_BOOTVEC_REG)); 818 819 DPRINTF(sc->sc_dev, "XUSB_FALC_CPUCTL 0x%x\n", 820 csb_read_4(psc, XUSB_CSB_FALCON_CPUCTL_REG)); 821 csb_write_4(psc, XUSB_CSB_FALCON_CPUCTL_REG, 822 XUSB_CSB_FALCON_CPUCTL_STARTCPU); 823 DPRINTF(sc->sc_dev, "XUSB_FALC_CPUCTL 0x%x\n", 824 csb_read_4(psc, XUSB_CSB_FALCON_CPUCTL_REG)); 825 826 return 0; 827 } 828 829 static uint32_t 830 csb_read_4(struct tegra_xusb_softc * const psc, bus_size_t csb_offset) 831 { 832 const uint32_t range = __SHIFTOUT(csb_offset, XUSB_CSB_RANGE); 833 const bus_size_t offset = __SHIFTOUT(csb_offset, XUSB_CSB_OFFSET); 834 const bus_space_tag_t bst = psc->sc_xhci.sc_iot; 835 const bus_space_handle_t fpcih = psc->sc_bsh_fpci; 836 837 bus_space_write_4(bst, fpcih, T_XUSB_CFG_ARU_C11_CSBRANGE_REG, range); 838 return bus_space_read_4(bst, fpcih, T_XUSB_CFG_CSB_BASE_ADDR + offset); 839 } 840 841 static void 842 csb_write_4(struct tegra_xusb_softc * const psc, bus_size_t csb_offset, 843 uint32_t value) 844 { 845 const uint32_t range = __SHIFTOUT(csb_offset, XUSB_CSB_RANGE); 846 const bus_size_t offset = __SHIFTOUT(csb_offset, XUSB_CSB_OFFSET); 847 const bus_space_tag_t bst = psc->sc_xhci.sc_iot; 848 const bus_space_handle_t fpcih = psc->sc_bsh_fpci; 849 850 bus_space_write_4(bst, fpcih, T_XUSB_CFG_ARU_C11_CSBRANGE_REG, range); 851 bus_space_write_4(bst, fpcih, T_XUSB_CFG_CSB_BASE_ADDR + offset, value); 852 } 853 854 static int 855 xusb_mailbox_send(struct tegra_xusb_softc * const psc, uint32_t msg) 856 { 857 struct xhci_softc * const sc = &psc->sc_xhci; 858 const bus_space_tag_t bst = psc->sc_xhci.sc_iot; 859 const bus_space_handle_t fpcih = psc->sc_bsh_fpci; 860 uint32_t val; 861 bool wait = false; 862 863 const uint8_t type = __SHIFTOUT(msg, MAILBOX_DATA_TYPE); 864 865 if (!(type == 128 || type == 129)) { 866 val = bus_space_read_4(bst, fpcih, 867 T_XUSB_CFG_ARU_MAILBOX_OWNER_REG); 868 DPRINTF(sc->sc_dev, "XUSB_CFG_ARU_MBOX_OWNER 0x%x\n", 869 val); 870 if (val != MAILBOX_OWNER_NONE) { 871 return EBUSY; 872 } 873 874 bus_space_write_4(bst, fpcih, T_XUSB_CFG_ARU_MAILBOX_OWNER_REG, 875 MAILBOX_OWNER_SW); 876 877 val = bus_space_read_4(bst, fpcih, 878 T_XUSB_CFG_ARU_MAILBOX_OWNER_REG); 879 DPRINTF(sc->sc_dev, "XUSB_CFG_ARU_MBOX_OWNER 0x%x\n", 880 val); 881 if (val != MAILBOX_OWNER_SW) { 882 return EBUSY; 883 } 884 885 wait = true; 886 } 887 888 bus_space_write_4(bst, fpcih, T_XUSB_CFG_ARU_MAILBOX_DATA_IN_REG, msg); 889 890 tegra_reg_set_clear(bst, fpcih, T_XUSB_CFG_ARU_MAILBOX_CMD_REG, 891 T_XUSB_CFG_ARU_MAILBOX_CMD_INT_EN | 892 T_XUSB_CFG_ARU_MAILBOX_CMD_DEST_FALCON, 0); 893 894 if (wait) { 895 896 for (u_int i = 0; i < 2500; i++) { 897 val = bus_space_read_4(bst, fpcih, 898 T_XUSB_CFG_ARU_MAILBOX_OWNER_REG); 899 DPRINTF(sc->sc_dev, 900 "XUSB_CFG_ARU_MBOX_OWNER 0x%x\n", val); 901 if (val == MAILBOX_OWNER_NONE) { 902 break; 903 } 904 DELAY(10); 905 } 906 907 val = bus_space_read_4(bst, fpcih, 908 T_XUSB_CFG_ARU_MAILBOX_OWNER_REG); 909 DPRINTF(sc->sc_dev, 910 "XUSB_CFG_ARU_MBOX_OWNER 0x%x\n", val); 911 if (val != MAILBOX_OWNER_NONE) { 912 aprint_error_dev(sc->sc_dev, 913 "timeout, XUSB_CFG_ARU_MBOX_OWNER 0x%x\n", val); 914 } 915 } 916 917 return 0; 918 } 919
Indexes created Thu Sep 25 16:09:42 GMT 2025