tegra_xusb.c revision 1.11
1 /* $NetBSD: tegra_xusb.c,v 1.11 2017/09/25 00:03:34 jmcneill Exp $ */ 2 3 /* 4 * Copyright (c) 2016 Jonathan A. Kollasch 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR 20 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 21 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 22 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 23 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 25 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 26 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include "locators.h" 30 #include "opt_tegra.h" 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: tegra_xusb.c,v 1.11 2017/09/25 00:03:34 jmcneill Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/bus.h> 37 #include <sys/device.h> 38 #include <sys/intr.h> 39 #include <sys/systm.h> 40 #include <sys/kernel.h> 41 42 #include <arm/nvidia/tegra_reg.h> 43 #include <arm/nvidia/tegra_var.h> 44 #include <arm/nvidia/tegra_xusbpad.h> 45 #include <arm/nvidia/tegra_xusbreg.h> 46 #include <arm/nvidia/tegra_pmcreg.h> 47 48 #include <dev/pci/pcireg.h> 49 50 #include <dev/fdt/fdtvar.h> 51 52 #include <dev/firmload.h> 53 54 #include <dev/usb/usb.h> 55 #include <dev/usb/usbdi.h> 56 #include <dev/usb/usbdivar.h> 57 #include <dev/usb/usb_mem.h> 58 59 #include <dev/usb/xhcireg.h> 60 #include <dev/usb/xhcivar.h> 61 62 #ifdef TEGRA_XUSB_DEBUG 63 int tegra_xusb_debug = 1; 64 #else 65 int tegra_xusb_debug = 0; 66 #endif 67 68 #define DPRINTF(...) if (tegra_xusb_debug) device_printf(__VA_ARGS__) 69 70 static int tegra_xusb_match(device_t, cfdata_t, void *); 71 static void tegra_xusb_attach(device_t, device_t, void *); 72 static void tegra_xusb_mountroot(device_t); 73 74 static int tegra_xusb_intr_mbox(void *); 75 76 #ifdef TEGRA124_XUSB_BIN_STATIC 77 extern const char _binary_tegra124_xusb_bin_size[]; 78 extern const char _binary_tegra124_xusb_bin_start[]; 79 #endif 80 81 #ifdef TEGRA210_XUSB_BIN_STATIC 82 extern const char _binary_tegra210_xusb_bin_size[]; 83 extern const char _binary_tegra210_xusb_bin_start[]; 84 #endif 85 86 enum xusb_type { 87 XUSB_T124 = 1, 88 XUSB_T210 89 }; 90 91 static const struct of_compat_data compat_data[] = { 92 { "nvidia,tegra124-xusb", XUSB_T124 }, 93 { "nvidia,tegra210-xusb", XUSB_T210 }, 94 { NULL } 95 }; 96 97 struct fw_dma { 98 bus_dmamap_t map; 99 void * addr; 100 bus_dma_segment_t segs[1]; 101 int nsegs; 102 size_t size; 103 }; 104 105 struct tegra_xusb_softc { 106 struct xhci_softc sc_xhci; 107 int sc_phandle; 108 bus_space_handle_t sc_bsh_xhci; 109 bus_space_handle_t sc_bsh_fpci; 110 bus_space_handle_t sc_bsh_ipfs; 111 void *sc_ih; 112 void *sc_ih_mbox; 113 struct fw_dma sc_fw_dma; 114 struct clk *sc_clk_ss_src; 115 enum xusb_type sc_type; 116 117 bool sc_scale_ss_clock; 118 }; 119 120 static uint32_t csb_read_4(struct tegra_xusb_softc * const, bus_size_t); 121 static void csb_write_4(struct tegra_xusb_softc * const, bus_size_t, 122 uint32_t); 123 124 static void tegra_xusb_init(struct tegra_xusb_softc * const); 125 static int tegra_xusb_open_fw(struct tegra_xusb_softc * const); 126 static int tegra_xusb_load_fw(struct tegra_xusb_softc * const, void *, 127 size_t); 128 static void tegra_xusb_init_regulators(struct tegra_xusb_softc * const); 129 130 static int xusb_mailbox_send(struct tegra_xusb_softc * const, uint32_t); 131 132 CFATTACH_DECL_NEW(tegra_xusb, sizeof(struct tegra_xusb_softc), 133 tegra_xusb_match, tegra_xusb_attach, NULL, NULL); 134 135 static int 136 tegra_xusb_match(device_t parent, cfdata_t cf, void *aux) 137 { 138 struct fdt_attach_args * const faa = aux; 139 140 return of_match_compat_data(faa->faa_phandle, compat_data); 141 } 142 143 #define tegra_xusb_attach_check(sc, cond, fmt, ...) \ 144 do { \ 145 if (cond) { \ 146 aprint_error_dev(sc->sc_dev, fmt, ## __VA_ARGS__); \ 147 return; \ 148 } \ 149 } while (0) 150 151 static void 152 tegra_xusb_attach(device_t parent, device_t self, void *aux) 153 { 154 struct tegra_xusb_softc * const psc = device_private(self); 155 struct xhci_softc * const sc = &psc->sc_xhci; 156 struct fdt_attach_args * const faa = aux; 157 bool wait_for_root = true; 158 char intrstr[128]; 159 bus_addr_t addr; 160 bus_size_t size; 161 struct fdtbus_reset *rst; 162 struct clk *clk; 163 uint32_t rate; 164 int error; 165 166 aprint_naive("\n"); 167 aprint_normal(": XUSB\n"); 168 169 sc->sc_dev = self; 170 sc->sc_iot = faa->faa_bst; 171 sc->sc_bus.ub_hcpriv = sc; 172 sc->sc_bus.ub_dmatag = faa->faa_dmat; 173 sc->sc_quirks = XHCI_DEFERRED_START; 174 psc->sc_phandle = faa->faa_phandle; 175 psc->sc_type = of_search_compatible(faa->faa_phandle, compat_data)->data; 176 177 switch (psc->sc_type) { 178 case XUSB_T124: 179 psc->sc_scale_ss_clock = true; 180 break; 181 default: 182 psc->sc_scale_ss_clock = false; 183 break; 184 } 185 186 if (fdtbus_get_reg_byname(faa->faa_phandle, "hcd", &addr, &size) != 0) { 187 aprint_error(": couldn't get registers\n"); 188 return; 189 } 190 error = bus_space_map(sc->sc_iot, addr, size, 0, &sc->sc_ioh); 191 if (error) { 192 aprint_error(": couldn't map %#llx: %d", (uint64_t)addr, error); 193 return; 194 } 195 DPRINTF(sc->sc_dev, "mapped %#llx\n", (uint64_t)addr); 196 197 if (fdtbus_get_reg_byname(faa->faa_phandle, "fpci", &addr, &size) != 0) { 198 aprint_error(": couldn't get registers\n"); 199 return; 200 } 201 error = bus_space_map(sc->sc_iot, addr, size, 0, &psc->sc_bsh_fpci); 202 if (error) { 203 aprint_error(": couldn't map %#llx: %d", (uint64_t)addr, error); 204 return; 205 } 206 DPRINTF(sc->sc_dev, "mapped %#llx\n", (uint64_t)addr); 207 208 if (fdtbus_get_reg_byname(faa->faa_phandle, "ipfs", &addr, &size) != 0) { 209 aprint_error(": couldn't get registers\n"); 210 return; 211 } 212 error = bus_space_map(sc->sc_iot, addr, size, 0, &psc->sc_bsh_ipfs); 213 if (error) { 214 aprint_error(": couldn't map %#llx: %d", (uint64_t)addr, error); 215 return; 216 } 217 DPRINTF(sc->sc_dev, "mapped %#llx\n", (uint64_t)addr); 218 219 if (!fdtbus_intr_str(faa->faa_phandle, 0, intrstr, sizeof(intrstr))) { 220 aprint_error_dev(self, "failed to decode interrupt\n"); 221 return; 222 } 223 224 psc->sc_ih = fdtbus_intr_establish(faa->faa_phandle, 0, IPL_USB, 225 FDT_INTR_MPSAFE, xhci_intr, sc); 226 if (psc->sc_ih == NULL) { 227 aprint_error_dev(self, "failed to establish interrupt on %s\n", 228 intrstr); 229 return; 230 } 231 aprint_normal_dev(self, "interrupting on %s\n", intrstr); 232 233 if (!fdtbus_intr_str(faa->faa_phandle, 1, intrstr, sizeof(intrstr))) { 234 aprint_error_dev(self, "failed to decode interrupt\n"); 235 return; 236 } 237 238 psc->sc_ih_mbox = fdtbus_intr_establish(faa->faa_phandle, 1, IPL_VM, 239 FDT_INTR_MPSAFE, tegra_xusb_intr_mbox, psc); 240 if (psc->sc_ih_mbox == NULL) { 241 aprint_error_dev(self, "failed to establish interrupt on %s\n", 242 intrstr); 243 return; 244 } 245 aprint_normal_dev(self, "interrupting on %s\n", intrstr); 246 247 /* Enable XUSB power rails */ 248 249 tegra_pmc_power(PMC_PARTID_XUSBC, true); /* Host/USB2.0 */ 250 tegra_pmc_power(PMC_PARTID_XUSBA, true); /* SuperSpeed */ 251 252 /* Enable XUSB clocks */ 253 254 clk = fdtbus_clock_get(faa->faa_phandle, "pll_e"); 255 rate = clk_get_rate(clk); 256 error = clk_enable(clk); /* XXX set frequency */ 257 DPRINTF(sc->sc_dev, "rate %u error %d\n", rate, error); 258 tegra_xusb_attach_check(sc, error, "failed to enable pll_e clock"); 259 260 clk = fdtbus_clock_get(faa->faa_phandle, "xusb_host_src"); 261 rate = clk_get_rate(clk); 262 DPRINTF(sc->sc_dev, "rate %u error %d\n", rate, error); 263 error = clk_set_rate(clk, 102000000); 264 tegra_xusb_attach_check(sc, error, "failed to set xusb_host_src clock rate"); 265 266 rate = clk_get_rate(clk); 267 error = clk_enable(clk); /* XXX set frequency */ 268 DPRINTF(sc->sc_dev, "rate %u error %d\n", rate, error); 269 tegra_xusb_attach_check(sc, error, "failed to enable xusb_host_src clock"); 270 271 clk = fdtbus_clock_get(faa->faa_phandle, "xusb_falcon_src"); 272 rate = clk_get_rate(clk); 273 DPRINTF(sc->sc_dev, "rate %u error %d\n", rate, error); 274 error = clk_set_rate(clk, 204000000); 275 tegra_xusb_attach_check(sc, error, "failed to set xusb_falcon_src clock rate"); 276 277 rate = clk_get_rate(clk); 278 error = clk_enable(clk); 279 DPRINTF(sc->sc_dev, "rate %u error %d\n", rate, error); 280 tegra_xusb_attach_check(sc, error, "failed to enable xusb_falcon_src clock"); 281 282 clk = fdtbus_clock_get(faa->faa_phandle, "xusb_host"); 283 rate = clk_get_rate(clk); 284 error = clk_enable(clk); /* XXX set frequency */ 285 DPRINTF(sc->sc_dev, "rate %u error %d\n", rate, error); 286 287 clk = fdtbus_clock_get(faa->faa_phandle, "xusb_ss"); 288 rate = clk_get_rate(clk); 289 error = clk_enable(clk); /* XXX set frequency */ 290 DPRINTF(sc->sc_dev, "xusb_ss rate %u error %d\n", rate, error); 291 tegra_xusb_attach_check(sc, error, "failed to enable xusb_ss clock"); 292 293 psc->sc_clk_ss_src = fdtbus_clock_get(faa->faa_phandle, "xusb_ss_src"); 294 tegra_xusb_attach_check(sc, psc->sc_clk_ss_src == NULL, 295 "failed to get xusb_ss_src clock"); 296 297 if (psc->sc_scale_ss_clock) { 298 rate = clk_get_rate(psc->sc_clk_ss_src); 299 DPRINTF(sc->sc_dev, "xusb_ss_src rate %u\n", rate); 300 error = clk_set_rate(psc->sc_clk_ss_src, 2000000); 301 rate = clk_get_rate(psc->sc_clk_ss_src); 302 DPRINTF(sc->sc_dev, "xusb_ss_src rate %u error %d\n", rate, error); 303 tegra_xusb_attach_check(sc, error, "failed to get xusb_ss_src clock rate"); 304 305 rate = clk_get_rate(psc->sc_clk_ss_src); 306 DPRINTF(sc->sc_dev, "ss_src rate %u\n", rate); 307 tegra_xusb_attach_check(sc, error, "failed to set xusb_ss_src clock rate"); 308 309 error = clk_set_rate(psc->sc_clk_ss_src, 120000000); 310 rate = clk_get_rate(psc->sc_clk_ss_src); 311 DPRINTF(sc->sc_dev, "ss_src rate %u error %d\n", rate, error); 312 tegra_xusb_attach_check(sc, error, "failed to get xusb_ss_src clock rate"); 313 } 314 315 rate = clk_get_rate(psc->sc_clk_ss_src); 316 error = clk_enable(psc->sc_clk_ss_src); 317 DPRINTF(sc->sc_dev, "ss_src rate %u error %d\n", rate, error); 318 tegra_xusb_attach_check(sc, error, "failed to enable xusb_ss_src clock"); 319 320 #if 0 321 clk = fdtbus_clock_get(faa->faa_phandle, "xusb_hs_src"); 322 error = 0; 323 rate = clk_get_rate(clk); 324 DPRINTF(sc->sc_dev, "rate %u error %d\n", rate, error); 325 #endif 326 327 clk = fdtbus_clock_get(faa->faa_phandle, "xusb_fs_src"); 328 rate = clk_get_rate(clk); 329 error = clk_enable(clk); /* XXX set frequency */ 330 DPRINTF(sc->sc_dev, "rate %u error %d\n", rate, error); 331 tegra_xusb_attach_check(sc, error, "failed to enable xusb_fs_src clock"); 332 333 rst = fdtbus_reset_get(faa->faa_phandle, "xusb_host"); 334 fdtbus_reset_deassert(rst); 335 336 rst = fdtbus_reset_get(faa->faa_phandle, "xusb_src"); 337 fdtbus_reset_deassert(rst); 338 339 rst = fdtbus_reset_get(faa->faa_phandle, "xusb_ss"); 340 fdtbus_reset_deassert(rst); 341 342 DELAY(1); 343 344 tegra_xusb_init_regulators(psc); 345 346 tegra_xusb_init(psc); 347 348 #if defined(TEGRA124_XUSB_BIN_STATIC) 349 if (psc->sc_type == XUSB_T124) 350 wait_for_root = false; 351 #endif 352 #if defined(TEGRA210_XUSB_BIN_STATIC) 353 if (psc->sc_type == XUSB_T210) 354 wait_for_root = false; 355 #endif 356 357 if (wait_for_root) 358 config_mountroot(sc->sc_dev, tegra_xusb_mountroot); 359 else 360 tegra_xusb_mountroot(sc->sc_dev); 361 } 362 363 static void 364 tegra_xusb_mountroot(device_t self) 365 { 366 struct tegra_xusb_softc * const psc = device_private(self); 367 struct xhci_softc * const sc = &psc->sc_xhci; 368 const bus_space_tag_t bst = sc->sc_iot; 369 const bus_space_handle_t ipfsh = psc->sc_bsh_ipfs; 370 struct clk *clk; 371 struct fdtbus_reset *rst; 372 uint32_t rate; 373 uint32_t val; 374 int error; 375 376 DPRINTF(sc->sc_dev, "%s()\n", __func__); 377 378 val = bus_space_read_4(bst, ipfsh, 0x0); 379 DPRINTF(sc->sc_dev, "%s ipfs 0x0 = 0x%x\n", __func__, val); 380 381 if (tegra_xusb_open_fw(psc) != 0) 382 return; 383 DPRINTF(sc->sc_dev, "post fw\n"); 384 385 tegra_xusbpad_xhci_enable(); 386 387 clk = fdtbus_clock_get(psc->sc_phandle, "xusb_falcon_src"); 388 rate = clk_get_rate(clk); 389 error = clk_enable(clk); 390 DPRINTF(sc->sc_dev, "rate %u error %d\n", rate, error); 391 392 clk = fdtbus_clock_get(psc->sc_phandle, "xusb_host_src"); 393 rate = clk_get_rate(clk); 394 error = clk_enable(clk); 395 DPRINTF(sc->sc_dev, "rate %u error %d\n", rate, error); 396 397 val = bus_space_read_4(bst, ipfsh, 0x0); 398 DPRINTF(sc->sc_dev, "%s ipfs 0x0 = 0x%x\n", __func__, val); 399 400 rst = fdtbus_reset_get(psc->sc_phandle, "xusb_host"); 401 fdtbus_reset_deassert(rst); 402 403 rst = fdtbus_reset_get(psc->sc_phandle, "xusb_src"); 404 fdtbus_reset_deassert(rst); 405 406 rst = fdtbus_reset_get(psc->sc_phandle, "xusb_ss"); 407 fdtbus_reset_deassert(rst); 408 409 val = csb_read_4(psc, XUSB_CSB_FALCON_CPUCTL_REG); 410 DPRINTF(sc->sc_dev, "XUSB_FALC_CPUCTL 0x%x\n", val); 411 412 error = xhci_init(sc); 413 if (error) { 414 aprint_error_dev(self, "init failed, error=%d\n", error); 415 return; 416 } 417 418 sc->sc_child = config_found(self, &sc->sc_bus, usbctlprint); 419 420 sc->sc_child2 = config_found(self, &sc->sc_bus2, usbctlprint); 421 422 xhci_start(sc); 423 424 error = xusb_mailbox_send(psc, 0x01000000); 425 if (error) { 426 aprint_error_dev(self, "send failed, error=%d\n", error); 427 } 428 } 429 430 static int 431 tegra_xusb_intr_mbox(void *v) 432 { 433 struct tegra_xusb_softc * const psc = v; 434 struct xhci_softc * const sc = &psc->sc_xhci; 435 const bus_space_tag_t bst = sc->sc_iot; 436 const bus_space_handle_t fpcih = psc->sc_bsh_fpci; 437 uint32_t val; 438 uint32_t irv; 439 uint32_t msg; 440 int error; 441 442 DPRINTF(sc->sc_dev, "%s()\n", __func__); 443 444 irv = bus_space_read_4(bst, fpcih, T_XUSB_CFG_ARU_SMI_INTR_REG); 445 DPRINTF(sc->sc_dev, "XUSB_CFG_ARU_SMI_INTR 0x%x\n", irv); 446 bus_space_write_4(bst, fpcih, T_XUSB_CFG_ARU_SMI_INTR_REG, irv); 447 448 if (irv & T_XUSB_CFG_ARU_SMI_INTR_FW_HANG) 449 aprint_error_dev(sc->sc_dev, "firmware hang\n"); 450 451 msg = bus_space_read_4(bst, fpcih, T_XUSB_CFG_ARU_MAILBOX_DATA_OUT_REG); 452 DPRINTF(sc->sc_dev, "XUSB_CFG_ARU_MBOX_DATA_OUT 0x%x\n", msg); 453 454 val = bus_space_read_4(bst, fpcih, T_XUSB_CFG_ARU_MAILBOX_CMD_REG); 455 DPRINTF(sc->sc_dev, "XUSB_CFG_ARU_MBOX_CMD 0x%x\n", val); 456 val &= ~T_XUSB_CFG_ARU_MAILBOX_CMD_DEST_SMI; 457 bus_space_write_4(bst, fpcih, T_XUSB_CFG_ARU_MAILBOX_CMD_REG, val); 458 459 bool sendresp = true; 460 u_int rate; 461 462 const uint32_t data = __SHIFTOUT(msg, MAILBOX_DATA_DATA); 463 const uint8_t type = __SHIFTOUT(msg, MAILBOX_DATA_TYPE); 464 465 switch (type) { 466 case 2: 467 case 3: 468 DPRINTF(sc->sc_dev, "FALC_CLOCK %u\n", data * 1000); 469 break; 470 case 4: 471 case 5: 472 if (psc->sc_scale_ss_clock) { 473 DPRINTF(sc->sc_dev, "SSPI_CLOCK %u\n", data * 1000); 474 rate = clk_get_rate(psc->sc_clk_ss_src); 475 DPRINTF(sc->sc_dev, "rate of psc->sc_clk_ss_src %u\n", 476 rate); 477 error = clk_set_rate(psc->sc_clk_ss_src, data * 1000); 478 if (error != 0) 479 goto clk_fail; 480 rate = clk_get_rate(psc->sc_clk_ss_src); 481 DPRINTF(sc->sc_dev, 482 "rate of psc->sc_clk_ss_src %u after\n", rate); 483 if (data == (rate / 1000)) { 484 msg = __SHIFTIN(128, MAILBOX_DATA_TYPE) | 485 __SHIFTIN(rate / 1000, MAILBOX_DATA_DATA); 486 } else 487 clk_fail: 488 msg = __SHIFTIN(129, MAILBOX_DATA_TYPE) | 489 __SHIFTIN(rate / 1000, MAILBOX_DATA_DATA); 490 } else { 491 msg = __SHIFTIN(128, MAILBOX_DATA_TYPE) | 492 __SHIFTIN(data, MAILBOX_DATA_DATA); 493 } 494 xusb_mailbox_send(psc, msg); 495 break; 496 case 9: 497 msg = __SHIFTIN(data, MAILBOX_DATA_DATA) | 498 __SHIFTIN(128, MAILBOX_DATA_TYPE); 499 xusb_mailbox_send(psc, msg); 500 break; 501 case 6: 502 case 128: 503 case 129: 504 sendresp = false; 505 break; 506 default: 507 sendresp = false; 508 break; 509 } 510 511 if (sendresp == false) 512 bus_space_write_4(bst, fpcih, T_XUSB_CFG_ARU_MAILBOX_OWNER_REG, 513 MAILBOX_OWNER_NONE); 514 515 return irv; 516 } 517 518 static void 519 tegra_xusb_init_regulators(struct tegra_xusb_softc * const psc) 520 { 521 const char * supply_names[] = { 522 "dvddio-pex-supply", 523 "hvddio-pex-supply", 524 "avdd-usb-supply", 525 "avdd-pll-utmip-supply", 526 "avdd-pll-uerefe-supply", 527 "dvdd-usb-ss-pll-supply", 528 "hvdd-usb-ss-pll-e-supply" 529 }; 530 device_t dev = psc->sc_xhci.sc_dev; 531 const int phandle = psc->sc_phandle; 532 struct fdtbus_regulator *reg; 533 int n, error; 534 535 for (n = 0; n < __arraycount(supply_names); n++) { 536 if (!of_hasprop(phandle, supply_names[n])) 537 continue; 538 reg = fdtbus_regulator_acquire(phandle, supply_names[n]); 539 if (reg == NULL) { 540 aprint_error_dev(dev, "couldn't acquire supply '%s'\n", 541 supply_names[n]); 542 continue; 543 } 544 error = fdtbus_regulator_enable(reg); 545 if (error != 0) 546 aprint_error_dev(dev, "couldn't enable supply '%s': %d\n", 547 supply_names[n], error); 548 } 549 } 550 551 static void 552 tegra_xusb_init(struct tegra_xusb_softc * const psc) 553 { 554 struct xhci_softc * const sc = &psc->sc_xhci; 555 const bus_space_tag_t bst = sc->sc_iot; 556 const bus_space_handle_t ipfsh = psc->sc_bsh_ipfs; 557 const bus_space_handle_t fpcih = psc->sc_bsh_fpci; 558 559 DPRINTF(sc->sc_dev, "%s()\n", __func__); 560 561 DPRINTF(sc->sc_dev, "%s ipfs 0x0 = 0x%x\n", __func__, 562 bus_space_read_4(bst, ipfsh, 0x0)); 563 564 DPRINTF(sc->sc_dev, "%s ipfs 0x40 = 0x%x\n", __func__, 565 bus_space_read_4(bst, ipfsh, 0x40)); 566 567 DPRINTF(sc->sc_dev, "%s ipfs 0x80 = 0x%x\n", __func__, 568 bus_space_read_4(bst, ipfsh, 0x80)); 569 /* FPCI_BAR0_START and FPCI_BAR0_ACCESS_TYPE */ 570 bus_space_write_4(bst, ipfsh, 0x80, 0x00100000); 571 DPRINTF(sc->sc_dev, "%s ipfs 0x80 = 0x%x\n", __func__, 572 bus_space_read_4(bst, ipfsh, 0x80)); 573 574 DPRINTF(sc->sc_dev, "%s ipfs 0x180 = 0x%x\n", __func__, 575 bus_space_read_4(bst, ipfsh, 0x180)); 576 /* EN_FPCI */ 577 tegra_reg_set_clear(bst, ipfsh, 0x180, 1, 0); 578 DPRINTF(sc->sc_dev, "%s ipfs 0x180 = 0x%x\n", __func__, 579 bus_space_read_4(bst, ipfsh, 0x180)); 580 581 DPRINTF(sc->sc_dev, "%s fpci PCI_COMMAND_STATUS_REG = 0x%x\n", 582 __func__, bus_space_read_4(bst, fpcih, PCI_COMMAND_STATUS_REG)); 583 tegra_reg_set_clear(bst, fpcih, PCI_COMMAND_STATUS_REG, 584 PCI_COMMAND_MASTER_ENABLE|PCI_COMMAND_MEM_ENABLE, 0x0); 585 DPRINTF(sc->sc_dev, "%s fpci PCI_COMMAND_STATUS_REG = 0x%x\n", 586 __func__, bus_space_read_4(bst, fpcih, PCI_COMMAND_STATUS_REG)); 587 588 DPRINTF(sc->sc_dev, "%s fpci PCI_BAR0 = 0x%x\n", __func__, 589 bus_space_read_4(bst, fpcih, PCI_BAR0)); 590 /* match FPCI BAR0 to above */ 591 bus_space_write_4(bst, fpcih, PCI_BAR0, 0x10000000); 592 DPRINTF(sc->sc_dev, "%s fpci PCI_BAR0 = 0x%x\n", __func__, 593 bus_space_read_4(bst, fpcih, PCI_BAR0)); 594 595 DPRINTF(sc->sc_dev, "%s ipfs 0x188 = 0x%x\n", __func__, 596 bus_space_read_4(bst, ipfsh, 0x188)); 597 tegra_reg_set_clear(bst, ipfsh, 0x188, __BIT(16), 0); 598 DPRINTF(sc->sc_dev, "%s ipfs 0x188 = 0x%x\n", __func__, 599 bus_space_read_4(bst, ipfsh, 0x188)); 600 601 DPRINTF(sc->sc_dev, "%s fpci 0x1bc = 0x%x\n", __func__, 602 bus_space_read_4(bst, fpcih, 0x1bc)); 603 bus_space_write_4(bst, fpcih, 0x1bc, 0x80); 604 DPRINTF(sc->sc_dev, "%s fpci 0x1bc = 0x%x\n", __func__, 605 bus_space_read_4(bst, fpcih, 0x1bc)); 606 } 607 608 static int 609 fw_dma_alloc(struct tegra_xusb_softc * const psc, size_t size, size_t align, 610 struct fw_dma * const p) 611 { 612 struct xhci_softc * const sc = &psc->sc_xhci; 613 const bus_dma_tag_t dmat = sc->sc_bus.ub_dmatag; 614 int err; 615 616 p->size = size; 617 err = bus_dmamem_alloc(dmat, p->size, align, 0, p->segs, 618 sizeof(p->segs) / sizeof(p->segs[0]), &p->nsegs, BUS_DMA_NOWAIT); 619 if (err) 620 return err; 621 err = bus_dmamem_map(dmat, p->segs, p->nsegs, p->size, &p->addr, 622 BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 623 if (err) 624 goto free; 625 err = bus_dmamap_create(dmat, p->size, 1, p->size, 0, BUS_DMA_NOWAIT, 626 &p->map); 627 if (err) 628 goto unmap; 629 err = bus_dmamap_load(dmat, p->map, p->addr, p->size, NULL, 630 BUS_DMA_NOWAIT); 631 if (err) 632 goto destroy; 633 634 return 0; 635 636 destroy: 637 bus_dmamap_destroy(dmat, p->map); 638 unmap: 639 bus_dmamem_unmap(dmat, p->addr, p->size); 640 free: 641 bus_dmamem_free(dmat, p->segs, p->nsegs); 642 643 return err; 644 } 645 646 #if !defined(TEGRA124_XUSB_BIN_STATIC) 647 static void 648 fw_dma_free(struct tegra_xusb_softc * const psc, struct fw_dma * const p) 649 { 650 const struct xhci_softc * const sc = &psc->sc_xhci; 651 const bus_dma_tag_t dmat = sc->sc_bus.ub_dmatag; 652 653 bus_dmamap_unload(dmat, p->map); 654 bus_dmamap_destroy(dmat, p->map); 655 bus_dmamem_unmap(dmat, p->addr, p->size); 656 bus_dmamem_free(dmat, p->segs, p->nsegs); 657 } 658 #endif 659 660 #define FWHEADER_BOOT_CODETAG 8 661 #define FWHEADER_BOOT_CODESIZE 12 662 #define FWHEADER_FWIMG_LEN 100 663 #define FWHEADER__LEN 256 664 665 static int 666 tegra_xusb_open_fw(struct tegra_xusb_softc * const psc) 667 { 668 struct xhci_softc * const sc = &psc->sc_xhci; 669 firmware_handle_t fw; 670 size_t firmware_size = 0; 671 void *firmware_image; 672 const char *fw_path = NULL; 673 void *fw_static = NULL; 674 int error; 675 676 switch (psc->sc_type) { 677 case XUSB_T124: 678 #if defined(TEGRA124_XUSB_BIN_STATIC) 679 firmware_size = (uintptr_t)&_binary_tegra124_xusb_bin_size; 680 fw_static = _binary_tegra124_xusb_bin_start; 681 #else 682 fw_path = "nvidia/tegra124"; 683 #endif 684 break; 685 case XUSB_T210: 686 #if defined(TEGRA210_XUSB_BIN_STATIC) 687 firmware_size = (uintptr_t)&_binary_tegra210_xusb_bin_size; 688 fw_static = _binary_tegra210_xusb_bin_start; 689 #else 690 fw_path = "nvidia/tegra210"; 691 #endif 692 break; 693 default: 694 return EINVAL; 695 } 696 697 if (fw_path != NULL) { 698 error = firmware_open(fw_path, "xusb.bin", &fw); 699 if (error != 0) { 700 aprint_error_dev(sc->sc_dev, 701 "couldn't load firmware from %s/xusb.bin: %d\n", 702 fw_path, error); 703 return error; 704 } 705 firmware_size = firmware_get_size(fw); 706 } 707 708 error = fw_dma_alloc(psc, firmware_size, PAGE_SIZE, 709 &psc->sc_fw_dma); 710 if (error != 0) 711 return error; 712 firmware_image = psc->sc_fw_dma.addr; 713 714 if (fw_path != NULL) { 715 error = firmware_read(fw, 0, firmware_image, firmware_size); 716 if (error != 0) { 717 fw_dma_free(psc, &psc->sc_fw_dma); 718 firmware_close(fw); 719 return error; 720 } 721 firmware_close(fw); 722 } else { 723 memcpy(firmware_image, fw_static, firmware_size); 724 } 725 726 return tegra_xusb_load_fw(psc, firmware_image, firmware_size); 727 } 728 729 static int 730 tegra_xusb_load_fw(struct tegra_xusb_softc * const psc, void *firmware_image, 731 size_t firmware_size) 732 { 733 struct xhci_softc * const sc = &psc->sc_xhci; 734 const uint8_t *header; 735 736 header = firmware_image; 737 738 const uint32_t fwimg_len = le32dec(&header[FWHEADER_FWIMG_LEN]); 739 const uint32_t boot_codetag = le32dec(&header[FWHEADER_BOOT_CODETAG]); 740 const uint32_t boot_codesize = le32dec(&header[FWHEADER_BOOT_CODESIZE]); 741 742 if (fwimg_len != firmware_size) 743 aprint_error_dev(sc->sc_dev, "fwimg_len mismatch %u != %zu\n", 744 fwimg_len, firmware_size); 745 746 bus_dmamap_sync(sc->sc_bus.ub_dmatag, psc->sc_fw_dma.map, 0, 747 firmware_size, BUS_DMASYNC_PREWRITE); 748 749 DPRINTF(sc->sc_dev, "XUSB_FALC_CPUCTL 0x%x\n", 750 csb_read_4(psc, XUSB_CSB_FALCON_CPUCTL_REG)); 751 DPRINTF(sc->sc_dev, "XUSB_CSB_MP_ILOAD_BASE_LO 0x%x\n", 752 csb_read_4(psc, XUSB_CSB_MEMPOOL_ILOAD_BASE_LO_REG)); 753 754 DPRINTF(sc->sc_dev, "XUSB_CSB_MP_ILOAD_ATTR 0x%x\n", 755 csb_read_4(psc, XUSB_CSB_MEMPOOL_ILOAD_ATTR_REG)); 756 csb_write_4(psc, XUSB_CSB_MEMPOOL_ILOAD_ATTR_REG, 757 fwimg_len); 758 DPRINTF(sc->sc_dev, "XUSB_CSB_MP_ILOAD_ATTR 0x%x\n", 759 csb_read_4(psc, XUSB_CSB_MEMPOOL_ILOAD_ATTR_REG)); 760 761 const uint64_t fwbase = psc->sc_fw_dma.map->dm_segs[0].ds_addr + 762 FWHEADER__LEN; 763 764 csb_write_4(psc, XUSB_CSB_MEMPOOL_ILOAD_BASE_HI_REG, fwbase >> 32); 765 csb_write_4(psc, XUSB_CSB_MEMPOOL_ILOAD_BASE_LO_REG, fwbase); 766 DPRINTF(sc->sc_dev, "XUSB_CSB_MP_ILOAD_BASE_LO 0x%x\n", 767 csb_read_4(psc, XUSB_CSB_MEMPOOL_ILOAD_BASE_LO_REG)); 768 DPRINTF(sc->sc_dev, "XUSB_CSB_MP_ILOAD_BASE_HI 0x%x\n", 769 csb_read_4(psc, XUSB_CSB_MEMPOOL_ILOAD_BASE_HI_REG)); 770 771 DPRINTF(sc->sc_dev, "XUSB_CSB_MP_APMAP 0x%x\n", 772 csb_read_4(psc, XUSB_CSB_MEMPOOL_APMAP_REG)); 773 csb_write_4(psc, XUSB_CSB_MEMPOOL_APMAP_REG, 774 XUSB_CSB_MEMPOOL_APMAP_BOOTPATH); 775 DPRINTF(sc->sc_dev, "XUSB_CSB_MP_APMAP 0x%x\n", 776 csb_read_4(psc, XUSB_CSB_MEMPOOL_APMAP_REG)); 777 778 DPRINTF(sc->sc_dev, "XUSB_CSB_MP_L2IMEMOP_TRIG 0x%x\n", 779 csb_read_4(psc, XUSB_CSB_MEMPOOL_L2IMEMOP_TRIG_REG)); 780 csb_write_4(psc, XUSB_CSB_MEMPOOL_L2IMEMOP_TRIG_REG, 781 __SHIFTIN(ACTION_L2IMEM_INVALIDATE_ALL, 782 XUSB_CSB_MEMPOOL_L2IMEMOP_TRIG_ACTION)); 783 DPRINTF(sc->sc_dev, "XUSB_CSB_MP_L2IMEMOP_TRIG 0x%x\n", 784 csb_read_4(psc, XUSB_CSB_MEMPOOL_L2IMEMOP_TRIG_REG)); 785 786 const u_int code_tag_blocks = 787 howmany(boot_codetag, IMEM_BLOCK_SIZE); 788 const u_int code_size_blocks = 789 howmany(boot_codesize, IMEM_BLOCK_SIZE); 790 const u_int code_blocks = code_tag_blocks + code_size_blocks; 791 792 DPRINTF(sc->sc_dev, "XUSB_CSB_MP_L2IMEMOP_SIZE 0x%x\n", 793 csb_read_4(psc, XUSB_CSB_MEMPOOL_L2IMEMOP_SIZE_REG)); 794 csb_write_4(psc, XUSB_CSB_MEMPOOL_L2IMEMOP_SIZE_REG, 795 __SHIFTIN(code_tag_blocks, 796 XUSB_CSB_MEMPOOL_L2IMEMOP_SIZE_SRC_OFFSET) | 797 __SHIFTIN(code_size_blocks, 798 XUSB_CSB_MEMPOOL_L2IMEMOP_SIZE_SRC_COUNT)); 799 DPRINTF(sc->sc_dev, "XUSB_CSB_MP_L2IMEMOP_SIZE 0x%x\n", 800 csb_read_4(psc, XUSB_CSB_MEMPOOL_L2IMEMOP_SIZE_REG)); 801 802 DPRINTF(sc->sc_dev, "XUSB_CSB_MP_L2IMEMOP_TRIG 0x%x\n", 803 csb_read_4(psc, XUSB_CSB_MEMPOOL_L2IMEMOP_TRIG_REG)); 804 csb_write_4(psc, XUSB_CSB_MEMPOOL_L2IMEMOP_TRIG_REG, 805 __SHIFTIN(ACTION_L2IMEM_LOAD_LOCKED_RESULT, 806 XUSB_CSB_MEMPOOL_L2IMEMOP_TRIG_ACTION)); 807 DPRINTF(sc->sc_dev, "XUSB_CSB_MP_L2IMEMOP_TRIG 0x%x\n", 808 csb_read_4(psc, XUSB_CSB_MEMPOOL_L2IMEMOP_TRIG_REG)); 809 810 DPRINTF(sc->sc_dev, "XUSB_FALC_IMFILLCTL 0x%x\n", 811 csb_read_4(psc, XUSB_CSB_FALCON_IMFILLCTL_REG)); 812 csb_write_4(psc, XUSB_CSB_FALCON_IMFILLCTL_REG, code_size_blocks); 813 DPRINTF(sc->sc_dev, "XUSB_FALC_IMFILLCTL 0x%x\n", 814 csb_read_4(psc, XUSB_CSB_FALCON_IMFILLCTL_REG)); 815 816 DPRINTF(sc->sc_dev, "XUSB_FALC_IMFILLRNG1 0x%x\n", 817 csb_read_4(psc, XUSB_CSB_FALCON_IMFILLRNG1_REG)); 818 csb_write_4(psc, XUSB_CSB_FALCON_IMFILLRNG1_REG, 819 __SHIFTIN(code_tag_blocks, XUSB_CSB_FALCON_IMFILLRNG1_TAG_LO) | 820 __SHIFTIN(code_blocks, XUSB_CSB_FALCON_IMFILLRNG1_TAG_HI)); 821 DPRINTF(sc->sc_dev, "XUSB_FALC_IMFILLRNG1 0x%x\n", 822 csb_read_4(psc, XUSB_CSB_FALCON_IMFILLRNG1_REG)); 823 824 DPRINTF(sc->sc_dev, "XUSB_FALC_DMACTL 0x%x\n", 825 csb_read_4(psc, XUSB_CSB_FALCON_DMACTL_REG)); 826 csb_write_4(psc, XUSB_CSB_FALCON_DMACTL_REG, 0); 827 DPRINTF(sc->sc_dev, "XUSB_FALC_DMACTL 0x%x\n", 828 csb_read_4(psc, XUSB_CSB_FALCON_DMACTL_REG)); 829 830 DPRINTF(sc->sc_dev, "XUSB_FALC_BOOTVEC 0x%x\n", 831 csb_read_4(psc, XUSB_CSB_FALCON_BOOTVEC_REG)); 832 csb_write_4(psc, XUSB_CSB_FALCON_BOOTVEC_REG, 833 boot_codetag); 834 DPRINTF(sc->sc_dev, "XUSB_FALC_BOOTVEC 0x%x\n", 835 csb_read_4(psc, XUSB_CSB_FALCON_BOOTVEC_REG)); 836 837 DPRINTF(sc->sc_dev, "XUSB_FALC_CPUCTL 0x%x\n", 838 csb_read_4(psc, XUSB_CSB_FALCON_CPUCTL_REG)); 839 csb_write_4(psc, XUSB_CSB_FALCON_CPUCTL_REG, 840 XUSB_CSB_FALCON_CPUCTL_STARTCPU); 841 DPRINTF(sc->sc_dev, "XUSB_FALC_CPUCTL 0x%x\n", 842 csb_read_4(psc, XUSB_CSB_FALCON_CPUCTL_REG)); 843 844 return 0; 845 } 846 847 static uint32_t 848 csb_read_4(struct tegra_xusb_softc * const psc, bus_size_t csb_offset) 849 { 850 const uint32_t range = __SHIFTOUT(csb_offset, XUSB_CSB_RANGE); 851 const bus_size_t offset = __SHIFTOUT(csb_offset, XUSB_CSB_OFFSET); 852 const bus_space_tag_t bst = psc->sc_xhci.sc_iot; 853 const bus_space_handle_t fpcih = psc->sc_bsh_fpci; 854 855 bus_space_write_4(bst, fpcih, T_XUSB_CFG_ARU_C11_CSBRANGE_REG, range); 856 return bus_space_read_4(bst, fpcih, T_XUSB_CFG_CSB_BASE_ADDR + offset); 857 } 858 859 static void 860 csb_write_4(struct tegra_xusb_softc * const psc, bus_size_t csb_offset, 861 uint32_t value) 862 { 863 const uint32_t range = __SHIFTOUT(csb_offset, XUSB_CSB_RANGE); 864 const bus_size_t offset = __SHIFTOUT(csb_offset, XUSB_CSB_OFFSET); 865 const bus_space_tag_t bst = psc->sc_xhci.sc_iot; 866 const bus_space_handle_t fpcih = psc->sc_bsh_fpci; 867 868 bus_space_write_4(bst, fpcih, T_XUSB_CFG_ARU_C11_CSBRANGE_REG, range); 869 bus_space_write_4(bst, fpcih, T_XUSB_CFG_CSB_BASE_ADDR + offset, value); 870 } 871 872 static int 873 xusb_mailbox_send(struct tegra_xusb_softc * const psc, uint32_t msg) 874 { 875 struct xhci_softc * const sc = &psc->sc_xhci; 876 const bus_space_tag_t bst = psc->sc_xhci.sc_iot; 877 const bus_space_handle_t fpcih = psc->sc_bsh_fpci; 878 uint32_t val; 879 bool wait = false; 880 881 const uint8_t type = __SHIFTOUT(msg, MAILBOX_DATA_TYPE); 882 883 if (!(type == 128 || type == 129)) { 884 val = bus_space_read_4(bst, fpcih, 885 T_XUSB_CFG_ARU_MAILBOX_OWNER_REG); 886 DPRINTF(sc->sc_dev, "XUSB_CFG_ARU_MBOX_OWNER 0x%x\n", 887 val); 888 if (val != MAILBOX_OWNER_NONE) { 889 return EBUSY; 890 } 891 892 bus_space_write_4(bst, fpcih, T_XUSB_CFG_ARU_MAILBOX_OWNER_REG, 893 MAILBOX_OWNER_SW); 894 895 val = bus_space_read_4(bst, fpcih, 896 T_XUSB_CFG_ARU_MAILBOX_OWNER_REG); 897 DPRINTF(sc->sc_dev, "XUSB_CFG_ARU_MBOX_OWNER 0x%x\n", 898 val); 899 if (val != MAILBOX_OWNER_SW) { 900 return EBUSY; 901 } 902 903 wait = true; 904 } 905 906 bus_space_write_4(bst, fpcih, T_XUSB_CFG_ARU_MAILBOX_DATA_IN_REG, msg); 907 908 tegra_reg_set_clear(bst, fpcih, T_XUSB_CFG_ARU_MAILBOX_CMD_REG, 909 T_XUSB_CFG_ARU_MAILBOX_CMD_INT_EN | 910 T_XUSB_CFG_ARU_MAILBOX_CMD_DEST_FALCON, 0); 911 912 if (wait) { 913 914 for (u_int i = 0; i < 2500; i++) { 915 val = bus_space_read_4(bst, fpcih, 916 T_XUSB_CFG_ARU_MAILBOX_OWNER_REG); 917 DPRINTF(sc->sc_dev, 918 "XUSB_CFG_ARU_MBOX_OWNER 0x%x\n", val); 919 if (val == MAILBOX_OWNER_NONE) { 920 break; 921 } 922 DELAY(10); 923 } 924 925 val = bus_space_read_4(bst, fpcih, 926 T_XUSB_CFG_ARU_MAILBOX_OWNER_REG); 927 DPRINTF(sc->sc_dev, 928 "XUSB_CFG_ARU_MBOX_OWNER 0x%x\n", val); 929 if (val != MAILBOX_OWNER_NONE) { 930 aprint_error_dev(sc->sc_dev, 931 "timeout, XUSB_CFG_ARU_MBOX_OWNER 0x%x\n", val); 932 } 933 } 934 935 return 0; 936 } 937
Indexes created Thu Sep 25 08:09:54 GMT 2025