tegra_xusb.c revision 1.12
1 /* $NetBSD: tegra_xusb.c,v 1.12 2017/09/26 16:12:45 jmcneill Exp $ */ 2 3 /* 4 * Copyright (c) 2016 Jonathan A. Kollasch 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR 20 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 21 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 22 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 23 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 25 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 26 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include "locators.h" 30 #include "opt_tegra.h" 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: tegra_xusb.c,v 1.12 2017/09/26 16:12:45 jmcneill Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/bus.h> 37 #include <sys/device.h> 38 #include <sys/intr.h> 39 #include <sys/systm.h> 40 #include <sys/kernel.h> 41 42 #include <arm/nvidia/tegra_reg.h> 43 #include <arm/nvidia/tegra_var.h> 44 #include <arm/nvidia/tegra_xusbpad.h> 45 #include <arm/nvidia/tegra_xusbreg.h> 46 #include <arm/nvidia/tegra_pmcreg.h> 47 48 #include <dev/pci/pcireg.h> 49 50 #include <dev/fdt/fdtvar.h> 51 52 #include <dev/firmload.h> 53 54 #include <dev/usb/usb.h> 55 #include <dev/usb/usbdi.h> 56 #include <dev/usb/usbdivar.h> 57 #include <dev/usb/usb_mem.h> 58 59 #include <dev/usb/xhcireg.h> 60 #include <dev/usb/xhcivar.h> 61 62 #ifdef TEGRA_XUSB_DEBUG 63 int tegra_xusb_debug = 1; 64 #else 65 int tegra_xusb_debug = 0; 66 #endif 67 68 #define DPRINTF(...) if (tegra_xusb_debug) device_printf(__VA_ARGS__) 69 70 static int tegra_xusb_match(device_t, cfdata_t, void *); 71 static void tegra_xusb_attach(device_t, device_t, void *); 72 static void tegra_xusb_mountroot(device_t); 73 74 static int tegra_xusb_intr_mbox(void *); 75 76 #ifdef TEGRA124_XUSB_BIN_STATIC 77 extern const char _binary_tegra124_xusb_bin_size[]; 78 extern const char _binary_tegra124_xusb_bin_start[]; 79 #endif 80 81 #ifdef TEGRA210_XUSB_BIN_STATIC 82 extern const char _binary_tegra210_xusb_bin_size[]; 83 extern const char _binary_tegra210_xusb_bin_start[]; 84 #endif 85 86 enum xusb_type { 87 XUSB_T124 = 1, 88 XUSB_T210 89 }; 90 91 static const struct of_compat_data compat_data[] = { 92 { "nvidia,tegra124-xusb", XUSB_T124 }, 93 { "nvidia,tegra210-xusb", XUSB_T210 }, 94 { NULL } 95 }; 96 97 struct fw_dma { 98 bus_dmamap_t map; 99 void * addr; 100 bus_dma_segment_t segs[1]; 101 int nsegs; 102 size_t size; 103 }; 104 105 struct tegra_xusb_softc { 106 struct xhci_softc sc_xhci; 107 int sc_phandle; 108 bus_space_handle_t sc_bsh_xhci; 109 bus_space_handle_t sc_bsh_fpci; 110 bus_space_handle_t sc_bsh_ipfs; 111 void *sc_ih; 112 void *sc_ih_mbox; 113 struct fw_dma sc_fw_dma; 114 struct clk *sc_clk_ss_src; 115 enum xusb_type sc_type; 116 117 bool sc_scale_ss_clock; 118 }; 119 120 static uint32_t csb_read_4(struct tegra_xusb_softc * const, bus_size_t); 121 static void csb_write_4(struct tegra_xusb_softc * const, bus_size_t, 122 uint32_t); 123 124 static void tegra_xusb_init(struct tegra_xusb_softc * const); 125 static int tegra_xusb_open_fw(struct tegra_xusb_softc * const); 126 static int tegra_xusb_load_fw(struct tegra_xusb_softc * const, void *, 127 size_t); 128 static void tegra_xusb_init_regulators(struct tegra_xusb_softc * const); 129 130 static int xusb_mailbox_send(struct tegra_xusb_softc * const, uint32_t); 131 132 CFATTACH_DECL_NEW(tegra_xusb, sizeof(struct tegra_xusb_softc), 133 tegra_xusb_match, tegra_xusb_attach, NULL, NULL); 134 135 static int 136 tegra_xusb_match(device_t parent, cfdata_t cf, void *aux) 137 { 138 struct fdt_attach_args * const faa = aux; 139 140 return of_match_compat_data(faa->faa_phandle, compat_data); 141 } 142 143 #define tegra_xusb_attach_check(sc, cond, fmt, ...) \ 144 do { \ 145 if (cond) { \ 146 aprint_error_dev(sc->sc_dev, fmt, ## __VA_ARGS__); \ 147 return; \ 148 } \ 149 } while (0) 150 151 static void 152 tegra_xusb_attach(device_t parent, device_t self, void *aux) 153 { 154 struct tegra_xusb_softc * const psc = device_private(self); 155 struct xhci_softc * const sc = &psc->sc_xhci; 156 struct fdt_attach_args * const faa = aux; 157 bool wait_for_root = true; 158 char intrstr[128]; 159 bus_addr_t addr; 160 bus_size_t size; 161 struct fdtbus_reset *rst; 162 struct fdtbus_phy *phy; 163 struct clk *clk; 164 uint32_t rate; 165 int error, n; 166 167 aprint_naive("\n"); 168 aprint_normal(": XUSB\n"); 169 170 sc->sc_dev = self; 171 sc->sc_iot = faa->faa_bst; 172 sc->sc_bus.ub_hcpriv = sc; 173 sc->sc_bus.ub_dmatag = faa->faa_dmat; 174 sc->sc_quirks = XHCI_DEFERRED_START; 175 psc->sc_phandle = faa->faa_phandle; 176 psc->sc_type = of_search_compatible(faa->faa_phandle, compat_data)->data; 177 178 switch (psc->sc_type) { 179 case XUSB_T124: 180 psc->sc_scale_ss_clock = true; 181 break; 182 default: 183 psc->sc_scale_ss_clock = false; 184 break; 185 } 186 187 if (fdtbus_get_reg_byname(faa->faa_phandle, "hcd", &addr, &size) != 0) { 188 aprint_error(": couldn't get registers\n"); 189 return; 190 } 191 error = bus_space_map(sc->sc_iot, addr, size, 0, &sc->sc_ioh); 192 if (error) { 193 aprint_error(": couldn't map %#llx: %d", (uint64_t)addr, error); 194 return; 195 } 196 DPRINTF(sc->sc_dev, "mapped %#llx\n", (uint64_t)addr); 197 198 if (fdtbus_get_reg_byname(faa->faa_phandle, "fpci", &addr, &size) != 0) { 199 aprint_error(": couldn't get registers\n"); 200 return; 201 } 202 error = bus_space_map(sc->sc_iot, addr, size, 0, &psc->sc_bsh_fpci); 203 if (error) { 204 aprint_error(": couldn't map %#llx: %d", (uint64_t)addr, error); 205 return; 206 } 207 DPRINTF(sc->sc_dev, "mapped %#llx\n", (uint64_t)addr); 208 209 if (fdtbus_get_reg_byname(faa->faa_phandle, "ipfs", &addr, &size) != 0) { 210 aprint_error(": couldn't get registers\n"); 211 return; 212 } 213 error = bus_space_map(sc->sc_iot, addr, size, 0, &psc->sc_bsh_ipfs); 214 if (error) { 215 aprint_error(": couldn't map %#llx: %d", (uint64_t)addr, error); 216 return; 217 } 218 DPRINTF(sc->sc_dev, "mapped %#llx\n", (uint64_t)addr); 219 220 if (!fdtbus_intr_str(faa->faa_phandle, 0, intrstr, sizeof(intrstr))) { 221 aprint_error_dev(self, "failed to decode interrupt\n"); 222 return; 223 } 224 225 psc->sc_ih = fdtbus_intr_establish(faa->faa_phandle, 0, IPL_USB, 226 FDT_INTR_MPSAFE, xhci_intr, sc); 227 if (psc->sc_ih == NULL) { 228 aprint_error_dev(self, "failed to establish interrupt on %s\n", 229 intrstr); 230 return; 231 } 232 aprint_normal_dev(self, "interrupting on %s\n", intrstr); 233 234 if (!fdtbus_intr_str(faa->faa_phandle, 1, intrstr, sizeof(intrstr))) { 235 aprint_error_dev(self, "failed to decode interrupt\n"); 236 return; 237 } 238 239 psc->sc_ih_mbox = fdtbus_intr_establish(faa->faa_phandle, 1, IPL_VM, 240 FDT_INTR_MPSAFE, tegra_xusb_intr_mbox, psc); 241 if (psc->sc_ih_mbox == NULL) { 242 aprint_error_dev(self, "failed to establish interrupt on %s\n", 243 intrstr); 244 return; 245 } 246 aprint_normal_dev(self, "interrupting on %s\n", intrstr); 247 248 /* Enable PHYs */ 249 for (n = 0; (phy = fdtbus_phy_get_index(faa->faa_phandle, n)) != NULL; n++) 250 if (fdtbus_phy_enable(phy, true) != 0) 251 aprint_error_dev(self, "failed to enable PHY #%d\n", n); 252 253 /* Enable XUSB power rails */ 254 255 tegra_pmc_power(PMC_PARTID_XUSBC, true); /* Host/USB2.0 */ 256 tegra_pmc_remove_clamping(PMC_PARTID_XUSBC); 257 tegra_pmc_power(PMC_PARTID_XUSBA, true); /* SuperSpeed */ 258 tegra_pmc_remove_clamping(PMC_PARTID_XUSBA); 259 260 /* Enable XUSB clocks */ 261 262 clk = fdtbus_clock_get(faa->faa_phandle, "pll_e"); 263 rate = clk_get_rate(clk); 264 error = clk_enable(clk); /* XXX set frequency */ 265 DPRINTF(sc->sc_dev, "rate %u error %d\n", rate, error); 266 tegra_xusb_attach_check(sc, error, "failed to enable pll_e clock"); 267 268 clk = fdtbus_clock_get(faa->faa_phandle, "xusb_host_src"); 269 rate = clk_get_rate(clk); 270 DPRINTF(sc->sc_dev, "rate %u error %d\n", rate, error); 271 error = clk_set_rate(clk, 102000000); 272 tegra_xusb_attach_check(sc, error, "failed to set xusb_host_src clock rate"); 273 274 rate = clk_get_rate(clk); 275 error = clk_enable(clk); /* XXX set frequency */ 276 DPRINTF(sc->sc_dev, "rate %u error %d\n", rate, error); 277 tegra_xusb_attach_check(sc, error, "failed to enable xusb_host_src clock"); 278 279 clk = fdtbus_clock_get(faa->faa_phandle, "xusb_falcon_src"); 280 rate = clk_get_rate(clk); 281 DPRINTF(sc->sc_dev, "rate %u error %d\n", rate, error); 282 error = clk_set_rate(clk, 204000000); 283 tegra_xusb_attach_check(sc, error, "failed to set xusb_falcon_src clock rate"); 284 285 rate = clk_get_rate(clk); 286 error = clk_enable(clk); 287 DPRINTF(sc->sc_dev, "rate %u error %d\n", rate, error); 288 tegra_xusb_attach_check(sc, error, "failed to enable xusb_falcon_src clock"); 289 290 clk = fdtbus_clock_get(faa->faa_phandle, "xusb_host"); 291 rate = clk_get_rate(clk); 292 error = clk_enable(clk); /* XXX set frequency */ 293 DPRINTF(sc->sc_dev, "rate %u error %d\n", rate, error); 294 295 clk = fdtbus_clock_get(faa->faa_phandle, "xusb_ss"); 296 rate = clk_get_rate(clk); 297 error = clk_enable(clk); /* XXX set frequency */ 298 DPRINTF(sc->sc_dev, "xusb_ss rate %u error %d\n", rate, error); 299 tegra_xusb_attach_check(sc, error, "failed to enable xusb_ss clock"); 300 301 psc->sc_clk_ss_src = fdtbus_clock_get(faa->faa_phandle, "xusb_ss_src"); 302 tegra_xusb_attach_check(sc, psc->sc_clk_ss_src == NULL, 303 "failed to get xusb_ss_src clock"); 304 305 if (psc->sc_scale_ss_clock) { 306 rate = clk_get_rate(psc->sc_clk_ss_src); 307 DPRINTF(sc->sc_dev, "xusb_ss_src rate %u\n", rate); 308 error = clk_set_rate(psc->sc_clk_ss_src, 2000000); 309 rate = clk_get_rate(psc->sc_clk_ss_src); 310 DPRINTF(sc->sc_dev, "xusb_ss_src rate %u error %d\n", rate, error); 311 tegra_xusb_attach_check(sc, error, "failed to get xusb_ss_src clock rate"); 312 313 rate = clk_get_rate(psc->sc_clk_ss_src); 314 DPRINTF(sc->sc_dev, "ss_src rate %u\n", rate); 315 tegra_xusb_attach_check(sc, error, "failed to set xusb_ss_src clock rate"); 316 317 error = clk_set_rate(psc->sc_clk_ss_src, 120000000); 318 rate = clk_get_rate(psc->sc_clk_ss_src); 319 DPRINTF(sc->sc_dev, "ss_src rate %u error %d\n", rate, error); 320 tegra_xusb_attach_check(sc, error, "failed to get xusb_ss_src clock rate"); 321 } 322 323 rate = clk_get_rate(psc->sc_clk_ss_src); 324 error = clk_enable(psc->sc_clk_ss_src); 325 DPRINTF(sc->sc_dev, "ss_src rate %u error %d\n", rate, error); 326 tegra_xusb_attach_check(sc, error, "failed to enable xusb_ss_src clock"); 327 328 #if 0 329 clk = fdtbus_clock_get(faa->faa_phandle, "xusb_hs_src"); 330 error = 0; 331 rate = clk_get_rate(clk); 332 DPRINTF(sc->sc_dev, "rate %u error %d\n", rate, error); 333 #endif 334 335 clk = fdtbus_clock_get(faa->faa_phandle, "xusb_fs_src"); 336 rate = clk_get_rate(clk); 337 error = clk_enable(clk); /* XXX set frequency */ 338 DPRINTF(sc->sc_dev, "rate %u error %d\n", rate, error); 339 tegra_xusb_attach_check(sc, error, "failed to enable xusb_fs_src clock"); 340 341 rst = fdtbus_reset_get(faa->faa_phandle, "xusb_host"); 342 fdtbus_reset_deassert(rst); 343 344 rst = fdtbus_reset_get(faa->faa_phandle, "xusb_src"); 345 fdtbus_reset_deassert(rst); 346 347 rst = fdtbus_reset_get(faa->faa_phandle, "xusb_ss"); 348 fdtbus_reset_deassert(rst); 349 350 DELAY(1); 351 352 tegra_xusb_init_regulators(psc); 353 354 tegra_xusb_init(psc); 355 356 #if defined(TEGRA124_XUSB_BIN_STATIC) 357 if (psc->sc_type == XUSB_T124) 358 wait_for_root = false; 359 #endif 360 #if defined(TEGRA210_XUSB_BIN_STATIC) 361 if (psc->sc_type == XUSB_T210) 362 wait_for_root = false; 363 #endif 364 365 if (wait_for_root) 366 config_mountroot(sc->sc_dev, tegra_xusb_mountroot); 367 else 368 tegra_xusb_mountroot(sc->sc_dev); 369 } 370 371 static void 372 tegra_xusb_mountroot(device_t self) 373 { 374 struct tegra_xusb_softc * const psc = device_private(self); 375 struct xhci_softc * const sc = &psc->sc_xhci; 376 const bus_space_tag_t bst = sc->sc_iot; 377 const bus_space_handle_t ipfsh = psc->sc_bsh_ipfs; 378 struct clk *clk; 379 struct fdtbus_reset *rst; 380 uint32_t rate; 381 uint32_t val; 382 int error; 383 384 DPRINTF(sc->sc_dev, "%s()\n", __func__); 385 386 val = bus_space_read_4(bst, ipfsh, 0x0); 387 DPRINTF(sc->sc_dev, "%s ipfs 0x0 = 0x%x\n", __func__, val); 388 389 if (tegra_xusb_open_fw(psc) != 0) 390 return; 391 DPRINTF(sc->sc_dev, "post fw\n"); 392 393 tegra_xusbpad_xhci_enable(); 394 395 clk = fdtbus_clock_get(psc->sc_phandle, "xusb_falcon_src"); 396 rate = clk_get_rate(clk); 397 error = clk_enable(clk); 398 DPRINTF(sc->sc_dev, "rate %u error %d\n", rate, error); 399 400 clk = fdtbus_clock_get(psc->sc_phandle, "xusb_host_src"); 401 rate = clk_get_rate(clk); 402 error = clk_enable(clk); 403 DPRINTF(sc->sc_dev, "rate %u error %d\n", rate, error); 404 405 val = bus_space_read_4(bst, ipfsh, 0x0); 406 DPRINTF(sc->sc_dev, "%s ipfs 0x0 = 0x%x\n", __func__, val); 407 408 rst = fdtbus_reset_get(psc->sc_phandle, "xusb_host"); 409 fdtbus_reset_deassert(rst); 410 411 rst = fdtbus_reset_get(psc->sc_phandle, "xusb_src"); 412 fdtbus_reset_deassert(rst); 413 414 rst = fdtbus_reset_get(psc->sc_phandle, "xusb_ss"); 415 fdtbus_reset_deassert(rst); 416 417 val = csb_read_4(psc, XUSB_CSB_FALCON_CPUCTL_REG); 418 DPRINTF(sc->sc_dev, "XUSB_FALC_CPUCTL 0x%x\n", val); 419 420 error = xhci_init(sc); 421 if (error) { 422 aprint_error_dev(self, "init failed, error=%d\n", error); 423 return; 424 } 425 426 sc->sc_child = config_found(self, &sc->sc_bus, usbctlprint); 427 428 sc->sc_child2 = config_found(self, &sc->sc_bus2, usbctlprint); 429 430 xhci_start(sc); 431 432 error = xusb_mailbox_send(psc, 0x01000000); 433 if (error) { 434 aprint_error_dev(self, "send failed, error=%d\n", error); 435 } 436 } 437 438 static int 439 tegra_xusb_intr_mbox(void *v) 440 { 441 struct tegra_xusb_softc * const psc = v; 442 struct xhci_softc * const sc = &psc->sc_xhci; 443 const bus_space_tag_t bst = sc->sc_iot; 444 const bus_space_handle_t fpcih = psc->sc_bsh_fpci; 445 uint32_t val; 446 uint32_t irv; 447 uint32_t msg; 448 int error; 449 450 DPRINTF(sc->sc_dev, "%s()\n", __func__); 451 452 irv = bus_space_read_4(bst, fpcih, T_XUSB_CFG_ARU_SMI_INTR_REG); 453 DPRINTF(sc->sc_dev, "XUSB_CFG_ARU_SMI_INTR 0x%x\n", irv); 454 bus_space_write_4(bst, fpcih, T_XUSB_CFG_ARU_SMI_INTR_REG, irv); 455 456 if (irv & T_XUSB_CFG_ARU_SMI_INTR_FW_HANG) 457 aprint_error_dev(sc->sc_dev, "firmware hang\n"); 458 459 msg = bus_space_read_4(bst, fpcih, T_XUSB_CFG_ARU_MAILBOX_DATA_OUT_REG); 460 DPRINTF(sc->sc_dev, "XUSB_CFG_ARU_MBOX_DATA_OUT 0x%x\n", msg); 461 462 val = bus_space_read_4(bst, fpcih, T_XUSB_CFG_ARU_MAILBOX_CMD_REG); 463 DPRINTF(sc->sc_dev, "XUSB_CFG_ARU_MBOX_CMD 0x%x\n", val); 464 val &= ~T_XUSB_CFG_ARU_MAILBOX_CMD_DEST_SMI; 465 bus_space_write_4(bst, fpcih, T_XUSB_CFG_ARU_MAILBOX_CMD_REG, val); 466 467 bool sendresp = true; 468 u_int rate; 469 470 const uint32_t data = __SHIFTOUT(msg, MAILBOX_DATA_DATA); 471 const uint8_t type = __SHIFTOUT(msg, MAILBOX_DATA_TYPE); 472 473 switch (type) { 474 case 2: 475 case 3: 476 DPRINTF(sc->sc_dev, "FALC_CLOCK %u\n", data * 1000); 477 break; 478 case 4: 479 case 5: 480 if (psc->sc_scale_ss_clock) { 481 DPRINTF(sc->sc_dev, "SSPI_CLOCK %u\n", data * 1000); 482 rate = clk_get_rate(psc->sc_clk_ss_src); 483 DPRINTF(sc->sc_dev, "rate of psc->sc_clk_ss_src %u\n", 484 rate); 485 error = clk_set_rate(psc->sc_clk_ss_src, data * 1000); 486 if (error != 0) 487 goto clk_fail; 488 rate = clk_get_rate(psc->sc_clk_ss_src); 489 DPRINTF(sc->sc_dev, 490 "rate of psc->sc_clk_ss_src %u after\n", rate); 491 if (data == (rate / 1000)) { 492 msg = __SHIFTIN(128, MAILBOX_DATA_TYPE) | 493 __SHIFTIN(rate / 1000, MAILBOX_DATA_DATA); 494 } else 495 clk_fail: 496 msg = __SHIFTIN(129, MAILBOX_DATA_TYPE) | 497 __SHIFTIN(rate / 1000, MAILBOX_DATA_DATA); 498 } else { 499 msg = __SHIFTIN(128, MAILBOX_DATA_TYPE) | 500 __SHIFTIN(data, MAILBOX_DATA_DATA); 501 } 502 xusb_mailbox_send(psc, msg); 503 break; 504 case 9: 505 msg = __SHIFTIN(data, MAILBOX_DATA_DATA) | 506 __SHIFTIN(128, MAILBOX_DATA_TYPE); 507 xusb_mailbox_send(psc, msg); 508 break; 509 case 6: 510 case 128: 511 case 129: 512 sendresp = false; 513 break; 514 default: 515 sendresp = false; 516 break; 517 } 518 519 if (sendresp == false) 520 bus_space_write_4(bst, fpcih, T_XUSB_CFG_ARU_MAILBOX_OWNER_REG, 521 MAILBOX_OWNER_NONE); 522 523 return irv; 524 } 525 526 static void 527 tegra_xusb_init_regulators(struct tegra_xusb_softc * const psc) 528 { 529 const char * supply_names[] = { 530 "dvddio-pex-supply", 531 "hvddio-pex-supply", 532 "avdd-usb-supply", 533 "avdd-pll-utmip-supply", 534 "avdd-pll-uerefe-supply", 535 "dvdd-usb-ss-pll-supply", 536 "hvdd-usb-ss-pll-e-supply" 537 }; 538 device_t dev = psc->sc_xhci.sc_dev; 539 const int phandle = psc->sc_phandle; 540 struct fdtbus_regulator *reg; 541 int n, error; 542 543 for (n = 0; n < __arraycount(supply_names); n++) { 544 if (!of_hasprop(phandle, supply_names[n])) 545 continue; 546 reg = fdtbus_regulator_acquire(phandle, supply_names[n]); 547 if (reg == NULL) { 548 aprint_error_dev(dev, "couldn't acquire supply '%s'\n", 549 supply_names[n]); 550 continue; 551 } 552 error = fdtbus_regulator_enable(reg); 553 if (error != 0) 554 aprint_error_dev(dev, "couldn't enable supply '%s': %d\n", 555 supply_names[n], error); 556 } 557 } 558 559 static void 560 tegra_xusb_init(struct tegra_xusb_softc * const psc) 561 { 562 struct xhci_softc * const sc = &psc->sc_xhci; 563 const bus_space_tag_t bst = sc->sc_iot; 564 const bus_space_handle_t ipfsh = psc->sc_bsh_ipfs; 565 const bus_space_handle_t fpcih = psc->sc_bsh_fpci; 566 567 DPRINTF(sc->sc_dev, "%s()\n", __func__); 568 569 DPRINTF(sc->sc_dev, "%s ipfs 0x0 = 0x%x\n", __func__, 570 bus_space_read_4(bst, ipfsh, 0x0)); 571 572 DPRINTF(sc->sc_dev, "%s ipfs 0x40 = 0x%x\n", __func__, 573 bus_space_read_4(bst, ipfsh, 0x40)); 574 575 DPRINTF(sc->sc_dev, "%s ipfs 0x80 = 0x%x\n", __func__, 576 bus_space_read_4(bst, ipfsh, 0x80)); 577 /* FPCI_BAR0_START and FPCI_BAR0_ACCESS_TYPE */ 578 bus_space_write_4(bst, ipfsh, 0x80, 0x00100000); 579 DPRINTF(sc->sc_dev, "%s ipfs 0x80 = 0x%x\n", __func__, 580 bus_space_read_4(bst, ipfsh, 0x80)); 581 582 DPRINTF(sc->sc_dev, "%s ipfs 0x180 = 0x%x\n", __func__, 583 bus_space_read_4(bst, ipfsh, 0x180)); 584 /* EN_FPCI */ 585 tegra_reg_set_clear(bst, ipfsh, 0x180, 1, 0); 586 DPRINTF(sc->sc_dev, "%s ipfs 0x180 = 0x%x\n", __func__, 587 bus_space_read_4(bst, ipfsh, 0x180)); 588 589 DPRINTF(sc->sc_dev, "%s fpci PCI_COMMAND_STATUS_REG = 0x%x\n", 590 __func__, bus_space_read_4(bst, fpcih, PCI_COMMAND_STATUS_REG)); 591 tegra_reg_set_clear(bst, fpcih, PCI_COMMAND_STATUS_REG, 592 PCI_COMMAND_MASTER_ENABLE|PCI_COMMAND_MEM_ENABLE, 0x0); 593 DPRINTF(sc->sc_dev, "%s fpci PCI_COMMAND_STATUS_REG = 0x%x\n", 594 __func__, bus_space_read_4(bst, fpcih, PCI_COMMAND_STATUS_REG)); 595 596 DPRINTF(sc->sc_dev, "%s fpci PCI_BAR0 = 0x%x\n", __func__, 597 bus_space_read_4(bst, fpcih, PCI_BAR0)); 598 /* match FPCI BAR0 to above */ 599 bus_space_write_4(bst, fpcih, PCI_BAR0, 0x10000000); 600 DPRINTF(sc->sc_dev, "%s fpci PCI_BAR0 = 0x%x\n", __func__, 601 bus_space_read_4(bst, fpcih, PCI_BAR0)); 602 603 DPRINTF(sc->sc_dev, "%s ipfs 0x188 = 0x%x\n", __func__, 604 bus_space_read_4(bst, ipfsh, 0x188)); 605 tegra_reg_set_clear(bst, ipfsh, 0x188, __BIT(16), 0); 606 DPRINTF(sc->sc_dev, "%s ipfs 0x188 = 0x%x\n", __func__, 607 bus_space_read_4(bst, ipfsh, 0x188)); 608 609 DPRINTF(sc->sc_dev, "%s fpci 0x1bc = 0x%x\n", __func__, 610 bus_space_read_4(bst, fpcih, 0x1bc)); 611 bus_space_write_4(bst, fpcih, 0x1bc, 0x80); 612 DPRINTF(sc->sc_dev, "%s fpci 0x1bc = 0x%x\n", __func__, 613 bus_space_read_4(bst, fpcih, 0x1bc)); 614 } 615 616 static int 617 fw_dma_alloc(struct tegra_xusb_softc * const psc, size_t size, size_t align, 618 struct fw_dma * const p) 619 { 620 struct xhci_softc * const sc = &psc->sc_xhci; 621 const bus_dma_tag_t dmat = sc->sc_bus.ub_dmatag; 622 int err; 623 624 p->size = size; 625 err = bus_dmamem_alloc(dmat, p->size, align, 0, p->segs, 626 sizeof(p->segs) / sizeof(p->segs[0]), &p->nsegs, BUS_DMA_NOWAIT); 627 if (err) 628 return err; 629 err = bus_dmamem_map(dmat, p->segs, p->nsegs, p->size, &p->addr, 630 BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 631 if (err) 632 goto free; 633 err = bus_dmamap_create(dmat, p->size, 1, p->size, 0, BUS_DMA_NOWAIT, 634 &p->map); 635 if (err) 636 goto unmap; 637 err = bus_dmamap_load(dmat, p->map, p->addr, p->size, NULL, 638 BUS_DMA_NOWAIT); 639 if (err) 640 goto destroy; 641 642 return 0; 643 644 destroy: 645 bus_dmamap_destroy(dmat, p->map); 646 unmap: 647 bus_dmamem_unmap(dmat, p->addr, p->size); 648 free: 649 bus_dmamem_free(dmat, p->segs, p->nsegs); 650 651 return err; 652 } 653 654 #if !defined(TEGRA124_XUSB_BIN_STATIC) 655 static void 656 fw_dma_free(struct tegra_xusb_softc * const psc, struct fw_dma * const p) 657 { 658 const struct xhci_softc * const sc = &psc->sc_xhci; 659 const bus_dma_tag_t dmat = sc->sc_bus.ub_dmatag; 660 661 bus_dmamap_unload(dmat, p->map); 662 bus_dmamap_destroy(dmat, p->map); 663 bus_dmamem_unmap(dmat, p->addr, p->size); 664 bus_dmamem_free(dmat, p->segs, p->nsegs); 665 } 666 #endif 667 668 #define FWHEADER_BOOT_CODETAG 8 669 #define FWHEADER_BOOT_CODESIZE 12 670 #define FWHEADER_FWIMG_LEN 100 671 #define FWHEADER__LEN 256 672 673 static int 674 tegra_xusb_open_fw(struct tegra_xusb_softc * const psc) 675 { 676 struct xhci_softc * const sc = &psc->sc_xhci; 677 firmware_handle_t fw; 678 size_t firmware_size = 0; 679 void *firmware_image; 680 const char *fw_path = NULL; 681 void *fw_static = NULL; 682 int error; 683 684 switch (psc->sc_type) { 685 case XUSB_T124: 686 #if defined(TEGRA124_XUSB_BIN_STATIC) 687 firmware_size = (uintptr_t)&_binary_tegra124_xusb_bin_size; 688 fw_static = _binary_tegra124_xusb_bin_start; 689 #else 690 fw_path = "nvidia/tegra124"; 691 #endif 692 break; 693 case XUSB_T210: 694 #if defined(TEGRA210_XUSB_BIN_STATIC) 695 firmware_size = (uintptr_t)&_binary_tegra210_xusb_bin_size; 696 fw_static = _binary_tegra210_xusb_bin_start; 697 #else 698 fw_path = "nvidia/tegra210"; 699 #endif 700 break; 701 default: 702 return EINVAL; 703 } 704 705 if (fw_path != NULL) { 706 error = firmware_open(fw_path, "xusb.bin", &fw); 707 if (error != 0) { 708 aprint_error_dev(sc->sc_dev, 709 "couldn't load firmware from %s/xusb.bin: %d\n", 710 fw_path, error); 711 return error; 712 } 713 firmware_size = firmware_get_size(fw); 714 } 715 716 error = fw_dma_alloc(psc, firmware_size, PAGE_SIZE, 717 &psc->sc_fw_dma); 718 if (error != 0) 719 return error; 720 firmware_image = psc->sc_fw_dma.addr; 721 722 if (fw_path != NULL) { 723 error = firmware_read(fw, 0, firmware_image, firmware_size); 724 if (error != 0) { 725 fw_dma_free(psc, &psc->sc_fw_dma); 726 firmware_close(fw); 727 return error; 728 } 729 firmware_close(fw); 730 } else { 731 memcpy(firmware_image, fw_static, firmware_size); 732 } 733 734 return tegra_xusb_load_fw(psc, firmware_image, firmware_size); 735 } 736 737 static int 738 tegra_xusb_load_fw(struct tegra_xusb_softc * const psc, void *firmware_image, 739 size_t firmware_size) 740 { 741 struct xhci_softc * const sc = &psc->sc_xhci; 742 const uint8_t *header; 743 744 header = firmware_image; 745 746 const uint32_t fwimg_len = le32dec(&header[FWHEADER_FWIMG_LEN]); 747 const uint32_t boot_codetag = le32dec(&header[FWHEADER_BOOT_CODETAG]); 748 const uint32_t boot_codesize = le32dec(&header[FWHEADER_BOOT_CODESIZE]); 749 750 if (fwimg_len != firmware_size) 751 aprint_error_dev(sc->sc_dev, "fwimg_len mismatch %u != %zu\n", 752 fwimg_len, firmware_size); 753 754 bus_dmamap_sync(sc->sc_bus.ub_dmatag, psc->sc_fw_dma.map, 0, 755 firmware_size, BUS_DMASYNC_PREWRITE); 756 757 DPRINTF(sc->sc_dev, "XUSB_FALC_CPUCTL 0x%x\n", 758 csb_read_4(psc, XUSB_CSB_FALCON_CPUCTL_REG)); 759 DPRINTF(sc->sc_dev, "XUSB_CSB_MP_ILOAD_BASE_LO 0x%x\n", 760 csb_read_4(psc, XUSB_CSB_MEMPOOL_ILOAD_BASE_LO_REG)); 761 762 DPRINTF(sc->sc_dev, "XUSB_CSB_MP_ILOAD_ATTR 0x%x\n", 763 csb_read_4(psc, XUSB_CSB_MEMPOOL_ILOAD_ATTR_REG)); 764 csb_write_4(psc, XUSB_CSB_MEMPOOL_ILOAD_ATTR_REG, 765 fwimg_len); 766 DPRINTF(sc->sc_dev, "XUSB_CSB_MP_ILOAD_ATTR 0x%x\n", 767 csb_read_4(psc, XUSB_CSB_MEMPOOL_ILOAD_ATTR_REG)); 768 769 const uint64_t fwbase = psc->sc_fw_dma.map->dm_segs[0].ds_addr + 770 FWHEADER__LEN; 771 772 csb_write_4(psc, XUSB_CSB_MEMPOOL_ILOAD_BASE_HI_REG, fwbase >> 32); 773 csb_write_4(psc, XUSB_CSB_MEMPOOL_ILOAD_BASE_LO_REG, fwbase); 774 DPRINTF(sc->sc_dev, "XUSB_CSB_MP_ILOAD_BASE_LO 0x%x\n", 775 csb_read_4(psc, XUSB_CSB_MEMPOOL_ILOAD_BASE_LO_REG)); 776 DPRINTF(sc->sc_dev, "XUSB_CSB_MP_ILOAD_BASE_HI 0x%x\n", 777 csb_read_4(psc, XUSB_CSB_MEMPOOL_ILOAD_BASE_HI_REG)); 778 779 DPRINTF(sc->sc_dev, "XUSB_CSB_MP_APMAP 0x%x\n", 780 csb_read_4(psc, XUSB_CSB_MEMPOOL_APMAP_REG)); 781 csb_write_4(psc, XUSB_CSB_MEMPOOL_APMAP_REG, 782 XUSB_CSB_MEMPOOL_APMAP_BOOTPATH); 783 DPRINTF(sc->sc_dev, "XUSB_CSB_MP_APMAP 0x%x\n", 784 csb_read_4(psc, XUSB_CSB_MEMPOOL_APMAP_REG)); 785 786 DPRINTF(sc->sc_dev, "XUSB_CSB_MP_L2IMEMOP_TRIG 0x%x\n", 787 csb_read_4(psc, XUSB_CSB_MEMPOOL_L2IMEMOP_TRIG_REG)); 788 csb_write_4(psc, XUSB_CSB_MEMPOOL_L2IMEMOP_TRIG_REG, 789 __SHIFTIN(ACTION_L2IMEM_INVALIDATE_ALL, 790 XUSB_CSB_MEMPOOL_L2IMEMOP_TRIG_ACTION)); 791 DPRINTF(sc->sc_dev, "XUSB_CSB_MP_L2IMEMOP_TRIG 0x%x\n", 792 csb_read_4(psc, XUSB_CSB_MEMPOOL_L2IMEMOP_TRIG_REG)); 793 794 const u_int code_tag_blocks = 795 howmany(boot_codetag, IMEM_BLOCK_SIZE); 796 const u_int code_size_blocks = 797 howmany(boot_codesize, IMEM_BLOCK_SIZE); 798 const u_int code_blocks = code_tag_blocks + code_size_blocks; 799 800 DPRINTF(sc->sc_dev, "XUSB_CSB_MP_L2IMEMOP_SIZE 0x%x\n", 801 csb_read_4(psc, XUSB_CSB_MEMPOOL_L2IMEMOP_SIZE_REG)); 802 csb_write_4(psc, XUSB_CSB_MEMPOOL_L2IMEMOP_SIZE_REG, 803 __SHIFTIN(code_tag_blocks, 804 XUSB_CSB_MEMPOOL_L2IMEMOP_SIZE_SRC_OFFSET) | 805 __SHIFTIN(code_size_blocks, 806 XUSB_CSB_MEMPOOL_L2IMEMOP_SIZE_SRC_COUNT)); 807 DPRINTF(sc->sc_dev, "XUSB_CSB_MP_L2IMEMOP_SIZE 0x%x\n", 808 csb_read_4(psc, XUSB_CSB_MEMPOOL_L2IMEMOP_SIZE_REG)); 809 810 DPRINTF(sc->sc_dev, "XUSB_CSB_MP_L2IMEMOP_TRIG 0x%x\n", 811 csb_read_4(psc, XUSB_CSB_MEMPOOL_L2IMEMOP_TRIG_REG)); 812 csb_write_4(psc, XUSB_CSB_MEMPOOL_L2IMEMOP_TRIG_REG, 813 __SHIFTIN(ACTION_L2IMEM_LOAD_LOCKED_RESULT, 814 XUSB_CSB_MEMPOOL_L2IMEMOP_TRIG_ACTION)); 815 DPRINTF(sc->sc_dev, "XUSB_CSB_MP_L2IMEMOP_TRIG 0x%x\n", 816 csb_read_4(psc, XUSB_CSB_MEMPOOL_L2IMEMOP_TRIG_REG)); 817 818 DPRINTF(sc->sc_dev, "XUSB_FALC_IMFILLCTL 0x%x\n", 819 csb_read_4(psc, XUSB_CSB_FALCON_IMFILLCTL_REG)); 820 csb_write_4(psc, XUSB_CSB_FALCON_IMFILLCTL_REG, code_size_blocks); 821 DPRINTF(sc->sc_dev, "XUSB_FALC_IMFILLCTL 0x%x\n", 822 csb_read_4(psc, XUSB_CSB_FALCON_IMFILLCTL_REG)); 823 824 DPRINTF(sc->sc_dev, "XUSB_FALC_IMFILLRNG1 0x%x\n", 825 csb_read_4(psc, XUSB_CSB_FALCON_IMFILLRNG1_REG)); 826 csb_write_4(psc, XUSB_CSB_FALCON_IMFILLRNG1_REG, 827 __SHIFTIN(code_tag_blocks, XUSB_CSB_FALCON_IMFILLRNG1_TAG_LO) | 828 __SHIFTIN(code_blocks, XUSB_CSB_FALCON_IMFILLRNG1_TAG_HI)); 829 DPRINTF(sc->sc_dev, "XUSB_FALC_IMFILLRNG1 0x%x\n", 830 csb_read_4(psc, XUSB_CSB_FALCON_IMFILLRNG1_REG)); 831 832 DPRINTF(sc->sc_dev, "XUSB_FALC_DMACTL 0x%x\n", 833 csb_read_4(psc, XUSB_CSB_FALCON_DMACTL_REG)); 834 csb_write_4(psc, XUSB_CSB_FALCON_DMACTL_REG, 0); 835 DPRINTF(sc->sc_dev, "XUSB_FALC_DMACTL 0x%x\n", 836 csb_read_4(psc, XUSB_CSB_FALCON_DMACTL_REG)); 837 838 DPRINTF(sc->sc_dev, "XUSB_FALC_BOOTVEC 0x%x\n", 839 csb_read_4(psc, XUSB_CSB_FALCON_BOOTVEC_REG)); 840 csb_write_4(psc, XUSB_CSB_FALCON_BOOTVEC_REG, 841 boot_codetag); 842 DPRINTF(sc->sc_dev, "XUSB_FALC_BOOTVEC 0x%x\n", 843 csb_read_4(psc, XUSB_CSB_FALCON_BOOTVEC_REG)); 844 845 DPRINTF(sc->sc_dev, "XUSB_FALC_CPUCTL 0x%x\n", 846 csb_read_4(psc, XUSB_CSB_FALCON_CPUCTL_REG)); 847 csb_write_4(psc, XUSB_CSB_FALCON_CPUCTL_REG, 848 XUSB_CSB_FALCON_CPUCTL_STARTCPU); 849 DPRINTF(sc->sc_dev, "XUSB_FALC_CPUCTL 0x%x\n", 850 csb_read_4(psc, XUSB_CSB_FALCON_CPUCTL_REG)); 851 852 return 0; 853 } 854 855 static uint32_t 856 csb_read_4(struct tegra_xusb_softc * const psc, bus_size_t csb_offset) 857 { 858 const uint32_t range = __SHIFTOUT(csb_offset, XUSB_CSB_RANGE); 859 const bus_size_t offset = __SHIFTOUT(csb_offset, XUSB_CSB_OFFSET); 860 const bus_space_tag_t bst = psc->sc_xhci.sc_iot; 861 const bus_space_handle_t fpcih = psc->sc_bsh_fpci; 862 863 bus_space_write_4(bst, fpcih, T_XUSB_CFG_ARU_C11_CSBRANGE_REG, range); 864 return bus_space_read_4(bst, fpcih, T_XUSB_CFG_CSB_BASE_ADDR + offset); 865 } 866 867 static void 868 csb_write_4(struct tegra_xusb_softc * const psc, bus_size_t csb_offset, 869 uint32_t value) 870 { 871 const uint32_t range = __SHIFTOUT(csb_offset, XUSB_CSB_RANGE); 872 const bus_size_t offset = __SHIFTOUT(csb_offset, XUSB_CSB_OFFSET); 873 const bus_space_tag_t bst = psc->sc_xhci.sc_iot; 874 const bus_space_handle_t fpcih = psc->sc_bsh_fpci; 875 876 bus_space_write_4(bst, fpcih, T_XUSB_CFG_ARU_C11_CSBRANGE_REG, range); 877 bus_space_write_4(bst, fpcih, T_XUSB_CFG_CSB_BASE_ADDR + offset, value); 878 } 879 880 static int 881 xusb_mailbox_send(struct tegra_xusb_softc * const psc, uint32_t msg) 882 { 883 struct xhci_softc * const sc = &psc->sc_xhci; 884 const bus_space_tag_t bst = psc->sc_xhci.sc_iot; 885 const bus_space_handle_t fpcih = psc->sc_bsh_fpci; 886 uint32_t val; 887 bool wait = false; 888 889 const uint8_t type = __SHIFTOUT(msg, MAILBOX_DATA_TYPE); 890 891 if (!(type == 128 || type == 129)) { 892 val = bus_space_read_4(bst, fpcih, 893 T_XUSB_CFG_ARU_MAILBOX_OWNER_REG); 894 DPRINTF(sc->sc_dev, "XUSB_CFG_ARU_MBOX_OWNER 0x%x\n", 895 val); 896 if (val != MAILBOX_OWNER_NONE) { 897 return EBUSY; 898 } 899 900 bus_space_write_4(bst, fpcih, T_XUSB_CFG_ARU_MAILBOX_OWNER_REG, 901 MAILBOX_OWNER_SW); 902 903 val = bus_space_read_4(bst, fpcih, 904 T_XUSB_CFG_ARU_MAILBOX_OWNER_REG); 905 DPRINTF(sc->sc_dev, "XUSB_CFG_ARU_MBOX_OWNER 0x%x\n", 906 val); 907 if (val != MAILBOX_OWNER_SW) { 908 return EBUSY; 909 } 910 911 wait = true; 912 } 913 914 bus_space_write_4(bst, fpcih, T_XUSB_CFG_ARU_MAILBOX_DATA_IN_REG, msg); 915 916 tegra_reg_set_clear(bst, fpcih, T_XUSB_CFG_ARU_MAILBOX_CMD_REG, 917 T_XUSB_CFG_ARU_MAILBOX_CMD_INT_EN | 918 T_XUSB_CFG_ARU_MAILBOX_CMD_DEST_FALCON, 0); 919 920 if (wait) { 921 922 for (u_int i = 0; i < 2500; i++) { 923 val = bus_space_read_4(bst, fpcih, 924 T_XUSB_CFG_ARU_MAILBOX_OWNER_REG); 925 DPRINTF(sc->sc_dev, 926 "XUSB_CFG_ARU_MBOX_OWNER 0x%x\n", val); 927 if (val == MAILBOX_OWNER_NONE) { 928 break; 929 } 930 DELAY(10); 931 } 932 933 val = bus_space_read_4(bst, fpcih, 934 T_XUSB_CFG_ARU_MAILBOX_OWNER_REG); 935 DPRINTF(sc->sc_dev, 936 "XUSB_CFG_ARU_MBOX_OWNER 0x%x\n", val); 937 if (val != MAILBOX_OWNER_NONE) { 938 aprint_error_dev(sc->sc_dev, 939 "timeout, XUSB_CFG_ARU_MBOX_OWNER 0x%x\n", val); 940 } 941 } 942 943 return 0; 944 } 945
Indexes created Fri Sep 26 20:09:58 GMT 2025