tegra_xusb.c revision 1.19
1 /* $NetBSD: tegra_xusb.c,v 1.19 2019/10/13 06:11:31 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 2016 Jonathan A. Kollasch 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR 20 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 21 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 22 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 23 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 25 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 26 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include "locators.h" 30 #include "opt_tegra.h" 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: tegra_xusb.c,v 1.19 2019/10/13 06:11:31 skrll Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/bus.h> 37 #include <sys/device.h> 38 #include <sys/intr.h> 39 #include <sys/systm.h> 40 #include <sys/kernel.h> 41 42 #include <arm/nvidia/tegra_reg.h> 43 #include <arm/nvidia/tegra_var.h> 44 #include <arm/nvidia/tegra_xusbpad.h> 45 #include <arm/nvidia/tegra_xusbreg.h> 46 #include <arm/nvidia/tegra_pmcreg.h> 47 48 #include <dev/pci/pcireg.h> 49 50 #include <dev/fdt/fdtvar.h> 51 52 #include <dev/firmload.h> 53 54 #include <dev/usb/usb.h> 55 #include <dev/usb/usbdi.h> 56 #include <dev/usb/usbdivar.h> 57 #include <dev/usb/usb_mem.h> 58 59 #include <dev/usb/xhcireg.h> 60 #include <dev/usb/xhcivar.h> 61 62 #ifdef TEGRA_XUSB_DEBUG 63 int tegra_xusb_debug = 1; 64 #else 65 int tegra_xusb_debug = 0; 66 #endif 67 68 #define DPRINTF(...) if (tegra_xusb_debug) device_printf(__VA_ARGS__) 69 70 static int tegra_xusb_match(device_t, cfdata_t, void *); 71 static void tegra_xusb_attach(device_t, device_t, void *); 72 static void tegra_xusb_mountroot(device_t); 73 74 static int tegra_xusb_intr_mbox(void *); 75 76 #ifdef TEGRA124_XUSB_BIN_STATIC 77 extern const char _binary_tegra124_xusb_bin_size[]; 78 extern const char _binary_tegra124_xusb_bin_start[]; 79 #endif 80 81 #ifdef TEGRA210_XUSB_BIN_STATIC 82 extern const char _binary_tegra210_xusb_bin_size[]; 83 extern const char _binary_tegra210_xusb_bin_start[]; 84 #endif 85 86 enum xusb_type { 87 XUSB_T124 = 1, 88 XUSB_T210 89 }; 90 91 struct tegra_xhci_data { 92 enum xusb_type txd_type; 93 const char * const * txd_supplies; 94 size_t txd_nsupplies; 95 bool txd_scale_ss_clock; 96 }; 97 98 const char *tegra124_xhci_supplies[] = { 99 "dvddio-pex-supply", 100 "hvddio-pex-supply", 101 "avdd-usb-supply", 102 "avdd-pll-utmip-supply", 103 "avdd-pll-uerefe-supply", 104 "dvdd-usb-ss-pll-supply", 105 "hvdd-usb-ss-pll-e-supply" 106 }; 107 108 struct tegra_xhci_data tegra124_xhci_data = { 109 .txd_type = XUSB_T124, 110 .txd_supplies = tegra124_xhci_supplies, 111 .txd_nsupplies = __arraycount(tegra124_xhci_supplies), 112 .txd_scale_ss_clock = true, 113 }; 114 115 const char *tegra210_xhci_supplies[] = { 116 "dvddio-pex", 117 "hvddio-pex", 118 "avdd-usb", 119 "avdd-pll-utmip", 120 "avdd-pll-uerefe", 121 "dvdd-pex-pll", 122 "hvdd-pex-pll-e", 123 }; 124 125 struct tegra_xhci_data tegra210_xhci_data = { 126 .txd_type = XUSB_T210, 127 .txd_supplies = tegra210_xhci_supplies, 128 .txd_nsupplies = __arraycount(tegra210_xhci_supplies), 129 .txd_scale_ss_clock = false, 130 }; 131 132 static const struct of_compat_data compat_data[] = { 133 { "nvidia,tegra124-xusb", (uintptr_t)&tegra124_xhci_data }, 134 { "nvidia,tegra210-xusb", (uintptr_t)&tegra210_xhci_data }, 135 { NULL } 136 }; 137 138 struct fw_dma { 139 bus_dmamap_t map; 140 void * addr; 141 bus_dma_segment_t segs[1]; 142 int nsegs; 143 size_t size; 144 }; 145 146 struct tegra_xusb_softc { 147 struct xhci_softc sc_xhci; 148 int sc_phandle; 149 bus_space_handle_t sc_bsh_xhci; 150 bus_space_handle_t sc_bsh_fpci; 151 bus_space_handle_t sc_bsh_ipfs; 152 void *sc_ih; 153 void *sc_ih_mbox; 154 struct fw_dma sc_fw_dma; 155 struct clk *sc_clk_ss_src; 156 157 struct tegra_xhci_data *sc_txd; 158 }; 159 160 static uint32_t csb_read_4(struct tegra_xusb_softc * const, bus_size_t); 161 static void csb_write_4(struct tegra_xusb_softc * const, bus_size_t, 162 uint32_t); 163 164 static void tegra_xusb_init(struct tegra_xusb_softc * const); 165 static int tegra_xusb_open_fw(struct tegra_xusb_softc * const); 166 static int tegra_xusb_load_fw(struct tegra_xusb_softc * const, void *, 167 size_t); 168 static void tegra_xusb_init_regulators(struct tegra_xusb_softc * const); 169 170 static int xusb_mailbox_send(struct tegra_xusb_softc * const, uint32_t); 171 172 CFATTACH_DECL_NEW(tegra_xusb, sizeof(struct tegra_xusb_softc), 173 tegra_xusb_match, tegra_xusb_attach, NULL, NULL); 174 175 static int 176 tegra_xusb_match(device_t parent, cfdata_t cf, void *aux) 177 { 178 struct fdt_attach_args * const faa = aux; 179 180 return of_match_compat_data(faa->faa_phandle, compat_data); 181 } 182 183 #define tegra_xusb_attach_check(sc, cond, fmt, ...) \ 184 do { \ 185 if (cond) { \ 186 aprint_error_dev(sc->sc_dev, fmt, ## __VA_ARGS__); \ 187 return; \ 188 } \ 189 } while (0) 190 191 static void 192 tegra_xusb_attach(device_t parent, device_t self, void *aux) 193 { 194 struct tegra_xusb_softc * const psc = device_private(self); 195 struct xhci_softc * const sc = &psc->sc_xhci; 196 struct fdt_attach_args * const faa = aux; 197 bool wait_for_root = true; 198 char intrstr[128]; 199 bus_addr_t addr; 200 bus_size_t size; 201 struct fdtbus_reset *rst; 202 struct fdtbus_phy *phy; 203 struct clk *clk; 204 uint32_t rate; 205 int error, n; 206 207 aprint_naive("\n"); 208 aprint_normal(": XUSB\n"); 209 210 sc->sc_dev = self; 211 sc->sc_iot = faa->faa_bst; 212 sc->sc_bus.ub_hcpriv = sc; 213 sc->sc_bus.ub_dmatag = faa->faa_dmat; 214 sc->sc_quirks = XHCI_DEFERRED_START; 215 psc->sc_phandle = faa->faa_phandle; 216 217 uintptr_t data = of_search_compatible(faa->faa_phandle, compat_data)->data; 218 psc->sc_txd = (struct tegra_xhci_data *)data; 219 220 if (fdtbus_get_reg_byname(faa->faa_phandle, "hcd", &addr, &size) != 0) { 221 aprint_error(": couldn't get registers\n"); 222 return; 223 } 224 error = bus_space_map(sc->sc_iot, addr, size, 0, &sc->sc_ioh); 225 if (error) { 226 aprint_error(": couldn't map %#" PRIxBUSADDR ": %d", addr, error); 227 return; 228 } 229 DPRINTF(sc->sc_dev, "mapped %#" PRIxBUSADDR "\n", addr); 230 231 if (fdtbus_get_reg_byname(faa->faa_phandle, "fpci", &addr, &size) != 0) { 232 aprint_error(": couldn't get registers\n"); 233 return; 234 } 235 error = bus_space_map(sc->sc_iot, addr, size, 0, &psc->sc_bsh_fpci); 236 if (error) { 237 aprint_error(": couldn't map %#" PRIxBUSADDR ": %d", addr, error); 238 return; 239 } 240 DPRINTF(sc->sc_dev, "mapped %#" PRIxBUSADDR "\n", addr); 241 242 if (fdtbus_get_reg_byname(faa->faa_phandle, "ipfs", &addr, &size) != 0) { 243 aprint_error(": couldn't get registers\n"); 244 return; 245 } 246 error = bus_space_map(sc->sc_iot, addr, size, 0, &psc->sc_bsh_ipfs); 247 if (error) { 248 aprint_error(": couldn't map %#" PRIxBUSADDR ": %d", addr, error); 249 return; 250 } 251 DPRINTF(sc->sc_dev, "mapped %#" PRIxBUSADDR "\n", addr); 252 253 if (!fdtbus_intr_str(faa->faa_phandle, 0, intrstr, sizeof(intrstr))) { 254 aprint_error_dev(self, "failed to decode interrupt\n"); 255 return; 256 } 257 258 psc->sc_ih = fdtbus_intr_establish(faa->faa_phandle, 0, IPL_USB, 259 FDT_INTR_MPSAFE, xhci_intr, sc); 260 if (psc->sc_ih == NULL) { 261 aprint_error_dev(self, "failed to establish interrupt on %s\n", 262 intrstr); 263 return; 264 } 265 aprint_normal_dev(self, "interrupting on %s\n", intrstr); 266 267 if (!fdtbus_intr_str(faa->faa_phandle, 1, intrstr, sizeof(intrstr))) { 268 aprint_error_dev(self, "failed to decode interrupt\n"); 269 return; 270 } 271 272 psc->sc_ih_mbox = fdtbus_intr_establish(faa->faa_phandle, 1, IPL_VM, 273 FDT_INTR_MPSAFE, tegra_xusb_intr_mbox, psc); 274 if (psc->sc_ih_mbox == NULL) { 275 aprint_error_dev(self, "failed to establish interrupt on %s\n", 276 intrstr); 277 return; 278 } 279 aprint_normal_dev(self, "interrupting on %s\n", intrstr); 280 281 /* Enable PHYs */ 282 for (n = 0; (phy = fdtbus_phy_get_index(faa->faa_phandle, n)) != NULL; n++) 283 if (fdtbus_phy_enable(phy, true) != 0) 284 aprint_error_dev(self, "failed to enable PHY #%d\n", n); 285 286 /* Enable XUSB power rails */ 287 288 tegra_pmc_power(PMC_PARTID_XUSBC, true); /* Host/USB2.0 */ 289 tegra_pmc_remove_clamping(PMC_PARTID_XUSBC); 290 tegra_pmc_power(PMC_PARTID_XUSBA, true); /* SuperSpeed */ 291 tegra_pmc_remove_clamping(PMC_PARTID_XUSBA); 292 293 /* Enable XUSB clocks */ 294 295 clk = fdtbus_clock_get(faa->faa_phandle, "pll_e"); 296 rate = clk_get_rate(clk); 297 error = clk_enable(clk); /* XXX set frequency */ 298 DPRINTF(sc->sc_dev, "rate %u error %d\n", rate, error); 299 tegra_xusb_attach_check(sc, error, "failed to enable pll_e clock"); 300 301 clk = fdtbus_clock_get(faa->faa_phandle, "xusb_host_src"); 302 rate = clk_get_rate(clk); 303 DPRINTF(sc->sc_dev, "rate %u error %d\n", rate, error); 304 error = clk_set_rate(clk, 102000000); 305 tegra_xusb_attach_check(sc, error, "failed to set xusb_host_src clock rate"); 306 307 rate = clk_get_rate(clk); 308 error = clk_enable(clk); /* XXX set frequency */ 309 DPRINTF(sc->sc_dev, "rate %u error %d\n", rate, error); 310 tegra_xusb_attach_check(sc, error, "failed to enable xusb_host_src clock"); 311 312 clk = fdtbus_clock_get(faa->faa_phandle, "xusb_falcon_src"); 313 rate = clk_get_rate(clk); 314 DPRINTF(sc->sc_dev, "rate %u error %d\n", rate, error); 315 error = clk_set_rate(clk, 204000000); 316 tegra_xusb_attach_check(sc, error, "failed to set xusb_falcon_src clock rate"); 317 318 rate = clk_get_rate(clk); 319 error = clk_enable(clk); 320 DPRINTF(sc->sc_dev, "rate %u error %d\n", rate, error); 321 tegra_xusb_attach_check(sc, error, "failed to enable xusb_falcon_src clock"); 322 323 clk = fdtbus_clock_get(faa->faa_phandle, "xusb_host"); 324 rate = clk_get_rate(clk); 325 error = clk_enable(clk); /* XXX set frequency */ 326 DPRINTF(sc->sc_dev, "rate %u error %d\n", rate, error); 327 328 clk = fdtbus_clock_get(faa->faa_phandle, "xusb_ss"); 329 rate = clk_get_rate(clk); 330 error = clk_enable(clk); /* XXX set frequency */ 331 DPRINTF(sc->sc_dev, "xusb_ss rate %u error %d\n", rate, error); 332 tegra_xusb_attach_check(sc, error, "failed to enable xusb_ss clock"); 333 334 psc->sc_clk_ss_src = fdtbus_clock_get(faa->faa_phandle, "xusb_ss_src"); 335 tegra_xusb_attach_check(sc, psc->sc_clk_ss_src == NULL, 336 "failed to get xusb_ss_src clock"); 337 338 if (psc->sc_txd->txd_scale_ss_clock) { 339 rate = clk_get_rate(psc->sc_clk_ss_src); 340 DPRINTF(sc->sc_dev, "xusb_ss_src rate %u\n", rate); 341 error = clk_set_rate(psc->sc_clk_ss_src, 2000000); 342 rate = clk_get_rate(psc->sc_clk_ss_src); 343 DPRINTF(sc->sc_dev, "xusb_ss_src rate %u error %d\n", rate, error); 344 tegra_xusb_attach_check(sc, error, "failed to get xusb_ss_src clock rate"); 345 346 rate = clk_get_rate(psc->sc_clk_ss_src); 347 DPRINTF(sc->sc_dev, "ss_src rate %u\n", rate); 348 tegra_xusb_attach_check(sc, error, "failed to set xusb_ss_src clock rate"); 349 350 error = clk_set_rate(psc->sc_clk_ss_src, 120000000); 351 rate = clk_get_rate(psc->sc_clk_ss_src); 352 DPRINTF(sc->sc_dev, "ss_src rate %u error %d\n", rate, error); 353 tegra_xusb_attach_check(sc, error, "failed to get xusb_ss_src clock rate"); 354 } 355 356 rate = clk_get_rate(psc->sc_clk_ss_src); 357 error = clk_enable(psc->sc_clk_ss_src); 358 DPRINTF(sc->sc_dev, "ss_src rate %u error %d\n", rate, error); 359 tegra_xusb_attach_check(sc, error, "failed to enable xusb_ss_src clock"); 360 361 #if 0 362 clk = fdtbus_clock_get(faa->faa_phandle, "xusb_hs_src"); 363 error = 0; 364 rate = clk_get_rate(clk); 365 DPRINTF(sc->sc_dev, "rate %u error %d\n", rate, error); 366 #endif 367 368 clk = fdtbus_clock_get(faa->faa_phandle, "xusb_fs_src"); 369 rate = clk_get_rate(clk); 370 error = clk_enable(clk); /* XXX set frequency */ 371 DPRINTF(sc->sc_dev, "rate %u error %d\n", rate, error); 372 tegra_xusb_attach_check(sc, error, "failed to enable xusb_fs_src clock"); 373 374 rst = fdtbus_reset_get(faa->faa_phandle, "xusb_host"); 375 fdtbus_reset_deassert(rst); 376 377 rst = fdtbus_reset_get(faa->faa_phandle, "xusb_src"); 378 fdtbus_reset_deassert(rst); 379 380 rst = fdtbus_reset_get(faa->faa_phandle, "xusb_ss"); 381 fdtbus_reset_deassert(rst); 382 383 DELAY(1); 384 385 tegra_xusb_init_regulators(psc); 386 387 tegra_xusb_init(psc); 388 389 #if defined(TEGRA124_XUSB_BIN_STATIC) 390 if (psc->sc_txd->txd_type == XUSB_T124) 391 wait_for_root = false; 392 #endif 393 #if defined(TEGRA210_XUSB_BIN_STATIC) 394 if (psc->sc_txd->txd_type == XUSB_T210) 395 wait_for_root = false; 396 #endif 397 398 if (wait_for_root) 399 config_mountroot(sc->sc_dev, tegra_xusb_mountroot); 400 else 401 tegra_xusb_mountroot(sc->sc_dev); 402 } 403 404 static void 405 tegra_xusb_mountroot(device_t self) 406 { 407 struct tegra_xusb_softc * const psc = device_private(self); 408 struct xhci_softc * const sc = &psc->sc_xhci; 409 const bus_space_tag_t bst = sc->sc_iot; 410 const bus_space_handle_t ipfsh = psc->sc_bsh_ipfs; 411 struct clk *clk; 412 struct fdtbus_reset *rst; 413 uint32_t rate; 414 uint32_t val; 415 int error; 416 417 DPRINTF(sc->sc_dev, "%s()\n", __func__); 418 419 val = bus_space_read_4(bst, ipfsh, 0x0); 420 DPRINTF(sc->sc_dev, "%s ipfs 0x0 = 0x%x\n", __func__, val); 421 422 if (tegra_xusb_open_fw(psc) != 0) 423 return; 424 DPRINTF(sc->sc_dev, "post fw\n"); 425 426 tegra_xusbpad_xhci_enable(); 427 428 clk = fdtbus_clock_get(psc->sc_phandle, "xusb_falcon_src"); 429 rate = clk_get_rate(clk); 430 error = clk_enable(clk); 431 DPRINTF(sc->sc_dev, "rate %u error %d\n", rate, error); 432 433 clk = fdtbus_clock_get(psc->sc_phandle, "xusb_host_src"); 434 rate = clk_get_rate(clk); 435 error = clk_enable(clk); 436 DPRINTF(sc->sc_dev, "rate %u error %d\n", rate, error); 437 438 val = bus_space_read_4(bst, ipfsh, 0x0); 439 DPRINTF(sc->sc_dev, "%s ipfs 0x0 = 0x%x\n", __func__, val); 440 441 rst = fdtbus_reset_get(psc->sc_phandle, "xusb_host"); 442 fdtbus_reset_deassert(rst); 443 444 rst = fdtbus_reset_get(psc->sc_phandle, "xusb_src"); 445 fdtbus_reset_deassert(rst); 446 447 rst = fdtbus_reset_get(psc->sc_phandle, "xusb_ss"); 448 fdtbus_reset_deassert(rst); 449 450 val = csb_read_4(psc, XUSB_CSB_FALCON_CPUCTL_REG); 451 DPRINTF(sc->sc_dev, "XUSB_FALC_CPUCTL 0x%x\n", val); 452 453 val = bus_space_read_4(bst, psc->sc_bsh_fpci, PCI_USBREV) 454 & PCI_USBREV_MASK; 455 switch (val) { 456 case PCI_USBREV_3_0: 457 sc->sc_bus.ub_revision = USBREV_3_0; 458 break; 459 case PCI_USBREV_3_1: 460 sc->sc_bus.ub_revision = USBREV_3_1; 461 break; 462 default: 463 if (val < PCI_USBREV_3_0) { 464 aprint_error_dev(self, "Unknown revision (%02x)\n", val); 465 sc->sc_bus.ub_revision = USBREV_UNKNOWN; 466 } else { 467 /* Default to the latest revision */ 468 aprint_normal_dev(self, 469 "Unknown revision (%02x). Set to 3.1.\n", val); 470 sc->sc_bus.ub_revision = USBREV_3_1; 471 } 472 break; 473 } 474 475 error = xhci_init(sc); 476 if (error) { 477 aprint_error_dev(self, "init failed, error=%d\n", error); 478 return; 479 } 480 481 sc->sc_child = config_found(self, &sc->sc_bus, usbctlprint); 482 483 sc->sc_child2 = config_found(self, &sc->sc_bus2, usbctlprint); 484 485 xhci_start(sc); 486 487 error = xusb_mailbox_send(psc, 0x01000000); 488 if (error) { 489 aprint_error_dev(self, "send failed, error=%d\n", error); 490 } 491 } 492 493 static int 494 tegra_xusb_intr_mbox(void *v) 495 { 496 struct tegra_xusb_softc * const psc = v; 497 struct xhci_softc * const sc = &psc->sc_xhci; 498 const bus_space_tag_t bst = sc->sc_iot; 499 const bus_space_handle_t fpcih = psc->sc_bsh_fpci; 500 uint32_t val; 501 uint32_t irv; 502 uint32_t msg; 503 int error; 504 505 DPRINTF(sc->sc_dev, "%s()\n", __func__); 506 507 irv = bus_space_read_4(bst, fpcih, T_XUSB_CFG_ARU_SMI_INTR_REG); 508 DPRINTF(sc->sc_dev, "XUSB_CFG_ARU_SMI_INTR 0x%x\n", irv); 509 bus_space_write_4(bst, fpcih, T_XUSB_CFG_ARU_SMI_INTR_REG, irv); 510 511 if (irv & T_XUSB_CFG_ARU_SMI_INTR_FW_HANG) 512 aprint_error_dev(sc->sc_dev, "firmware hang\n"); 513 514 msg = bus_space_read_4(bst, fpcih, T_XUSB_CFG_ARU_MAILBOX_DATA_OUT_REG); 515 DPRINTF(sc->sc_dev, "XUSB_CFG_ARU_MBOX_DATA_OUT 0x%x\n", msg); 516 517 val = bus_space_read_4(bst, fpcih, T_XUSB_CFG_ARU_MAILBOX_CMD_REG); 518 DPRINTF(sc->sc_dev, "XUSB_CFG_ARU_MBOX_CMD 0x%x\n", val); 519 val &= ~T_XUSB_CFG_ARU_MAILBOX_CMD_DEST_SMI; 520 bus_space_write_4(bst, fpcih, T_XUSB_CFG_ARU_MAILBOX_CMD_REG, val); 521 522 bool sendresp = true; 523 u_int rate; 524 525 const uint32_t data = __SHIFTOUT(msg, MAILBOX_DATA_DATA); 526 const uint8_t type = __SHIFTOUT(msg, MAILBOX_DATA_TYPE); 527 528 switch (type) { 529 case 2: 530 case 3: 531 DPRINTF(sc->sc_dev, "FALC_CLOCK %u\n", data * 1000); 532 break; 533 case 4: 534 case 5: 535 if (psc->sc_txd->txd_scale_ss_clock) { 536 DPRINTF(sc->sc_dev, "SSPI_CLOCK %u\n", data * 1000); 537 rate = clk_get_rate(psc->sc_clk_ss_src); 538 DPRINTF(sc->sc_dev, "rate of psc->sc_clk_ss_src %u\n", 539 rate); 540 error = clk_set_rate(psc->sc_clk_ss_src, data * 1000); 541 if (error != 0) 542 goto clk_fail; 543 rate = clk_get_rate(psc->sc_clk_ss_src); 544 DPRINTF(sc->sc_dev, 545 "rate of psc->sc_clk_ss_src %u after\n", rate); 546 if (data == (rate / 1000)) { 547 msg = __SHIFTIN(128, MAILBOX_DATA_TYPE) | 548 __SHIFTIN(rate / 1000, MAILBOX_DATA_DATA); 549 } else 550 clk_fail: 551 msg = __SHIFTIN(129, MAILBOX_DATA_TYPE) | 552 __SHIFTIN(rate / 1000, MAILBOX_DATA_DATA); 553 } else { 554 msg = __SHIFTIN(128, MAILBOX_DATA_TYPE) | 555 __SHIFTIN(data, MAILBOX_DATA_DATA); 556 } 557 xusb_mailbox_send(psc, msg); 558 break; 559 case 9: 560 msg = __SHIFTIN(data, MAILBOX_DATA_DATA) | 561 __SHIFTIN(128, MAILBOX_DATA_TYPE); 562 xusb_mailbox_send(psc, msg); 563 break; 564 case 6: 565 case 128: 566 case 129: 567 sendresp = false; 568 break; 569 default: 570 sendresp = false; 571 break; 572 } 573 574 if (sendresp == false) 575 bus_space_write_4(bst, fpcih, T_XUSB_CFG_ARU_MAILBOX_OWNER_REG, 576 MAILBOX_OWNER_NONE); 577 578 return irv; 579 } 580 581 static void 582 tegra_xusb_init_regulators(struct tegra_xusb_softc * const psc) 583 { 584 585 device_t dev = psc->sc_xhci.sc_dev; 586 const int phandle = psc->sc_phandle; 587 struct fdtbus_regulator *reg; 588 int n, error; 589 590 for (n = 0; n < psc->sc_txd->txd_nsupplies; n++) { 591 if (!of_hasprop(phandle, psc->sc_txd->txd_supplies[n])) 592 continue; 593 reg = fdtbus_regulator_acquire(phandle, psc->sc_txd->txd_supplies[n]); 594 if (reg == NULL) { 595 aprint_error_dev(dev, "couldn't acquire supply '%s'\n", 596 psc->sc_txd->txd_supplies[n]); 597 continue; 598 } 599 error = fdtbus_regulator_enable(reg); 600 if (error != 0) 601 aprint_error_dev(dev, "couldn't enable supply '%s': %d\n", 602 psc->sc_txd->txd_supplies[n], error); 603 } 604 } 605 606 static void 607 tegra_xusb_init(struct tegra_xusb_softc * const psc) 608 { 609 struct xhci_softc * const sc = &psc->sc_xhci; 610 const bus_space_tag_t bst = sc->sc_iot; 611 const bus_space_handle_t ipfsh = psc->sc_bsh_ipfs; 612 const bus_space_handle_t fpcih = psc->sc_bsh_fpci; 613 614 DPRINTF(sc->sc_dev, "%s()\n", __func__); 615 616 DPRINTF(sc->sc_dev, "%s ipfs 0x0 = 0x%x\n", __func__, 617 bus_space_read_4(bst, ipfsh, 0x0)); 618 619 DPRINTF(sc->sc_dev, "%s ipfs 0x40 = 0x%x\n", __func__, 620 bus_space_read_4(bst, ipfsh, 0x40)); 621 622 DPRINTF(sc->sc_dev, "%s ipfs 0x80 = 0x%x\n", __func__, 623 bus_space_read_4(bst, ipfsh, 0x80)); 624 /* FPCI_BAR0_START and FPCI_BAR0_ACCESS_TYPE */ 625 bus_space_write_4(bst, ipfsh, 0x80, 0x00100000); 626 DPRINTF(sc->sc_dev, "%s ipfs 0x80 = 0x%x\n", __func__, 627 bus_space_read_4(bst, ipfsh, 0x80)); 628 629 DPRINTF(sc->sc_dev, "%s ipfs 0x180 = 0x%x\n", __func__, 630 bus_space_read_4(bst, ipfsh, 0x180)); 631 /* EN_FPCI */ 632 tegra_reg_set_clear(bst, ipfsh, 0x180, 1, 0); 633 DPRINTF(sc->sc_dev, "%s ipfs 0x180 = 0x%x\n", __func__, 634 bus_space_read_4(bst, ipfsh, 0x180)); 635 636 DPRINTF(sc->sc_dev, "%s fpci PCI_COMMAND_STATUS_REG = 0x%x\n", 637 __func__, bus_space_read_4(bst, fpcih, PCI_COMMAND_STATUS_REG)); 638 tegra_reg_set_clear(bst, fpcih, PCI_COMMAND_STATUS_REG, 639 PCI_COMMAND_MASTER_ENABLE|PCI_COMMAND_MEM_ENABLE, 0x0); 640 DPRINTF(sc->sc_dev, "%s fpci PCI_COMMAND_STATUS_REG = 0x%x\n", 641 __func__, bus_space_read_4(bst, fpcih, PCI_COMMAND_STATUS_REG)); 642 643 DPRINTF(sc->sc_dev, "%s fpci PCI_BAR0 = 0x%x\n", __func__, 644 bus_space_read_4(bst, fpcih, PCI_BAR0)); 645 /* match FPCI BAR0 to above */ 646 bus_space_write_4(bst, fpcih, PCI_BAR0, 0x10000000); 647 DPRINTF(sc->sc_dev, "%s fpci PCI_BAR0 = 0x%x\n", __func__, 648 bus_space_read_4(bst, fpcih, PCI_BAR0)); 649 650 DPRINTF(sc->sc_dev, "%s ipfs 0x188 = 0x%x\n", __func__, 651 bus_space_read_4(bst, ipfsh, 0x188)); 652 tegra_reg_set_clear(bst, ipfsh, 0x188, __BIT(16), 0); 653 DPRINTF(sc->sc_dev, "%s ipfs 0x188 = 0x%x\n", __func__, 654 bus_space_read_4(bst, ipfsh, 0x188)); 655 656 DPRINTF(sc->sc_dev, "%s fpci 0x1bc = 0x%x\n", __func__, 657 bus_space_read_4(bst, fpcih, 0x1bc)); 658 bus_space_write_4(bst, fpcih, 0x1bc, 0x80); 659 DPRINTF(sc->sc_dev, "%s fpci 0x1bc = 0x%x\n", __func__, 660 bus_space_read_4(bst, fpcih, 0x1bc)); 661 } 662 663 static int 664 fw_dma_alloc(struct tegra_xusb_softc * const psc, size_t size, size_t align, 665 struct fw_dma * const p) 666 { 667 struct xhci_softc * const sc = &psc->sc_xhci; 668 const bus_dma_tag_t dmat = sc->sc_bus.ub_dmatag; 669 int err; 670 671 p->size = size; 672 err = bus_dmamem_alloc(dmat, p->size, align, 0, p->segs, 673 sizeof(p->segs) / sizeof(p->segs[0]), &p->nsegs, BUS_DMA_NOWAIT); 674 if (err) 675 return err; 676 err = bus_dmamem_map(dmat, p->segs, p->nsegs, p->size, &p->addr, 677 BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 678 if (err) 679 goto free; 680 err = bus_dmamap_create(dmat, p->size, 1, p->size, 0, BUS_DMA_NOWAIT, 681 &p->map); 682 if (err) 683 goto unmap; 684 err = bus_dmamap_load(dmat, p->map, p->addr, p->size, NULL, 685 BUS_DMA_NOWAIT); 686 if (err) 687 goto destroy; 688 689 return 0; 690 691 destroy: 692 bus_dmamap_destroy(dmat, p->map); 693 unmap: 694 bus_dmamem_unmap(dmat, p->addr, p->size); 695 free: 696 bus_dmamem_free(dmat, p->segs, p->nsegs); 697 698 return err; 699 } 700 701 static void 702 fw_dma_free(struct tegra_xusb_softc * const psc, struct fw_dma * const p) 703 { 704 const struct xhci_softc * const sc = &psc->sc_xhci; 705 const bus_dma_tag_t dmat = sc->sc_bus.ub_dmatag; 706 707 bus_dmamap_unload(dmat, p->map); 708 bus_dmamap_destroy(dmat, p->map); 709 bus_dmamem_unmap(dmat, p->addr, p->size); 710 bus_dmamem_free(dmat, p->segs, p->nsegs); 711 } 712 713 #define FWHEADER_BOOT_CODETAG 8 714 #define FWHEADER_BOOT_CODESIZE 12 715 #define FWHEADER_FWIMG_LEN 100 716 #define FWHEADER__LEN 256 717 718 static int 719 tegra_xusb_open_fw(struct tegra_xusb_softc * const psc) 720 { 721 struct xhci_softc * const sc = &psc->sc_xhci; 722 firmware_handle_t fw; 723 size_t firmware_size = 0; 724 void *firmware_image; 725 const char *fw_path = NULL; 726 void *fw_static = NULL; 727 int error; 728 729 switch (psc->sc_txd->txd_type) { 730 case XUSB_T124: 731 #if defined(TEGRA124_XUSB_BIN_STATIC) 732 firmware_size = (uintptr_t)&_binary_tegra124_xusb_bin_size; 733 fw_static = __UNCONST(_binary_tegra124_xusb_bin_start); 734 #else 735 fw_path = "nvidia/tegra124"; 736 #endif 737 break; 738 case XUSB_T210: 739 #if defined(TEGRA210_XUSB_BIN_STATIC) 740 firmware_size = (uintptr_t)&_binary_tegra210_xusb_bin_size; 741 fw_static = __UNCONST(_binary_tegra210_xusb_bin_start); 742 #else 743 fw_path = "nvidia/tegra210"; 744 #endif 745 break; 746 default: 747 return EINVAL; 748 } 749 750 if (fw_path != NULL) { 751 error = firmware_open(fw_path, "xusb.bin", &fw); 752 if (error != 0) { 753 aprint_error_dev(sc->sc_dev, 754 "couldn't load firmware from %s/xusb.bin: %d\n", 755 fw_path, error); 756 return error; 757 } 758 firmware_size = firmware_get_size(fw); 759 } 760 761 error = fw_dma_alloc(psc, firmware_size, PAGE_SIZE, 762 &psc->sc_fw_dma); 763 if (error != 0) 764 return error; 765 firmware_image = psc->sc_fw_dma.addr; 766 767 if (fw_path != NULL) { 768 error = firmware_read(fw, 0, firmware_image, firmware_size); 769 if (error != 0) { 770 fw_dma_free(psc, &psc->sc_fw_dma); 771 firmware_close(fw); 772 return error; 773 } 774 firmware_close(fw); 775 } else { 776 memcpy(firmware_image, fw_static, firmware_size); 777 } 778 779 return tegra_xusb_load_fw(psc, firmware_image, firmware_size); 780 } 781 782 static int 783 tegra_xusb_load_fw(struct tegra_xusb_softc * const psc, void *firmware_image, 784 size_t firmware_size) 785 { 786 struct xhci_softc * const sc = &psc->sc_xhci; 787 const uint8_t *header; 788 789 header = firmware_image; 790 791 const uint32_t fwimg_len = le32dec(&header[FWHEADER_FWIMG_LEN]); 792 const uint32_t boot_codetag = le32dec(&header[FWHEADER_BOOT_CODETAG]); 793 const uint32_t boot_codesize = le32dec(&header[FWHEADER_BOOT_CODESIZE]); 794 795 if (fwimg_len != firmware_size) 796 aprint_error_dev(sc->sc_dev, "fwimg_len mismatch %u != %zu\n", 797 fwimg_len, firmware_size); 798 799 bus_dmamap_sync(sc->sc_bus.ub_dmatag, psc->sc_fw_dma.map, 0, 800 firmware_size, BUS_DMASYNC_PREWRITE); 801 802 DPRINTF(sc->sc_dev, "XUSB_FALC_CPUCTL 0x%x\n", 803 csb_read_4(psc, XUSB_CSB_FALCON_CPUCTL_REG)); 804 DPRINTF(sc->sc_dev, "XUSB_CSB_MP_ILOAD_BASE_LO 0x%x\n", 805 csb_read_4(psc, XUSB_CSB_MEMPOOL_ILOAD_BASE_LO_REG)); 806 807 DPRINTF(sc->sc_dev, "XUSB_CSB_MP_ILOAD_ATTR 0x%x\n", 808 csb_read_4(psc, XUSB_CSB_MEMPOOL_ILOAD_ATTR_REG)); 809 csb_write_4(psc, XUSB_CSB_MEMPOOL_ILOAD_ATTR_REG, 810 fwimg_len); 811 DPRINTF(sc->sc_dev, "XUSB_CSB_MP_ILOAD_ATTR 0x%x\n", 812 csb_read_4(psc, XUSB_CSB_MEMPOOL_ILOAD_ATTR_REG)); 813 814 const uint64_t fwbase = psc->sc_fw_dma.map->dm_segs[0].ds_addr + 815 FWHEADER__LEN; 816 817 csb_write_4(psc, XUSB_CSB_MEMPOOL_ILOAD_BASE_HI_REG, fwbase >> 32); 818 csb_write_4(psc, XUSB_CSB_MEMPOOL_ILOAD_BASE_LO_REG, fwbase); 819 DPRINTF(sc->sc_dev, "XUSB_CSB_MP_ILOAD_BASE_LO 0x%x\n", 820 csb_read_4(psc, XUSB_CSB_MEMPOOL_ILOAD_BASE_LO_REG)); 821 DPRINTF(sc->sc_dev, "XUSB_CSB_MP_ILOAD_BASE_HI 0x%x\n", 822 csb_read_4(psc, XUSB_CSB_MEMPOOL_ILOAD_BASE_HI_REG)); 823 824 DPRINTF(sc->sc_dev, "XUSB_CSB_MP_APMAP 0x%x\n", 825 csb_read_4(psc, XUSB_CSB_MEMPOOL_APMAP_REG)); 826 csb_write_4(psc, XUSB_CSB_MEMPOOL_APMAP_REG, 827 XUSB_CSB_MEMPOOL_APMAP_BOOTPATH); 828 DPRINTF(sc->sc_dev, "XUSB_CSB_MP_APMAP 0x%x\n", 829 csb_read_4(psc, XUSB_CSB_MEMPOOL_APMAP_REG)); 830 831 DPRINTF(sc->sc_dev, "XUSB_CSB_MP_L2IMEMOP_TRIG 0x%x\n", 832 csb_read_4(psc, XUSB_CSB_MEMPOOL_L2IMEMOP_TRIG_REG)); 833 csb_write_4(psc, XUSB_CSB_MEMPOOL_L2IMEMOP_TRIG_REG, 834 __SHIFTIN(ACTION_L2IMEM_INVALIDATE_ALL, 835 XUSB_CSB_MEMPOOL_L2IMEMOP_TRIG_ACTION)); 836 DPRINTF(sc->sc_dev, "XUSB_CSB_MP_L2IMEMOP_TRIG 0x%x\n", 837 csb_read_4(psc, XUSB_CSB_MEMPOOL_L2IMEMOP_TRIG_REG)); 838 839 const u_int code_tag_blocks = 840 howmany(boot_codetag, IMEM_BLOCK_SIZE); 841 const u_int code_size_blocks = 842 howmany(boot_codesize, IMEM_BLOCK_SIZE); 843 const u_int code_blocks = code_tag_blocks + code_size_blocks; 844 845 DPRINTF(sc->sc_dev, "XUSB_CSB_MP_L2IMEMOP_SIZE 0x%x\n", 846 csb_read_4(psc, XUSB_CSB_MEMPOOL_L2IMEMOP_SIZE_REG)); 847 csb_write_4(psc, XUSB_CSB_MEMPOOL_L2IMEMOP_SIZE_REG, 848 __SHIFTIN(code_tag_blocks, 849 XUSB_CSB_MEMPOOL_L2IMEMOP_SIZE_SRC_OFFSET) | 850 __SHIFTIN(code_size_blocks, 851 XUSB_CSB_MEMPOOL_L2IMEMOP_SIZE_SRC_COUNT)); 852 DPRINTF(sc->sc_dev, "XUSB_CSB_MP_L2IMEMOP_SIZE 0x%x\n", 853 csb_read_4(psc, XUSB_CSB_MEMPOOL_L2IMEMOP_SIZE_REG)); 854 855 DPRINTF(sc->sc_dev, "XUSB_CSB_MP_L2IMEMOP_TRIG 0x%x\n", 856 csb_read_4(psc, XUSB_CSB_MEMPOOL_L2IMEMOP_TRIG_REG)); 857 csb_write_4(psc, XUSB_CSB_MEMPOOL_L2IMEMOP_TRIG_REG, 858 __SHIFTIN(ACTION_L2IMEM_LOAD_LOCKED_RESULT, 859 XUSB_CSB_MEMPOOL_L2IMEMOP_TRIG_ACTION)); 860 DPRINTF(sc->sc_dev, "XUSB_CSB_MP_L2IMEMOP_TRIG 0x%x\n", 861 csb_read_4(psc, XUSB_CSB_MEMPOOL_L2IMEMOP_TRIG_REG)); 862 863 DPRINTF(sc->sc_dev, "XUSB_FALC_IMFILLCTL 0x%x\n", 864 csb_read_4(psc, XUSB_CSB_FALCON_IMFILLCTL_REG)); 865 csb_write_4(psc, XUSB_CSB_FALCON_IMFILLCTL_REG, code_size_blocks); 866 DPRINTF(sc->sc_dev, "XUSB_FALC_IMFILLCTL 0x%x\n", 867 csb_read_4(psc, XUSB_CSB_FALCON_IMFILLCTL_REG)); 868 869 DPRINTF(sc->sc_dev, "XUSB_FALC_IMFILLRNG1 0x%x\n", 870 csb_read_4(psc, XUSB_CSB_FALCON_IMFILLRNG1_REG)); 871 csb_write_4(psc, XUSB_CSB_FALCON_IMFILLRNG1_REG, 872 __SHIFTIN(code_tag_blocks, XUSB_CSB_FALCON_IMFILLRNG1_TAG_LO) | 873 __SHIFTIN(code_blocks, XUSB_CSB_FALCON_IMFILLRNG1_TAG_HI)); 874 DPRINTF(sc->sc_dev, "XUSB_FALC_IMFILLRNG1 0x%x\n", 875 csb_read_4(psc, XUSB_CSB_FALCON_IMFILLRNG1_REG)); 876 877 DPRINTF(sc->sc_dev, "XUSB_FALC_DMACTL 0x%x\n", 878 csb_read_4(psc, XUSB_CSB_FALCON_DMACTL_REG)); 879 csb_write_4(psc, XUSB_CSB_FALCON_DMACTL_REG, 0); 880 DPRINTF(sc->sc_dev, "XUSB_FALC_DMACTL 0x%x\n", 881 csb_read_4(psc, XUSB_CSB_FALCON_DMACTL_REG)); 882 883 DPRINTF(sc->sc_dev, "XUSB_FALC_BOOTVEC 0x%x\n", 884 csb_read_4(psc, XUSB_CSB_FALCON_BOOTVEC_REG)); 885 csb_write_4(psc, XUSB_CSB_FALCON_BOOTVEC_REG, 886 boot_codetag); 887 DPRINTF(sc->sc_dev, "XUSB_FALC_BOOTVEC 0x%x\n", 888 csb_read_4(psc, XUSB_CSB_FALCON_BOOTVEC_REG)); 889 890 DPRINTF(sc->sc_dev, "XUSB_FALC_CPUCTL 0x%x\n", 891 csb_read_4(psc, XUSB_CSB_FALCON_CPUCTL_REG)); 892 csb_write_4(psc, XUSB_CSB_FALCON_CPUCTL_REG, 893 XUSB_CSB_FALCON_CPUCTL_STARTCPU); 894 DPRINTF(sc->sc_dev, "XUSB_FALC_CPUCTL 0x%x\n", 895 csb_read_4(psc, XUSB_CSB_FALCON_CPUCTL_REG)); 896 897 return 0; 898 } 899 900 static uint32_t 901 csb_read_4(struct tegra_xusb_softc * const psc, bus_size_t csb_offset) 902 { 903 const uint32_t range = __SHIFTOUT(csb_offset, XUSB_CSB_RANGE); 904 const bus_size_t offset = __SHIFTOUT(csb_offset, XUSB_CSB_OFFSET); 905 const bus_space_tag_t bst = psc->sc_xhci.sc_iot; 906 const bus_space_handle_t fpcih = psc->sc_bsh_fpci; 907 908 bus_space_write_4(bst, fpcih, T_XUSB_CFG_ARU_C11_CSBRANGE_REG, range); 909 return bus_space_read_4(bst, fpcih, T_XUSB_CFG_CSB_BASE_ADDR + offset); 910 } 911 912 static void 913 csb_write_4(struct tegra_xusb_softc * const psc, bus_size_t csb_offset, 914 uint32_t value) 915 { 916 const uint32_t range = __SHIFTOUT(csb_offset, XUSB_CSB_RANGE); 917 const bus_size_t offset = __SHIFTOUT(csb_offset, XUSB_CSB_OFFSET); 918 const bus_space_tag_t bst = psc->sc_xhci.sc_iot; 919 const bus_space_handle_t fpcih = psc->sc_bsh_fpci; 920 921 bus_space_write_4(bst, fpcih, T_XUSB_CFG_ARU_C11_CSBRANGE_REG, range); 922 bus_space_write_4(bst, fpcih, T_XUSB_CFG_CSB_BASE_ADDR + offset, value); 923 } 924 925 static int 926 xusb_mailbox_send(struct tegra_xusb_softc * const psc, uint32_t msg) 927 { 928 struct xhci_softc * const sc = &psc->sc_xhci; 929 const bus_space_tag_t bst = psc->sc_xhci.sc_iot; 930 const bus_space_handle_t fpcih = psc->sc_bsh_fpci; 931 uint32_t val; 932 bool wait = false; 933 934 const uint8_t type = __SHIFTOUT(msg, MAILBOX_DATA_TYPE); 935 936 if (!(type == 128 || type == 129)) { 937 val = bus_space_read_4(bst, fpcih, 938 T_XUSB_CFG_ARU_MAILBOX_OWNER_REG); 939 DPRINTF(sc->sc_dev, "XUSB_CFG_ARU_MBOX_OWNER 0x%x\n", 940 val); 941 if (val != MAILBOX_OWNER_NONE) { 942 return EBUSY; 943 } 944 945 bus_space_write_4(bst, fpcih, T_XUSB_CFG_ARU_MAILBOX_OWNER_REG, 946 MAILBOX_OWNER_SW); 947 948 val = bus_space_read_4(bst, fpcih, 949 T_XUSB_CFG_ARU_MAILBOX_OWNER_REG); 950 DPRINTF(sc->sc_dev, "XUSB_CFG_ARU_MBOX_OWNER 0x%x\n", 951 val); 952 if (val != MAILBOX_OWNER_SW) { 953 return EBUSY; 954 } 955 956 wait = true; 957 } 958 959 bus_space_write_4(bst, fpcih, T_XUSB_CFG_ARU_MAILBOX_DATA_IN_REG, msg); 960 961 tegra_reg_set_clear(bst, fpcih, T_XUSB_CFG_ARU_MAILBOX_CMD_REG, 962 T_XUSB_CFG_ARU_MAILBOX_CMD_INT_EN | 963 T_XUSB_CFG_ARU_MAILBOX_CMD_DEST_FALCON, 0); 964 965 if (wait) { 966 967 for (u_int i = 0; i < 2500; i++) { 968 val = bus_space_read_4(bst, fpcih, 969 T_XUSB_CFG_ARU_MAILBOX_OWNER_REG); 970 DPRINTF(sc->sc_dev, 971 "XUSB_CFG_ARU_MBOX_OWNER 0x%x\n", val); 972 if (val == MAILBOX_OWNER_NONE) { 973 break; 974 } 975 DELAY(10); 976 } 977 978 val = bus_space_read_4(bst, fpcih, 979 T_XUSB_CFG_ARU_MAILBOX_OWNER_REG); 980 DPRINTF(sc->sc_dev, 981 "XUSB_CFG_ARU_MBOX_OWNER 0x%x\n", val); 982 if (val != MAILBOX_OWNER_NONE) { 983 aprint_error_dev(sc->sc_dev, 984 "timeout, XUSB_CFG_ARU_MBOX_OWNER 0x%x\n", val); 985 } 986 } 987 988 return 0; 989 } 990
Indexes created Sat Sep 27 14:09:57 GMT 2025