tegra_xusb.c revision 1.20
1 /* $NetBSD: tegra_xusb.c,v 1.20 2020/08/29 19:06:17 jakllsch Exp $ */ 2 3 /* 4 * Copyright (c) 2016 Jonathan A. Kollasch 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR 20 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 21 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 22 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 23 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 25 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 26 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include "locators.h" 30 #include "opt_tegra.h" 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: tegra_xusb.c,v 1.20 2020/08/29 19:06:17 jakllsch Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/bus.h> 37 #include <sys/device.h> 38 #include <sys/intr.h> 39 #include <sys/systm.h> 40 #include <sys/kernel.h> 41 42 #include <arm/nvidia/tegra_reg.h> 43 #include <arm/nvidia/tegra_var.h> 44 #include <arm/nvidia/tegra_xusbpad.h> 45 #include <arm/nvidia/tegra_xusbreg.h> 46 #include <arm/nvidia/tegra_pmcreg.h> 47 48 #include <dev/pci/pcireg.h> 49 50 #include <dev/fdt/fdtvar.h> 51 52 #include <dev/firmload.h> 53 54 #include <dev/usb/usb.h> 55 #include <dev/usb/usbdi.h> 56 #include <dev/usb/usbdivar.h> 57 #include <dev/usb/usb_mem.h> 58 59 #include <dev/usb/xhcireg.h> 60 #include <dev/usb/xhcivar.h> 61 62 #ifdef TEGRA_XUSB_DEBUG 63 int tegra_xusb_debug = 1; 64 #else 65 int tegra_xusb_debug = 0; 66 #endif 67 68 #define DPRINTF(...) if (tegra_xusb_debug) device_printf(__VA_ARGS__) 69 70 static int tegra_xusb_match(device_t, cfdata_t, void *); 71 static void tegra_xusb_attach(device_t, device_t, void *); 72 static void tegra_xusb_mountroot(device_t); 73 74 static int tegra_xusb_intr_mbox(void *); 75 76 #ifdef TEGRA124_XUSB_BIN_STATIC 77 extern const char _binary_tegra124_xusb_bin_start[]; 78 extern const char _binary_tegra124_xusb_bin_end[]; 79 __asm__( 80 ".section \".rodata\"\n" 81 "_binary_tegra124_xusb_bin_start:\n" 82 ".incbin \"../external/nvidia-firmware/tegra/dist/tegra124/xusb.bin\"\n" 83 ".size _binary_tegra124_xusb_bin_start, . - _binary_tegra124_xusb_bin_start\n" 84 "_binary_tegra124_xusb_bin_end:\n" 85 ".previous\n" 86 ); 87 #endif 88 89 #ifdef TEGRA210_XUSB_BIN_STATIC 90 extern const char _binary_tegra210_xusb_bin_start[]; 91 extern const char _binary_tegra210_xusb_bin_end[]; 92 __asm__( 93 ".section \".rodata\"\n" 94 "_binary_tegra210_xusb_bin_start:\n" 95 ".incbin \"../external/nvidia-firmware/tegra/dist/tegra210/xusb.bin\"\n" 96 ".size _binary_tegra210_xusb_bin_start, . - _binary_tegra210_xusb_bin_start\n" 97 "_binary_tegra210_xusb_bin_end:\n" 98 ".previous\n" 99 ); 100 #endif 101 102 enum xusb_type { 103 XUSB_T124 = 1, 104 XUSB_T210 105 }; 106 107 struct tegra_xhci_data { 108 enum xusb_type txd_type; 109 const char * const * txd_supplies; 110 size_t txd_nsupplies; 111 bool txd_scale_ss_clock; 112 }; 113 114 const char *tegra124_xhci_supplies[] = { 115 "dvddio-pex-supply", 116 "hvddio-pex-supply", 117 "avdd-usb-supply", 118 "avdd-pll-utmip-supply", 119 "avdd-pll-uerefe-supply", 120 "dvdd-usb-ss-pll-supply", 121 "hvdd-usb-ss-pll-e-supply" 122 }; 123 124 struct tegra_xhci_data tegra124_xhci_data = { 125 .txd_type = XUSB_T124, 126 .txd_supplies = tegra124_xhci_supplies, 127 .txd_nsupplies = __arraycount(tegra124_xhci_supplies), 128 .txd_scale_ss_clock = true, 129 }; 130 131 const char *tegra210_xhci_supplies[] = { 132 "dvddio-pex", 133 "hvddio-pex", 134 "avdd-usb", 135 "avdd-pll-utmip", 136 "avdd-pll-uerefe", 137 "dvdd-pex-pll", 138 "hvdd-pex-pll-e", 139 }; 140 141 struct tegra_xhci_data tegra210_xhci_data = { 142 .txd_type = XUSB_T210, 143 .txd_supplies = tegra210_xhci_supplies, 144 .txd_nsupplies = __arraycount(tegra210_xhci_supplies), 145 .txd_scale_ss_clock = false, 146 }; 147 148 static const struct of_compat_data compat_data[] = { 149 { "nvidia,tegra124-xusb", (uintptr_t)&tegra124_xhci_data }, 150 { "nvidia,tegra210-xusb", (uintptr_t)&tegra210_xhci_data }, 151 { NULL } 152 }; 153 154 struct fw_dma { 155 bus_dmamap_t map; 156 void * addr; 157 bus_dma_segment_t segs[1]; 158 int nsegs; 159 size_t size; 160 }; 161 162 struct tegra_xusb_softc { 163 struct xhci_softc sc_xhci; 164 int sc_phandle; 165 bus_space_handle_t sc_bsh_xhci; 166 bus_space_handle_t sc_bsh_fpci; 167 bus_space_handle_t sc_bsh_ipfs; 168 void *sc_ih; 169 void *sc_ih_mbox; 170 struct fw_dma sc_fw_dma; 171 struct clk *sc_clk_ss_src; 172 173 struct tegra_xhci_data *sc_txd; 174 }; 175 176 static uint32_t csb_read_4(struct tegra_xusb_softc * const, bus_size_t); 177 static void csb_write_4(struct tegra_xusb_softc * const, bus_size_t, 178 uint32_t); 179 180 static void tegra_xusb_init(struct tegra_xusb_softc * const); 181 static int tegra_xusb_open_fw(struct tegra_xusb_softc * const); 182 static int tegra_xusb_load_fw(struct tegra_xusb_softc * const, void *, 183 size_t); 184 static void tegra_xusb_init_regulators(struct tegra_xusb_softc * const); 185 186 static int xusb_mailbox_send(struct tegra_xusb_softc * const, uint32_t); 187 188 CFATTACH_DECL_NEW(tegra_xusb, sizeof(struct tegra_xusb_softc), 189 tegra_xusb_match, tegra_xusb_attach, NULL, NULL); 190 191 static int 192 tegra_xusb_match(device_t parent, cfdata_t cf, void *aux) 193 { 194 struct fdt_attach_args * const faa = aux; 195 196 return of_match_compat_data(faa->faa_phandle, compat_data); 197 } 198 199 #define tegra_xusb_attach_check(sc, cond, fmt, ...) \ 200 do { \ 201 if (cond) { \ 202 aprint_error_dev(sc->sc_dev, fmt, ## __VA_ARGS__); \ 203 return; \ 204 } \ 205 } while (0) 206 207 static void 208 tegra_xusb_attach(device_t parent, device_t self, void *aux) 209 { 210 struct tegra_xusb_softc * const psc = device_private(self); 211 struct xhci_softc * const sc = &psc->sc_xhci; 212 struct fdt_attach_args * const faa = aux; 213 bool wait_for_root = true; 214 char intrstr[128]; 215 bus_addr_t addr; 216 bus_size_t size; 217 struct fdtbus_reset *rst; 218 struct fdtbus_phy *phy; 219 struct clk *clk; 220 uint32_t rate; 221 int error, n; 222 223 aprint_naive("\n"); 224 aprint_normal(": XUSB\n"); 225 226 sc->sc_dev = self; 227 sc->sc_iot = faa->faa_bst; 228 sc->sc_bus.ub_hcpriv = sc; 229 sc->sc_bus.ub_dmatag = faa->faa_dmat; 230 sc->sc_quirks = XHCI_DEFERRED_START; 231 psc->sc_phandle = faa->faa_phandle; 232 233 uintptr_t data = of_search_compatible(faa->faa_phandle, compat_data)->data; 234 psc->sc_txd = (struct tegra_xhci_data *)data; 235 236 if (fdtbus_get_reg_byname(faa->faa_phandle, "hcd", &addr, &size) != 0) { 237 aprint_error(": couldn't get registers\n"); 238 return; 239 } 240 error = bus_space_map(sc->sc_iot, addr, size, 0, &sc->sc_ioh); 241 if (error) { 242 aprint_error(": couldn't map %#" PRIxBUSADDR ": %d", addr, error); 243 return; 244 } 245 DPRINTF(sc->sc_dev, "mapped %#" PRIxBUSADDR "\n", addr); 246 247 if (fdtbus_get_reg_byname(faa->faa_phandle, "fpci", &addr, &size) != 0) { 248 aprint_error(": couldn't get registers\n"); 249 return; 250 } 251 error = bus_space_map(sc->sc_iot, addr, size, 0, &psc->sc_bsh_fpci); 252 if (error) { 253 aprint_error(": couldn't map %#" PRIxBUSADDR ": %d", addr, error); 254 return; 255 } 256 DPRINTF(sc->sc_dev, "mapped %#" PRIxBUSADDR "\n", addr); 257 258 if (fdtbus_get_reg_byname(faa->faa_phandle, "ipfs", &addr, &size) != 0) { 259 aprint_error(": couldn't get registers\n"); 260 return; 261 } 262 error = bus_space_map(sc->sc_iot, addr, size, 0, &psc->sc_bsh_ipfs); 263 if (error) { 264 aprint_error(": couldn't map %#" PRIxBUSADDR ": %d", addr, error); 265 return; 266 } 267 DPRINTF(sc->sc_dev, "mapped %#" PRIxBUSADDR "\n", addr); 268 269 if (!fdtbus_intr_str(faa->faa_phandle, 0, intrstr, sizeof(intrstr))) { 270 aprint_error_dev(self, "failed to decode interrupt\n"); 271 return; 272 } 273 274 psc->sc_ih = fdtbus_intr_establish(faa->faa_phandle, 0, IPL_USB, 275 FDT_INTR_MPSAFE, xhci_intr, sc); 276 if (psc->sc_ih == NULL) { 277 aprint_error_dev(self, "failed to establish interrupt on %s\n", 278 intrstr); 279 return; 280 } 281 aprint_normal_dev(self, "interrupting on %s\n", intrstr); 282 283 if (!fdtbus_intr_str(faa->faa_phandle, 1, intrstr, sizeof(intrstr))) { 284 aprint_error_dev(self, "failed to decode interrupt\n"); 285 return; 286 } 287 288 psc->sc_ih_mbox = fdtbus_intr_establish(faa->faa_phandle, 1, IPL_VM, 289 FDT_INTR_MPSAFE, tegra_xusb_intr_mbox, psc); 290 if (psc->sc_ih_mbox == NULL) { 291 aprint_error_dev(self, "failed to establish interrupt on %s\n", 292 intrstr); 293 return; 294 } 295 aprint_normal_dev(self, "interrupting on %s\n", intrstr); 296 297 /* Enable PHYs */ 298 for (n = 0; (phy = fdtbus_phy_get_index(faa->faa_phandle, n)) != NULL; n++) 299 if (fdtbus_phy_enable(phy, true) != 0) 300 aprint_error_dev(self, "failed to enable PHY #%d\n", n); 301 302 /* Enable XUSB power rails */ 303 304 tegra_pmc_power(PMC_PARTID_XUSBC, true); /* Host/USB2.0 */ 305 tegra_pmc_remove_clamping(PMC_PARTID_XUSBC); 306 tegra_pmc_power(PMC_PARTID_XUSBA, true); /* SuperSpeed */ 307 tegra_pmc_remove_clamping(PMC_PARTID_XUSBA); 308 309 /* Enable XUSB clocks */ 310 311 clk = fdtbus_clock_get(faa->faa_phandle, "pll_e"); 312 rate = clk_get_rate(clk); 313 error = clk_enable(clk); /* XXX set frequency */ 314 DPRINTF(sc->sc_dev, "rate %u error %d\n", rate, error); 315 tegra_xusb_attach_check(sc, error, "failed to enable pll_e clock"); 316 317 clk = fdtbus_clock_get(faa->faa_phandle, "xusb_host_src"); 318 rate = clk_get_rate(clk); 319 DPRINTF(sc->sc_dev, "rate %u error %d\n", rate, error); 320 error = clk_set_rate(clk, 102000000); 321 tegra_xusb_attach_check(sc, error, "failed to set xusb_host_src clock rate"); 322 323 rate = clk_get_rate(clk); 324 error = clk_enable(clk); /* XXX set frequency */ 325 DPRINTF(sc->sc_dev, "rate %u error %d\n", rate, error); 326 tegra_xusb_attach_check(sc, error, "failed to enable xusb_host_src clock"); 327 328 clk = fdtbus_clock_get(faa->faa_phandle, "xusb_falcon_src"); 329 rate = clk_get_rate(clk); 330 DPRINTF(sc->sc_dev, "rate %u error %d\n", rate, error); 331 error = clk_set_rate(clk, 204000000); 332 tegra_xusb_attach_check(sc, error, "failed to set xusb_falcon_src clock rate"); 333 334 rate = clk_get_rate(clk); 335 error = clk_enable(clk); 336 DPRINTF(sc->sc_dev, "rate %u error %d\n", rate, error); 337 tegra_xusb_attach_check(sc, error, "failed to enable xusb_falcon_src clock"); 338 339 clk = fdtbus_clock_get(faa->faa_phandle, "xusb_host"); 340 rate = clk_get_rate(clk); 341 error = clk_enable(clk); /* XXX set frequency */ 342 DPRINTF(sc->sc_dev, "rate %u error %d\n", rate, error); 343 344 clk = fdtbus_clock_get(faa->faa_phandle, "xusb_ss"); 345 rate = clk_get_rate(clk); 346 error = clk_enable(clk); /* XXX set frequency */ 347 DPRINTF(sc->sc_dev, "xusb_ss rate %u error %d\n", rate, error); 348 tegra_xusb_attach_check(sc, error, "failed to enable xusb_ss clock"); 349 350 psc->sc_clk_ss_src = fdtbus_clock_get(faa->faa_phandle, "xusb_ss_src"); 351 tegra_xusb_attach_check(sc, psc->sc_clk_ss_src == NULL, 352 "failed to get xusb_ss_src clock"); 353 354 if (psc->sc_txd->txd_scale_ss_clock) { 355 rate = clk_get_rate(psc->sc_clk_ss_src); 356 DPRINTF(sc->sc_dev, "xusb_ss_src rate %u\n", rate); 357 error = clk_set_rate(psc->sc_clk_ss_src, 2000000); 358 rate = clk_get_rate(psc->sc_clk_ss_src); 359 DPRINTF(sc->sc_dev, "xusb_ss_src rate %u error %d\n", rate, error); 360 tegra_xusb_attach_check(sc, error, "failed to get xusb_ss_src clock rate"); 361 362 rate = clk_get_rate(psc->sc_clk_ss_src); 363 DPRINTF(sc->sc_dev, "ss_src rate %u\n", rate); 364 tegra_xusb_attach_check(sc, error, "failed to set xusb_ss_src clock rate"); 365 366 error = clk_set_rate(psc->sc_clk_ss_src, 120000000); 367 rate = clk_get_rate(psc->sc_clk_ss_src); 368 DPRINTF(sc->sc_dev, "ss_src rate %u error %d\n", rate, error); 369 tegra_xusb_attach_check(sc, error, "failed to get xusb_ss_src clock rate"); 370 } 371 372 rate = clk_get_rate(psc->sc_clk_ss_src); 373 error = clk_enable(psc->sc_clk_ss_src); 374 DPRINTF(sc->sc_dev, "ss_src rate %u error %d\n", rate, error); 375 tegra_xusb_attach_check(sc, error, "failed to enable xusb_ss_src clock"); 376 377 #if 0 378 clk = fdtbus_clock_get(faa->faa_phandle, "xusb_hs_src"); 379 error = 0; 380 rate = clk_get_rate(clk); 381 DPRINTF(sc->sc_dev, "rate %u error %d\n", rate, error); 382 #endif 383 384 clk = fdtbus_clock_get(faa->faa_phandle, "xusb_fs_src"); 385 rate = clk_get_rate(clk); 386 error = clk_enable(clk); /* XXX set frequency */ 387 DPRINTF(sc->sc_dev, "rate %u error %d\n", rate, error); 388 tegra_xusb_attach_check(sc, error, "failed to enable xusb_fs_src clock"); 389 390 rst = fdtbus_reset_get(faa->faa_phandle, "xusb_host"); 391 fdtbus_reset_deassert(rst); 392 393 rst = fdtbus_reset_get(faa->faa_phandle, "xusb_src"); 394 fdtbus_reset_deassert(rst); 395 396 rst = fdtbus_reset_get(faa->faa_phandle, "xusb_ss"); 397 fdtbus_reset_deassert(rst); 398 399 DELAY(1); 400 401 tegra_xusb_init_regulators(psc); 402 403 tegra_xusb_init(psc); 404 405 #if defined(TEGRA124_XUSB_BIN_STATIC) 406 if (psc->sc_txd->txd_type == XUSB_T124) 407 wait_for_root = false; 408 #endif 409 #if defined(TEGRA210_XUSB_BIN_STATIC) 410 if (psc->sc_txd->txd_type == XUSB_T210) 411 wait_for_root = false; 412 #endif 413 414 if (wait_for_root) 415 config_mountroot(sc->sc_dev, tegra_xusb_mountroot); 416 else 417 tegra_xusb_mountroot(sc->sc_dev); 418 } 419 420 static void 421 tegra_xusb_mountroot(device_t self) 422 { 423 struct tegra_xusb_softc * const psc = device_private(self); 424 struct xhci_softc * const sc = &psc->sc_xhci; 425 const bus_space_tag_t bst = sc->sc_iot; 426 const bus_space_handle_t ipfsh = psc->sc_bsh_ipfs; 427 struct clk *clk; 428 struct fdtbus_reset *rst; 429 uint32_t rate; 430 uint32_t val; 431 int error; 432 433 DPRINTF(sc->sc_dev, "%s()\n", __func__); 434 435 val = bus_space_read_4(bst, ipfsh, 0x0); 436 DPRINTF(sc->sc_dev, "%s ipfs 0x0 = 0x%x\n", __func__, val); 437 438 if (tegra_xusb_open_fw(psc) != 0) 439 return; 440 DPRINTF(sc->sc_dev, "post fw\n"); 441 442 tegra_xusbpad_xhci_enable(); 443 444 clk = fdtbus_clock_get(psc->sc_phandle, "xusb_falcon_src"); 445 rate = clk_get_rate(clk); 446 error = clk_enable(clk); 447 DPRINTF(sc->sc_dev, "rate %u error %d\n", rate, error); 448 449 clk = fdtbus_clock_get(psc->sc_phandle, "xusb_host_src"); 450 rate = clk_get_rate(clk); 451 error = clk_enable(clk); 452 DPRINTF(sc->sc_dev, "rate %u error %d\n", rate, error); 453 454 val = bus_space_read_4(bst, ipfsh, 0x0); 455 DPRINTF(sc->sc_dev, "%s ipfs 0x0 = 0x%x\n", __func__, val); 456 457 rst = fdtbus_reset_get(psc->sc_phandle, "xusb_host"); 458 fdtbus_reset_deassert(rst); 459 460 rst = fdtbus_reset_get(psc->sc_phandle, "xusb_src"); 461 fdtbus_reset_deassert(rst); 462 463 rst = fdtbus_reset_get(psc->sc_phandle, "xusb_ss"); 464 fdtbus_reset_deassert(rst); 465 466 val = csb_read_4(psc, XUSB_CSB_FALCON_CPUCTL_REG); 467 DPRINTF(sc->sc_dev, "XUSB_FALC_CPUCTL 0x%x\n", val); 468 469 val = bus_space_read_4(bst, psc->sc_bsh_fpci, PCI_USBREV) 470 & PCI_USBREV_MASK; 471 switch (val) { 472 case PCI_USBREV_3_0: 473 sc->sc_bus.ub_revision = USBREV_3_0; 474 break; 475 case PCI_USBREV_3_1: 476 sc->sc_bus.ub_revision = USBREV_3_1; 477 break; 478 default: 479 if (val < PCI_USBREV_3_0) { 480 aprint_error_dev(self, "Unknown revision (%02x)\n", val); 481 sc->sc_bus.ub_revision = USBREV_UNKNOWN; 482 } else { 483 /* Default to the latest revision */ 484 aprint_normal_dev(self, 485 "Unknown revision (%02x). Set to 3.1.\n", val); 486 sc->sc_bus.ub_revision = USBREV_3_1; 487 } 488 break; 489 } 490 491 error = xhci_init(sc); 492 if (error) { 493 aprint_error_dev(self, "init failed, error=%d\n", error); 494 return; 495 } 496 497 sc->sc_child = config_found(self, &sc->sc_bus, usbctlprint); 498 499 sc->sc_child2 = config_found(self, &sc->sc_bus2, usbctlprint); 500 501 xhci_start(sc); 502 503 error = xusb_mailbox_send(psc, 0x01000000); 504 if (error) { 505 aprint_error_dev(self, "send failed, error=%d\n", error); 506 } 507 } 508 509 static int 510 tegra_xusb_intr_mbox(void *v) 511 { 512 struct tegra_xusb_softc * const psc = v; 513 struct xhci_softc * const sc = &psc->sc_xhci; 514 const bus_space_tag_t bst = sc->sc_iot; 515 const bus_space_handle_t fpcih = psc->sc_bsh_fpci; 516 uint32_t val; 517 uint32_t irv; 518 uint32_t msg; 519 int error; 520 521 DPRINTF(sc->sc_dev, "%s()\n", __func__); 522 523 irv = bus_space_read_4(bst, fpcih, T_XUSB_CFG_ARU_SMI_INTR_REG); 524 DPRINTF(sc->sc_dev, "XUSB_CFG_ARU_SMI_INTR 0x%x\n", irv); 525 bus_space_write_4(bst, fpcih, T_XUSB_CFG_ARU_SMI_INTR_REG, irv); 526 527 if (irv & T_XUSB_CFG_ARU_SMI_INTR_FW_HANG) 528 aprint_error_dev(sc->sc_dev, "firmware hang\n"); 529 530 msg = bus_space_read_4(bst, fpcih, T_XUSB_CFG_ARU_MAILBOX_DATA_OUT_REG); 531 DPRINTF(sc->sc_dev, "XUSB_CFG_ARU_MBOX_DATA_OUT 0x%x\n", msg); 532 533 val = bus_space_read_4(bst, fpcih, T_XUSB_CFG_ARU_MAILBOX_CMD_REG); 534 DPRINTF(sc->sc_dev, "XUSB_CFG_ARU_MBOX_CMD 0x%x\n", val); 535 val &= ~T_XUSB_CFG_ARU_MAILBOX_CMD_DEST_SMI; 536 bus_space_write_4(bst, fpcih, T_XUSB_CFG_ARU_MAILBOX_CMD_REG, val); 537 538 bool sendresp = true; 539 u_int rate; 540 541 const uint32_t data = __SHIFTOUT(msg, MAILBOX_DATA_DATA); 542 const uint8_t type = __SHIFTOUT(msg, MAILBOX_DATA_TYPE); 543 544 switch (type) { 545 case 2: 546 case 3: 547 DPRINTF(sc->sc_dev, "FALC_CLOCK %u\n", data * 1000); 548 break; 549 case 4: 550 case 5: 551 if (psc->sc_txd->txd_scale_ss_clock) { 552 DPRINTF(sc->sc_dev, "SSPI_CLOCK %u\n", data * 1000); 553 rate = clk_get_rate(psc->sc_clk_ss_src); 554 DPRINTF(sc->sc_dev, "rate of psc->sc_clk_ss_src %u\n", 555 rate); 556 error = clk_set_rate(psc->sc_clk_ss_src, data * 1000); 557 if (error != 0) 558 goto clk_fail; 559 rate = clk_get_rate(psc->sc_clk_ss_src); 560 DPRINTF(sc->sc_dev, 561 "rate of psc->sc_clk_ss_src %u after\n", rate); 562 if (data == (rate / 1000)) { 563 msg = __SHIFTIN(128, MAILBOX_DATA_TYPE) | 564 __SHIFTIN(rate / 1000, MAILBOX_DATA_DATA); 565 } else 566 clk_fail: 567 msg = __SHIFTIN(129, MAILBOX_DATA_TYPE) | 568 __SHIFTIN(rate / 1000, MAILBOX_DATA_DATA); 569 } else { 570 msg = __SHIFTIN(128, MAILBOX_DATA_TYPE) | 571 __SHIFTIN(data, MAILBOX_DATA_DATA); 572 } 573 xusb_mailbox_send(psc, msg); 574 break; 575 case 9: 576 msg = __SHIFTIN(data, MAILBOX_DATA_DATA) | 577 __SHIFTIN(128, MAILBOX_DATA_TYPE); 578 xusb_mailbox_send(psc, msg); 579 break; 580 case 6: 581 case 128: 582 case 129: 583 sendresp = false; 584 break; 585 default: 586 sendresp = false; 587 break; 588 } 589 590 if (sendresp == false) 591 bus_space_write_4(bst, fpcih, T_XUSB_CFG_ARU_MAILBOX_OWNER_REG, 592 MAILBOX_OWNER_NONE); 593 594 return irv; 595 } 596 597 static void 598 tegra_xusb_init_regulators(struct tegra_xusb_softc * const psc) 599 { 600 601 device_t dev = psc->sc_xhci.sc_dev; 602 const int phandle = psc->sc_phandle; 603 struct fdtbus_regulator *reg; 604 int n, error; 605 606 for (n = 0; n < psc->sc_txd->txd_nsupplies; n++) { 607 if (!of_hasprop(phandle, psc->sc_txd->txd_supplies[n])) 608 continue; 609 reg = fdtbus_regulator_acquire(phandle, psc->sc_txd->txd_supplies[n]); 610 if (reg == NULL) { 611 aprint_error_dev(dev, "couldn't acquire supply '%s'\n", 612 psc->sc_txd->txd_supplies[n]); 613 continue; 614 } 615 error = fdtbus_regulator_enable(reg); 616 if (error != 0) 617 aprint_error_dev(dev, "couldn't enable supply '%s': %d\n", 618 psc->sc_txd->txd_supplies[n], error); 619 } 620 } 621 622 static void 623 tegra_xusb_init(struct tegra_xusb_softc * const psc) 624 { 625 struct xhci_softc * const sc = &psc->sc_xhci; 626 const bus_space_tag_t bst = sc->sc_iot; 627 const bus_space_handle_t ipfsh = psc->sc_bsh_ipfs; 628 const bus_space_handle_t fpcih = psc->sc_bsh_fpci; 629 630 DPRINTF(sc->sc_dev, "%s()\n", __func__); 631 632 DPRINTF(sc->sc_dev, "%s ipfs 0x0 = 0x%x\n", __func__, 633 bus_space_read_4(bst, ipfsh, 0x0)); 634 635 DPRINTF(sc->sc_dev, "%s ipfs 0x40 = 0x%x\n", __func__, 636 bus_space_read_4(bst, ipfsh, 0x40)); 637 638 DPRINTF(sc->sc_dev, "%s ipfs 0x80 = 0x%x\n", __func__, 639 bus_space_read_4(bst, ipfsh, 0x80)); 640 /* FPCI_BAR0_START and FPCI_BAR0_ACCESS_TYPE */ 641 bus_space_write_4(bst, ipfsh, 0x80, 0x00100000); 642 DPRINTF(sc->sc_dev, "%s ipfs 0x80 = 0x%x\n", __func__, 643 bus_space_read_4(bst, ipfsh, 0x80)); 644 645 DPRINTF(sc->sc_dev, "%s ipfs 0x180 = 0x%x\n", __func__, 646 bus_space_read_4(bst, ipfsh, 0x180)); 647 /* EN_FPCI */ 648 tegra_reg_set_clear(bst, ipfsh, 0x180, 1, 0); 649 DPRINTF(sc->sc_dev, "%s ipfs 0x180 = 0x%x\n", __func__, 650 bus_space_read_4(bst, ipfsh, 0x180)); 651 652 DPRINTF(sc->sc_dev, "%s fpci PCI_COMMAND_STATUS_REG = 0x%x\n", 653 __func__, bus_space_read_4(bst, fpcih, PCI_COMMAND_STATUS_REG)); 654 tegra_reg_set_clear(bst, fpcih, PCI_COMMAND_STATUS_REG, 655 PCI_COMMAND_MASTER_ENABLE|PCI_COMMAND_MEM_ENABLE, 0x0); 656 DPRINTF(sc->sc_dev, "%s fpci PCI_COMMAND_STATUS_REG = 0x%x\n", 657 __func__, bus_space_read_4(bst, fpcih, PCI_COMMAND_STATUS_REG)); 658 659 DPRINTF(sc->sc_dev, "%s fpci PCI_BAR0 = 0x%x\n", __func__, 660 bus_space_read_4(bst, fpcih, PCI_BAR0)); 661 /* match FPCI BAR0 to above */ 662 bus_space_write_4(bst, fpcih, PCI_BAR0, 0x10000000); 663 DPRINTF(sc->sc_dev, "%s fpci PCI_BAR0 = 0x%x\n", __func__, 664 bus_space_read_4(bst, fpcih, PCI_BAR0)); 665 666 DPRINTF(sc->sc_dev, "%s ipfs 0x188 = 0x%x\n", __func__, 667 bus_space_read_4(bst, ipfsh, 0x188)); 668 tegra_reg_set_clear(bst, ipfsh, 0x188, __BIT(16), 0); 669 DPRINTF(sc->sc_dev, "%s ipfs 0x188 = 0x%x\n", __func__, 670 bus_space_read_4(bst, ipfsh, 0x188)); 671 672 DPRINTF(sc->sc_dev, "%s fpci 0x1bc = 0x%x\n", __func__, 673 bus_space_read_4(bst, fpcih, 0x1bc)); 674 bus_space_write_4(bst, fpcih, 0x1bc, 0x80); 675 DPRINTF(sc->sc_dev, "%s fpci 0x1bc = 0x%x\n", __func__, 676 bus_space_read_4(bst, fpcih, 0x1bc)); 677 } 678 679 static int 680 fw_dma_alloc(struct tegra_xusb_softc * const psc, size_t size, size_t align, 681 struct fw_dma * const p) 682 { 683 struct xhci_softc * const sc = &psc->sc_xhci; 684 const bus_dma_tag_t dmat = sc->sc_bus.ub_dmatag; 685 int err; 686 687 p->size = size; 688 err = bus_dmamem_alloc(dmat, p->size, align, 0, p->segs, 689 sizeof(p->segs) / sizeof(p->segs[0]), &p->nsegs, BUS_DMA_NOWAIT); 690 if (err) 691 return err; 692 err = bus_dmamem_map(dmat, p->segs, p->nsegs, p->size, &p->addr, 693 BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 694 if (err) 695 goto free; 696 err = bus_dmamap_create(dmat, p->size, 1, p->size, 0, BUS_DMA_NOWAIT, 697 &p->map); 698 if (err) 699 goto unmap; 700 err = bus_dmamap_load(dmat, p->map, p->addr, p->size, NULL, 701 BUS_DMA_NOWAIT); 702 if (err) 703 goto destroy; 704 705 return 0; 706 707 destroy: 708 bus_dmamap_destroy(dmat, p->map); 709 unmap: 710 bus_dmamem_unmap(dmat, p->addr, p->size); 711 free: 712 bus_dmamem_free(dmat, p->segs, p->nsegs); 713 714 return err; 715 } 716 717 static void 718 fw_dma_free(struct tegra_xusb_softc * const psc, struct fw_dma * const p) 719 { 720 const struct xhci_softc * const sc = &psc->sc_xhci; 721 const bus_dma_tag_t dmat = sc->sc_bus.ub_dmatag; 722 723 bus_dmamap_unload(dmat, p->map); 724 bus_dmamap_destroy(dmat, p->map); 725 bus_dmamem_unmap(dmat, p->addr, p->size); 726 bus_dmamem_free(dmat, p->segs, p->nsegs); 727 } 728 729 #define FWHEADER_BOOT_CODETAG 8 730 #define FWHEADER_BOOT_CODESIZE 12 731 #define FWHEADER_FWIMG_LEN 100 732 #define FWHEADER__LEN 256 733 734 static int 735 tegra_xusb_open_fw(struct tegra_xusb_softc * const psc) 736 { 737 struct xhci_softc * const sc = &psc->sc_xhci; 738 firmware_handle_t fw; 739 size_t firmware_size = 0; 740 void *firmware_image; 741 const char *fw_path = NULL; 742 void *fw_static = NULL; 743 int error; 744 745 switch (psc->sc_txd->txd_type) { 746 case XUSB_T124: 747 #if defined(TEGRA124_XUSB_BIN_STATIC) 748 firmware_size = (uintptr_t)&_binary_tegra124_xusb_bin_end 749 - (uintptr_t)&_binary_tegra124_xusb_bin_start; 750 fw_static = __UNCONST(_binary_tegra124_xusb_bin_start); 751 #else 752 fw_path = "nvidia/tegra124"; 753 #endif 754 break; 755 case XUSB_T210: 756 #if defined(TEGRA210_XUSB_BIN_STATIC) 757 firmware_size = (uintptr_t)&_binary_tegra210_xusb_bin_end 758 - (uintptr_t)&_binary_tegra210_xusb_bin_start; 759 fw_static = __UNCONST(_binary_tegra210_xusb_bin_start); 760 #else 761 fw_path = "nvidia/tegra210"; 762 #endif 763 break; 764 default: 765 return EINVAL; 766 } 767 768 if (fw_path != NULL) { 769 error = firmware_open(fw_path, "xusb.bin", &fw); 770 if (error != 0) { 771 aprint_error_dev(sc->sc_dev, 772 "couldn't load firmware from %s/xusb.bin: %d\n", 773 fw_path, error); 774 return error; 775 } 776 firmware_size = firmware_get_size(fw); 777 } 778 779 error = fw_dma_alloc(psc, firmware_size, PAGE_SIZE, 780 &psc->sc_fw_dma); 781 if (error != 0) 782 return error; 783 firmware_image = psc->sc_fw_dma.addr; 784 785 if (fw_path != NULL) { 786 error = firmware_read(fw, 0, firmware_image, firmware_size); 787 if (error != 0) { 788 fw_dma_free(psc, &psc->sc_fw_dma); 789 firmware_close(fw); 790 return error; 791 } 792 firmware_close(fw); 793 } else { 794 memcpy(firmware_image, fw_static, firmware_size); 795 } 796 797 return tegra_xusb_load_fw(psc, firmware_image, firmware_size); 798 } 799 800 static int 801 tegra_xusb_load_fw(struct tegra_xusb_softc * const psc, void *firmware_image, 802 size_t firmware_size) 803 { 804 struct xhci_softc * const sc = &psc->sc_xhci; 805 const uint8_t *header; 806 807 header = firmware_image; 808 809 const uint32_t fwimg_len = le32dec(&header[FWHEADER_FWIMG_LEN]); 810 const uint32_t boot_codetag = le32dec(&header[FWHEADER_BOOT_CODETAG]); 811 const uint32_t boot_codesize = le32dec(&header[FWHEADER_BOOT_CODESIZE]); 812 813 if (fwimg_len != firmware_size) 814 aprint_error_dev(sc->sc_dev, "fwimg_len mismatch %u != %zu\n", 815 fwimg_len, firmware_size); 816 817 bus_dmamap_sync(sc->sc_bus.ub_dmatag, psc->sc_fw_dma.map, 0, 818 firmware_size, BUS_DMASYNC_PREWRITE); 819 820 DPRINTF(sc->sc_dev, "XUSB_FALC_CPUCTL 0x%x\n", 821 csb_read_4(psc, XUSB_CSB_FALCON_CPUCTL_REG)); 822 DPRINTF(sc->sc_dev, "XUSB_CSB_MP_ILOAD_BASE_LO 0x%x\n", 823 csb_read_4(psc, XUSB_CSB_MEMPOOL_ILOAD_BASE_LO_REG)); 824 825 DPRINTF(sc->sc_dev, "XUSB_CSB_MP_ILOAD_ATTR 0x%x\n", 826 csb_read_4(psc, XUSB_CSB_MEMPOOL_ILOAD_ATTR_REG)); 827 csb_write_4(psc, XUSB_CSB_MEMPOOL_ILOAD_ATTR_REG, 828 fwimg_len); 829 DPRINTF(sc->sc_dev, "XUSB_CSB_MP_ILOAD_ATTR 0x%x\n", 830 csb_read_4(psc, XUSB_CSB_MEMPOOL_ILOAD_ATTR_REG)); 831 832 const uint64_t fwbase = psc->sc_fw_dma.map->dm_segs[0].ds_addr + 833 FWHEADER__LEN; 834 835 csb_write_4(psc, XUSB_CSB_MEMPOOL_ILOAD_BASE_HI_REG, fwbase >> 32); 836 csb_write_4(psc, XUSB_CSB_MEMPOOL_ILOAD_BASE_LO_REG, fwbase); 837 DPRINTF(sc->sc_dev, "XUSB_CSB_MP_ILOAD_BASE_LO 0x%x\n", 838 csb_read_4(psc, XUSB_CSB_MEMPOOL_ILOAD_BASE_LO_REG)); 839 DPRINTF(sc->sc_dev, "XUSB_CSB_MP_ILOAD_BASE_HI 0x%x\n", 840 csb_read_4(psc, XUSB_CSB_MEMPOOL_ILOAD_BASE_HI_REG)); 841 842 DPRINTF(sc->sc_dev, "XUSB_CSB_MP_APMAP 0x%x\n", 843 csb_read_4(psc, XUSB_CSB_MEMPOOL_APMAP_REG)); 844 csb_write_4(psc, XUSB_CSB_MEMPOOL_APMAP_REG, 845 XUSB_CSB_MEMPOOL_APMAP_BOOTPATH); 846 DPRINTF(sc->sc_dev, "XUSB_CSB_MP_APMAP 0x%x\n", 847 csb_read_4(psc, XUSB_CSB_MEMPOOL_APMAP_REG)); 848 849 DPRINTF(sc->sc_dev, "XUSB_CSB_MP_L2IMEMOP_TRIG 0x%x\n", 850 csb_read_4(psc, XUSB_CSB_MEMPOOL_L2IMEMOP_TRIG_REG)); 851 csb_write_4(psc, XUSB_CSB_MEMPOOL_L2IMEMOP_TRIG_REG, 852 __SHIFTIN(ACTION_L2IMEM_INVALIDATE_ALL, 853 XUSB_CSB_MEMPOOL_L2IMEMOP_TRIG_ACTION)); 854 DPRINTF(sc->sc_dev, "XUSB_CSB_MP_L2IMEMOP_TRIG 0x%x\n", 855 csb_read_4(psc, XUSB_CSB_MEMPOOL_L2IMEMOP_TRIG_REG)); 856 857 const u_int code_tag_blocks = 858 howmany(boot_codetag, IMEM_BLOCK_SIZE); 859 const u_int code_size_blocks = 860 howmany(boot_codesize, IMEM_BLOCK_SIZE); 861 const u_int code_blocks = code_tag_blocks + code_size_blocks; 862 863 DPRINTF(sc->sc_dev, "XUSB_CSB_MP_L2IMEMOP_SIZE 0x%x\n", 864 csb_read_4(psc, XUSB_CSB_MEMPOOL_L2IMEMOP_SIZE_REG)); 865 csb_write_4(psc, XUSB_CSB_MEMPOOL_L2IMEMOP_SIZE_REG, 866 __SHIFTIN(code_tag_blocks, 867 XUSB_CSB_MEMPOOL_L2IMEMOP_SIZE_SRC_OFFSET) | 868 __SHIFTIN(code_size_blocks, 869 XUSB_CSB_MEMPOOL_L2IMEMOP_SIZE_SRC_COUNT)); 870 DPRINTF(sc->sc_dev, "XUSB_CSB_MP_L2IMEMOP_SIZE 0x%x\n", 871 csb_read_4(psc, XUSB_CSB_MEMPOOL_L2IMEMOP_SIZE_REG)); 872 873 DPRINTF(sc->sc_dev, "XUSB_CSB_MP_L2IMEMOP_TRIG 0x%x\n", 874 csb_read_4(psc, XUSB_CSB_MEMPOOL_L2IMEMOP_TRIG_REG)); 875 csb_write_4(psc, XUSB_CSB_MEMPOOL_L2IMEMOP_TRIG_REG, 876 __SHIFTIN(ACTION_L2IMEM_LOAD_LOCKED_RESULT, 877 XUSB_CSB_MEMPOOL_L2IMEMOP_TRIG_ACTION)); 878 DPRINTF(sc->sc_dev, "XUSB_CSB_MP_L2IMEMOP_TRIG 0x%x\n", 879 csb_read_4(psc, XUSB_CSB_MEMPOOL_L2IMEMOP_TRIG_REG)); 880 881 DPRINTF(sc->sc_dev, "XUSB_FALC_IMFILLCTL 0x%x\n", 882 csb_read_4(psc, XUSB_CSB_FALCON_IMFILLCTL_REG)); 883 csb_write_4(psc, XUSB_CSB_FALCON_IMFILLCTL_REG, code_size_blocks); 884 DPRINTF(sc->sc_dev, "XUSB_FALC_IMFILLCTL 0x%x\n", 885 csb_read_4(psc, XUSB_CSB_FALCON_IMFILLCTL_REG)); 886 887 DPRINTF(sc->sc_dev, "XUSB_FALC_IMFILLRNG1 0x%x\n", 888 csb_read_4(psc, XUSB_CSB_FALCON_IMFILLRNG1_REG)); 889 csb_write_4(psc, XUSB_CSB_FALCON_IMFILLRNG1_REG, 890 __SHIFTIN(code_tag_blocks, XUSB_CSB_FALCON_IMFILLRNG1_TAG_LO) | 891 __SHIFTIN(code_blocks, XUSB_CSB_FALCON_IMFILLRNG1_TAG_HI)); 892 DPRINTF(sc->sc_dev, "XUSB_FALC_IMFILLRNG1 0x%x\n", 893 csb_read_4(psc, XUSB_CSB_FALCON_IMFILLRNG1_REG)); 894 895 DPRINTF(sc->sc_dev, "XUSB_FALC_DMACTL 0x%x\n", 896 csb_read_4(psc, XUSB_CSB_FALCON_DMACTL_REG)); 897 csb_write_4(psc, XUSB_CSB_FALCON_DMACTL_REG, 0); 898 DPRINTF(sc->sc_dev, "XUSB_FALC_DMACTL 0x%x\n", 899 csb_read_4(psc, XUSB_CSB_FALCON_DMACTL_REG)); 900 901 DPRINTF(sc->sc_dev, "XUSB_FALC_BOOTVEC 0x%x\n", 902 csb_read_4(psc, XUSB_CSB_FALCON_BOOTVEC_REG)); 903 csb_write_4(psc, XUSB_CSB_FALCON_BOOTVEC_REG, 904 boot_codetag); 905 DPRINTF(sc->sc_dev, "XUSB_FALC_BOOTVEC 0x%x\n", 906 csb_read_4(psc, XUSB_CSB_FALCON_BOOTVEC_REG)); 907 908 DPRINTF(sc->sc_dev, "XUSB_FALC_CPUCTL 0x%x\n", 909 csb_read_4(psc, XUSB_CSB_FALCON_CPUCTL_REG)); 910 csb_write_4(psc, XUSB_CSB_FALCON_CPUCTL_REG, 911 XUSB_CSB_FALCON_CPUCTL_STARTCPU); 912 DPRINTF(sc->sc_dev, "XUSB_FALC_CPUCTL 0x%x\n", 913 csb_read_4(psc, XUSB_CSB_FALCON_CPUCTL_REG)); 914 915 return 0; 916 } 917 918 static uint32_t 919 csb_read_4(struct tegra_xusb_softc * const psc, bus_size_t csb_offset) 920 { 921 const uint32_t range = __SHIFTOUT(csb_offset, XUSB_CSB_RANGE); 922 const bus_size_t offset = __SHIFTOUT(csb_offset, XUSB_CSB_OFFSET); 923 const bus_space_tag_t bst = psc->sc_xhci.sc_iot; 924 const bus_space_handle_t fpcih = psc->sc_bsh_fpci; 925 926 bus_space_write_4(bst, fpcih, T_XUSB_CFG_ARU_C11_CSBRANGE_REG, range); 927 return bus_space_read_4(bst, fpcih, T_XUSB_CFG_CSB_BASE_ADDR + offset); 928 } 929 930 static void 931 csb_write_4(struct tegra_xusb_softc * const psc, bus_size_t csb_offset, 932 uint32_t value) 933 { 934 const uint32_t range = __SHIFTOUT(csb_offset, XUSB_CSB_RANGE); 935 const bus_size_t offset = __SHIFTOUT(csb_offset, XUSB_CSB_OFFSET); 936 const bus_space_tag_t bst = psc->sc_xhci.sc_iot; 937 const bus_space_handle_t fpcih = psc->sc_bsh_fpci; 938 939 bus_space_write_4(bst, fpcih, T_XUSB_CFG_ARU_C11_CSBRANGE_REG, range); 940 bus_space_write_4(bst, fpcih, T_XUSB_CFG_CSB_BASE_ADDR + offset, value); 941 } 942 943 static int 944 xusb_mailbox_send(struct tegra_xusb_softc * const psc, uint32_t msg) 945 { 946 struct xhci_softc * const sc = &psc->sc_xhci; 947 const bus_space_tag_t bst = psc->sc_xhci.sc_iot; 948 const bus_space_handle_t fpcih = psc->sc_bsh_fpci; 949 uint32_t val; 950 bool wait = false; 951 952 const uint8_t type = __SHIFTOUT(msg, MAILBOX_DATA_TYPE); 953 954 if (!(type == 128 || type == 129)) { 955 val = bus_space_read_4(bst, fpcih, 956 T_XUSB_CFG_ARU_MAILBOX_OWNER_REG); 957 DPRINTF(sc->sc_dev, "XUSB_CFG_ARU_MBOX_OWNER 0x%x\n", 958 val); 959 if (val != MAILBOX_OWNER_NONE) { 960 return EBUSY; 961 } 962 963 bus_space_write_4(bst, fpcih, T_XUSB_CFG_ARU_MAILBOX_OWNER_REG, 964 MAILBOX_OWNER_SW); 965 966 val = bus_space_read_4(bst, fpcih, 967 T_XUSB_CFG_ARU_MAILBOX_OWNER_REG); 968 DPRINTF(sc->sc_dev, "XUSB_CFG_ARU_MBOX_OWNER 0x%x\n", 969 val); 970 if (val != MAILBOX_OWNER_SW) { 971 return EBUSY; 972 } 973 974 wait = true; 975 } 976 977 bus_space_write_4(bst, fpcih, T_XUSB_CFG_ARU_MAILBOX_DATA_IN_REG, msg); 978 979 tegra_reg_set_clear(bst, fpcih, T_XUSB_CFG_ARU_MAILBOX_CMD_REG, 980 T_XUSB_CFG_ARU_MAILBOX_CMD_INT_EN | 981 T_XUSB_CFG_ARU_MAILBOX_CMD_DEST_FALCON, 0); 982 983 if (wait) { 984 985 for (u_int i = 0; i < 2500; i++) { 986 val = bus_space_read_4(bst, fpcih, 987 T_XUSB_CFG_ARU_MAILBOX_OWNER_REG); 988 DPRINTF(sc->sc_dev, 989 "XUSB_CFG_ARU_MBOX_OWNER 0x%x\n", val); 990 if (val == MAILBOX_OWNER_NONE) { 991 break; 992 } 993 DELAY(10); 994 } 995 996 val = bus_space_read_4(bst, fpcih, 997 T_XUSB_CFG_ARU_MAILBOX_OWNER_REG); 998 DPRINTF(sc->sc_dev, 999 "XUSB_CFG_ARU_MBOX_OWNER 0x%x\n", val); 1000 if (val != MAILBOX_OWNER_NONE) { 1001 aprint_error_dev(sc->sc_dev, 1002 "timeout, XUSB_CFG_ARU_MBOX_OWNER 0x%x\n", val); 1003 } 1004 } 1005 1006 return 0; 1007 } 1008
Indexes created Wed Sep 24 22:09:59 GMT 2025