tegra_xusb.c revision 1.21
1 /* $NetBSD: tegra_xusb.c,v 1.21 2020/10/15 09:33:17 jmcneill Exp $ */ 2 3 /* 4 * Copyright (c) 2016 Jonathan A. Kollasch 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR 20 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 21 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 22 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 23 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 25 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 26 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include "locators.h" 30 #include "opt_tegra.h" 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: tegra_xusb.c,v 1.21 2020/10/15 09:33:17 jmcneill Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/bus.h> 37 #include <sys/device.h> 38 #include <sys/intr.h> 39 #include <sys/systm.h> 40 #include <sys/kernel.h> 41 42 #include <arm/nvidia/tegra_reg.h> 43 #include <arm/nvidia/tegra_var.h> 44 #include <arm/nvidia/tegra_xusbpad.h> 45 #include <arm/nvidia/tegra_xusbreg.h> 46 #include <arm/nvidia/tegra_pmcreg.h> 47 48 #include <dev/pci/pcireg.h> 49 50 #include <dev/fdt/fdtvar.h> 51 52 #include <dev/firmload.h> 53 54 #include <dev/usb/usb.h> 55 #include <dev/usb/usbdi.h> 56 #include <dev/usb/usbdivar.h> 57 #include <dev/usb/usb_mem.h> 58 59 #include <dev/usb/xhcireg.h> 60 #include <dev/usb/xhcivar.h> 61 62 #ifdef TEGRA_XUSB_DEBUG 63 int tegra_xusb_debug = 1; 64 #else 65 int tegra_xusb_debug = 0; 66 #endif 67 68 #define DPRINTF(...) if (tegra_xusb_debug) device_printf(__VA_ARGS__) 69 70 static int tegra_xusb_match(device_t, cfdata_t, void *); 71 static void tegra_xusb_attach(device_t, device_t, void *); 72 static void tegra_xusb_mountroot(device_t); 73 74 static int tegra_xusb_intr_mbox(void *); 75 76 #ifdef TEGRA124_XUSB_BIN_STATIC 77 extern const char _binary_tegra124_xusb_bin_start[]; 78 extern const char _binary_tegra124_xusb_bin_end[]; 79 __asm__( 80 ".section \".rodata\"\n" 81 "_binary_tegra124_xusb_bin_start:\n" 82 ".incbin \"../external/nvidia-firmware/tegra/dist/tegra124/xusb.bin\"\n" 83 ".size _binary_tegra124_xusb_bin_start, . - _binary_tegra124_xusb_bin_start\n" 84 "_binary_tegra124_xusb_bin_end:\n" 85 ".previous\n" 86 ); 87 #endif 88 89 #ifdef TEGRA210_XUSB_BIN_STATIC 90 extern const char _binary_tegra210_xusb_bin_start[]; 91 extern const char _binary_tegra210_xusb_bin_end[]; 92 __asm__( 93 ".section \".rodata\"\n" 94 "_binary_tegra210_xusb_bin_start:\n" 95 ".incbin \"../external/nvidia-firmware/tegra/dist/tegra210/xusb.bin\"\n" 96 ".size _binary_tegra210_xusb_bin_start, . - _binary_tegra210_xusb_bin_start\n" 97 "_binary_tegra210_xusb_bin_end:\n" 98 ".previous\n" 99 ); 100 #endif 101 102 enum xusb_type { 103 XUSB_T124 = 1, 104 XUSB_T210 105 }; 106 107 struct tegra_xhci_data { 108 enum xusb_type txd_type; 109 const char * const * txd_supplies; 110 size_t txd_nsupplies; 111 bool txd_scale_ss_clock; 112 }; 113 114 const char *tegra124_xhci_supplies[] = { 115 "dvddio-pex-supply", 116 "hvddio-pex-supply", 117 "avdd-usb-supply", 118 "avdd-pll-utmip-supply", 119 "avdd-pll-uerefe-supply", 120 "dvdd-usb-ss-pll-supply", 121 "hvdd-usb-ss-pll-e-supply" 122 }; 123 124 struct tegra_xhci_data tegra124_xhci_data = { 125 .txd_type = XUSB_T124, 126 .txd_supplies = tegra124_xhci_supplies, 127 .txd_nsupplies = __arraycount(tegra124_xhci_supplies), 128 .txd_scale_ss_clock = true, 129 }; 130 131 const char *tegra210_xhci_supplies[] = { 132 "dvddio-pex", 133 "hvddio-pex", 134 "avdd-usb", 135 "avdd-pll-utmip", 136 "avdd-pll-uerefe", 137 "dvdd-pex-pll", 138 "hvdd-pex-pll-e", 139 }; 140 141 struct tegra_xhci_data tegra210_xhci_data = { 142 .txd_type = XUSB_T210, 143 .txd_supplies = tegra210_xhci_supplies, 144 .txd_nsupplies = __arraycount(tegra210_xhci_supplies), 145 .txd_scale_ss_clock = false, 146 }; 147 148 static const struct of_compat_data compat_data[] = { 149 { "nvidia,tegra124-xusb", (uintptr_t)&tegra124_xhci_data }, 150 { "nvidia,tegra210-xusb", (uintptr_t)&tegra210_xhci_data }, 151 { NULL } 152 }; 153 154 struct fw_dma { 155 bus_dmamap_t map; 156 void * addr; 157 bus_dma_segment_t segs[1]; 158 int nsegs; 159 size_t size; 160 }; 161 162 struct tegra_xusb_softc { 163 struct xhci_softc sc_xhci; 164 int sc_phandle; 165 bus_space_handle_t sc_bsh_xhci; 166 bus_space_handle_t sc_bsh_fpci; 167 bus_space_handle_t sc_bsh_ipfs; 168 void *sc_ih; 169 void *sc_ih_mbox; 170 struct fw_dma sc_fw_dma; 171 struct clk *sc_clk_ss_src; 172 173 struct tegra_xhci_data *sc_txd; 174 }; 175 176 static uint32_t csb_read_4(struct tegra_xusb_softc * const, bus_size_t); 177 static void csb_write_4(struct tegra_xusb_softc * const, bus_size_t, 178 uint32_t); 179 180 static void tegra_xusb_init(struct tegra_xusb_softc * const); 181 static int tegra_xusb_open_fw(struct tegra_xusb_softc * const); 182 static int tegra_xusb_load_fw(struct tegra_xusb_softc * const, void *, 183 size_t); 184 static void tegra_xusb_init_regulators(struct tegra_xusb_softc * const); 185 186 static int xusb_mailbox_send(struct tegra_xusb_softc * const, uint32_t); 187 188 CFATTACH_DECL_NEW(tegra_xusb, sizeof(struct tegra_xusb_softc), 189 tegra_xusb_match, tegra_xusb_attach, NULL, NULL); 190 191 static int 192 tegra_xusb_match(device_t parent, cfdata_t cf, void *aux) 193 { 194 struct fdt_attach_args * const faa = aux; 195 196 return of_match_compat_data(faa->faa_phandle, compat_data); 197 } 198 199 #define tegra_xusb_attach_check(sc, cond, fmt, ...) \ 200 do { \ 201 if (cond) { \ 202 aprint_error_dev(sc->sc_dev, fmt, ## __VA_ARGS__); \ 203 return; \ 204 } \ 205 } while (0) 206 207 static void 208 tegra_xusb_attach(device_t parent, device_t self, void *aux) 209 { 210 struct tegra_xusb_softc * const psc = device_private(self); 211 struct xhci_softc * const sc = &psc->sc_xhci; 212 struct fdt_attach_args * const faa = aux; 213 bool wait_for_root = true; 214 char intrstr[128]; 215 bus_addr_t addr; 216 bus_size_t size; 217 struct fdtbus_reset *rst; 218 struct fdtbus_phy *phy; 219 struct clk *clk; 220 uint32_t rate; 221 int error, n; 222 223 aprint_naive("\n"); 224 aprint_normal(": XUSB\n"); 225 226 sc->sc_dev = self; 227 sc->sc_iot = faa->faa_bst; 228 sc->sc_bus.ub_hcpriv = sc; 229 sc->sc_bus.ub_dmatag = faa->faa_dmat; 230 sc->sc_quirks = XHCI_DEFERRED_START; 231 psc->sc_phandle = faa->faa_phandle; 232 233 uintptr_t data = of_search_compatible(faa->faa_phandle, compat_data)->data; 234 psc->sc_txd = (struct tegra_xhci_data *)data; 235 236 if (fdtbus_get_reg_byname(faa->faa_phandle, "hcd", &addr, &size) != 0) { 237 aprint_error(": couldn't get registers\n"); 238 return; 239 } 240 error = bus_space_map(sc->sc_iot, addr, size, 0, &sc->sc_ioh); 241 if (error) { 242 aprint_error(": couldn't map %#" PRIxBUSADDR ": %d", addr, error); 243 return; 244 } 245 DPRINTF(sc->sc_dev, "mapped %#" PRIxBUSADDR "\n", addr); 246 sc->sc_ios = size; 247 248 if (fdtbus_get_reg_byname(faa->faa_phandle, "fpci", &addr, &size) != 0) { 249 aprint_error(": couldn't get registers\n"); 250 return; 251 } 252 error = bus_space_map(sc->sc_iot, addr, size, 0, &psc->sc_bsh_fpci); 253 if (error) { 254 aprint_error(": couldn't map %#" PRIxBUSADDR ": %d", addr, error); 255 return; 256 } 257 DPRINTF(sc->sc_dev, "mapped %#" PRIxBUSADDR "\n", addr); 258 259 if (fdtbus_get_reg_byname(faa->faa_phandle, "ipfs", &addr, &size) != 0) { 260 aprint_error(": couldn't get registers\n"); 261 return; 262 } 263 error = bus_space_map(sc->sc_iot, addr, size, 0, &psc->sc_bsh_ipfs); 264 if (error) { 265 aprint_error(": couldn't map %#" PRIxBUSADDR ": %d", addr, error); 266 return; 267 } 268 DPRINTF(sc->sc_dev, "mapped %#" PRIxBUSADDR "\n", addr); 269 270 if (!fdtbus_intr_str(faa->faa_phandle, 0, intrstr, sizeof(intrstr))) { 271 aprint_error_dev(self, "failed to decode interrupt\n"); 272 return; 273 } 274 275 psc->sc_ih = fdtbus_intr_establish(faa->faa_phandle, 0, IPL_USB, 276 FDT_INTR_MPSAFE, xhci_intr, sc); 277 if (psc->sc_ih == NULL) { 278 aprint_error_dev(self, "failed to establish interrupt on %s\n", 279 intrstr); 280 return; 281 } 282 aprint_normal_dev(self, "interrupting on %s\n", intrstr); 283 284 if (!fdtbus_intr_str(faa->faa_phandle, 1, intrstr, sizeof(intrstr))) { 285 aprint_error_dev(self, "failed to decode interrupt\n"); 286 return; 287 } 288 289 psc->sc_ih_mbox = fdtbus_intr_establish(faa->faa_phandle, 1, IPL_VM, 290 FDT_INTR_MPSAFE, tegra_xusb_intr_mbox, psc); 291 if (psc->sc_ih_mbox == NULL) { 292 aprint_error_dev(self, "failed to establish interrupt on %s\n", 293 intrstr); 294 return; 295 } 296 aprint_normal_dev(self, "interrupting on %s\n", intrstr); 297 298 /* Enable PHYs */ 299 for (n = 0; (phy = fdtbus_phy_get_index(faa->faa_phandle, n)) != NULL; n++) 300 if (fdtbus_phy_enable(phy, true) != 0) 301 aprint_error_dev(self, "failed to enable PHY #%d\n", n); 302 303 /* Enable XUSB power rails */ 304 305 tegra_pmc_power(PMC_PARTID_XUSBC, true); /* Host/USB2.0 */ 306 tegra_pmc_remove_clamping(PMC_PARTID_XUSBC); 307 tegra_pmc_power(PMC_PARTID_XUSBA, true); /* SuperSpeed */ 308 tegra_pmc_remove_clamping(PMC_PARTID_XUSBA); 309 310 /* Enable XUSB clocks */ 311 312 clk = fdtbus_clock_get(faa->faa_phandle, "pll_e"); 313 rate = clk_get_rate(clk); 314 error = clk_enable(clk); /* XXX set frequency */ 315 DPRINTF(sc->sc_dev, "rate %u error %d\n", rate, error); 316 tegra_xusb_attach_check(sc, error, "failed to enable pll_e clock"); 317 318 clk = fdtbus_clock_get(faa->faa_phandle, "xusb_host_src"); 319 rate = clk_get_rate(clk); 320 DPRINTF(sc->sc_dev, "rate %u error %d\n", rate, error); 321 error = clk_set_rate(clk, 102000000); 322 tegra_xusb_attach_check(sc, error, "failed to set xusb_host_src clock rate"); 323 324 rate = clk_get_rate(clk); 325 error = clk_enable(clk); /* XXX set frequency */ 326 DPRINTF(sc->sc_dev, "rate %u error %d\n", rate, error); 327 tegra_xusb_attach_check(sc, error, "failed to enable xusb_host_src clock"); 328 329 clk = fdtbus_clock_get(faa->faa_phandle, "xusb_falcon_src"); 330 rate = clk_get_rate(clk); 331 DPRINTF(sc->sc_dev, "rate %u error %d\n", rate, error); 332 error = clk_set_rate(clk, 204000000); 333 tegra_xusb_attach_check(sc, error, "failed to set xusb_falcon_src clock rate"); 334 335 rate = clk_get_rate(clk); 336 error = clk_enable(clk); 337 DPRINTF(sc->sc_dev, "rate %u error %d\n", rate, error); 338 tegra_xusb_attach_check(sc, error, "failed to enable xusb_falcon_src clock"); 339 340 clk = fdtbus_clock_get(faa->faa_phandle, "xusb_host"); 341 rate = clk_get_rate(clk); 342 error = clk_enable(clk); /* XXX set frequency */ 343 DPRINTF(sc->sc_dev, "rate %u error %d\n", rate, error); 344 345 clk = fdtbus_clock_get(faa->faa_phandle, "xusb_ss"); 346 rate = clk_get_rate(clk); 347 error = clk_enable(clk); /* XXX set frequency */ 348 DPRINTF(sc->sc_dev, "xusb_ss rate %u error %d\n", rate, error); 349 tegra_xusb_attach_check(sc, error, "failed to enable xusb_ss clock"); 350 351 psc->sc_clk_ss_src = fdtbus_clock_get(faa->faa_phandle, "xusb_ss_src"); 352 tegra_xusb_attach_check(sc, psc->sc_clk_ss_src == NULL, 353 "failed to get xusb_ss_src clock"); 354 355 if (psc->sc_txd->txd_scale_ss_clock) { 356 rate = clk_get_rate(psc->sc_clk_ss_src); 357 DPRINTF(sc->sc_dev, "xusb_ss_src rate %u\n", rate); 358 error = clk_set_rate(psc->sc_clk_ss_src, 2000000); 359 rate = clk_get_rate(psc->sc_clk_ss_src); 360 DPRINTF(sc->sc_dev, "xusb_ss_src rate %u error %d\n", rate, error); 361 tegra_xusb_attach_check(sc, error, "failed to get xusb_ss_src clock rate"); 362 363 rate = clk_get_rate(psc->sc_clk_ss_src); 364 DPRINTF(sc->sc_dev, "ss_src rate %u\n", rate); 365 tegra_xusb_attach_check(sc, error, "failed to set xusb_ss_src clock rate"); 366 367 error = clk_set_rate(psc->sc_clk_ss_src, 120000000); 368 rate = clk_get_rate(psc->sc_clk_ss_src); 369 DPRINTF(sc->sc_dev, "ss_src rate %u error %d\n", rate, error); 370 tegra_xusb_attach_check(sc, error, "failed to get xusb_ss_src clock rate"); 371 } 372 373 rate = clk_get_rate(psc->sc_clk_ss_src); 374 error = clk_enable(psc->sc_clk_ss_src); 375 DPRINTF(sc->sc_dev, "ss_src rate %u error %d\n", rate, error); 376 tegra_xusb_attach_check(sc, error, "failed to enable xusb_ss_src clock"); 377 378 #if 0 379 clk = fdtbus_clock_get(faa->faa_phandle, "xusb_hs_src"); 380 error = 0; 381 rate = clk_get_rate(clk); 382 DPRINTF(sc->sc_dev, "rate %u error %d\n", rate, error); 383 #endif 384 385 clk = fdtbus_clock_get(faa->faa_phandle, "xusb_fs_src"); 386 rate = clk_get_rate(clk); 387 error = clk_enable(clk); /* XXX set frequency */ 388 DPRINTF(sc->sc_dev, "rate %u error %d\n", rate, error); 389 tegra_xusb_attach_check(sc, error, "failed to enable xusb_fs_src clock"); 390 391 rst = fdtbus_reset_get(faa->faa_phandle, "xusb_host"); 392 fdtbus_reset_deassert(rst); 393 394 rst = fdtbus_reset_get(faa->faa_phandle, "xusb_src"); 395 fdtbus_reset_deassert(rst); 396 397 rst = fdtbus_reset_get(faa->faa_phandle, "xusb_ss"); 398 fdtbus_reset_deassert(rst); 399 400 DELAY(1); 401 402 tegra_xusb_init_regulators(psc); 403 404 tegra_xusb_init(psc); 405 406 #if defined(TEGRA124_XUSB_BIN_STATIC) 407 if (psc->sc_txd->txd_type == XUSB_T124) 408 wait_for_root = false; 409 #endif 410 #if defined(TEGRA210_XUSB_BIN_STATIC) 411 if (psc->sc_txd->txd_type == XUSB_T210) 412 wait_for_root = false; 413 #endif 414 415 if (wait_for_root) 416 config_mountroot(sc->sc_dev, tegra_xusb_mountroot); 417 else 418 tegra_xusb_mountroot(sc->sc_dev); 419 } 420 421 static void 422 tegra_xusb_mountroot(device_t self) 423 { 424 struct tegra_xusb_softc * const psc = device_private(self); 425 struct xhci_softc * const sc = &psc->sc_xhci; 426 const bus_space_tag_t bst = sc->sc_iot; 427 const bus_space_handle_t ipfsh = psc->sc_bsh_ipfs; 428 struct clk *clk; 429 struct fdtbus_reset *rst; 430 uint32_t rate; 431 uint32_t val; 432 int error; 433 434 DPRINTF(sc->sc_dev, "%s()\n", __func__); 435 436 val = bus_space_read_4(bst, ipfsh, 0x0); 437 DPRINTF(sc->sc_dev, "%s ipfs 0x0 = 0x%x\n", __func__, val); 438 439 if (tegra_xusb_open_fw(psc) != 0) 440 return; 441 DPRINTF(sc->sc_dev, "post fw\n"); 442 443 tegra_xusbpad_xhci_enable(); 444 445 clk = fdtbus_clock_get(psc->sc_phandle, "xusb_falcon_src"); 446 rate = clk_get_rate(clk); 447 error = clk_enable(clk); 448 DPRINTF(sc->sc_dev, "rate %u error %d\n", rate, error); 449 450 clk = fdtbus_clock_get(psc->sc_phandle, "xusb_host_src"); 451 rate = clk_get_rate(clk); 452 error = clk_enable(clk); 453 DPRINTF(sc->sc_dev, "rate %u error %d\n", rate, error); 454 455 val = bus_space_read_4(bst, ipfsh, 0x0); 456 DPRINTF(sc->sc_dev, "%s ipfs 0x0 = 0x%x\n", __func__, val); 457 458 rst = fdtbus_reset_get(psc->sc_phandle, "xusb_host"); 459 fdtbus_reset_deassert(rst); 460 461 rst = fdtbus_reset_get(psc->sc_phandle, "xusb_src"); 462 fdtbus_reset_deassert(rst); 463 464 rst = fdtbus_reset_get(psc->sc_phandle, "xusb_ss"); 465 fdtbus_reset_deassert(rst); 466 467 val = csb_read_4(psc, XUSB_CSB_FALCON_CPUCTL_REG); 468 DPRINTF(sc->sc_dev, "XUSB_FALC_CPUCTL 0x%x\n", val); 469 470 val = bus_space_read_4(bst, psc->sc_bsh_fpci, PCI_USBREV) 471 & PCI_USBREV_MASK; 472 switch (val) { 473 case PCI_USBREV_3_0: 474 sc->sc_bus.ub_revision = USBREV_3_0; 475 break; 476 case PCI_USBREV_3_1: 477 sc->sc_bus.ub_revision = USBREV_3_1; 478 break; 479 default: 480 if (val < PCI_USBREV_3_0) { 481 aprint_error_dev(self, "Unknown revision (%02x)\n", val); 482 sc->sc_bus.ub_revision = USBREV_UNKNOWN; 483 } else { 484 /* Default to the latest revision */ 485 aprint_normal_dev(self, 486 "Unknown revision (%02x). Set to 3.1.\n", val); 487 sc->sc_bus.ub_revision = USBREV_3_1; 488 } 489 break; 490 } 491 492 error = xhci_init(sc); 493 if (error) { 494 aprint_error_dev(self, "init failed, error=%d\n", error); 495 return; 496 } 497 498 sc->sc_child = config_found(self, &sc->sc_bus, usbctlprint); 499 500 sc->sc_child2 = config_found(self, &sc->sc_bus2, usbctlprint); 501 502 xhci_start(sc); 503 504 error = xusb_mailbox_send(psc, 0x01000000); 505 if (error) { 506 aprint_error_dev(self, "send failed, error=%d\n", error); 507 } 508 } 509 510 static int 511 tegra_xusb_intr_mbox(void *v) 512 { 513 struct tegra_xusb_softc * const psc = v; 514 struct xhci_softc * const sc = &psc->sc_xhci; 515 const bus_space_tag_t bst = sc->sc_iot; 516 const bus_space_handle_t fpcih = psc->sc_bsh_fpci; 517 uint32_t val; 518 uint32_t irv; 519 uint32_t msg; 520 int error; 521 522 DPRINTF(sc->sc_dev, "%s()\n", __func__); 523 524 irv = bus_space_read_4(bst, fpcih, T_XUSB_CFG_ARU_SMI_INTR_REG); 525 DPRINTF(sc->sc_dev, "XUSB_CFG_ARU_SMI_INTR 0x%x\n", irv); 526 bus_space_write_4(bst, fpcih, T_XUSB_CFG_ARU_SMI_INTR_REG, irv); 527 528 if (irv & T_XUSB_CFG_ARU_SMI_INTR_FW_HANG) 529 aprint_error_dev(sc->sc_dev, "firmware hang\n"); 530 531 msg = bus_space_read_4(bst, fpcih, T_XUSB_CFG_ARU_MAILBOX_DATA_OUT_REG); 532 DPRINTF(sc->sc_dev, "XUSB_CFG_ARU_MBOX_DATA_OUT 0x%x\n", msg); 533 534 val = bus_space_read_4(bst, fpcih, T_XUSB_CFG_ARU_MAILBOX_CMD_REG); 535 DPRINTF(sc->sc_dev, "XUSB_CFG_ARU_MBOX_CMD 0x%x\n", val); 536 val &= ~T_XUSB_CFG_ARU_MAILBOX_CMD_DEST_SMI; 537 bus_space_write_4(bst, fpcih, T_XUSB_CFG_ARU_MAILBOX_CMD_REG, val); 538 539 bool sendresp = true; 540 u_int rate; 541 542 const uint32_t data = __SHIFTOUT(msg, MAILBOX_DATA_DATA); 543 const uint8_t type = __SHIFTOUT(msg, MAILBOX_DATA_TYPE); 544 545 switch (type) { 546 case 2: 547 case 3: 548 DPRINTF(sc->sc_dev, "FALC_CLOCK %u\n", data * 1000); 549 break; 550 case 4: 551 case 5: 552 if (psc->sc_txd->txd_scale_ss_clock) { 553 DPRINTF(sc->sc_dev, "SSPI_CLOCK %u\n", data * 1000); 554 rate = clk_get_rate(psc->sc_clk_ss_src); 555 DPRINTF(sc->sc_dev, "rate of psc->sc_clk_ss_src %u\n", 556 rate); 557 error = clk_set_rate(psc->sc_clk_ss_src, data * 1000); 558 if (error != 0) 559 goto clk_fail; 560 rate = clk_get_rate(psc->sc_clk_ss_src); 561 DPRINTF(sc->sc_dev, 562 "rate of psc->sc_clk_ss_src %u after\n", rate); 563 if (data == (rate / 1000)) { 564 msg = __SHIFTIN(128, MAILBOX_DATA_TYPE) | 565 __SHIFTIN(rate / 1000, MAILBOX_DATA_DATA); 566 } else 567 clk_fail: 568 msg = __SHIFTIN(129, MAILBOX_DATA_TYPE) | 569 __SHIFTIN(rate / 1000, MAILBOX_DATA_DATA); 570 } else { 571 msg = __SHIFTIN(128, MAILBOX_DATA_TYPE) | 572 __SHIFTIN(data, MAILBOX_DATA_DATA); 573 } 574 xusb_mailbox_send(psc, msg); 575 break; 576 case 9: 577 msg = __SHIFTIN(data, MAILBOX_DATA_DATA) | 578 __SHIFTIN(128, MAILBOX_DATA_TYPE); 579 xusb_mailbox_send(psc, msg); 580 break; 581 case 6: 582 case 128: 583 case 129: 584 sendresp = false; 585 break; 586 default: 587 sendresp = false; 588 break; 589 } 590 591 if (sendresp == false) 592 bus_space_write_4(bst, fpcih, T_XUSB_CFG_ARU_MAILBOX_OWNER_REG, 593 MAILBOX_OWNER_NONE); 594 595 return irv; 596 } 597 598 static void 599 tegra_xusb_init_regulators(struct tegra_xusb_softc * const psc) 600 { 601 602 device_t dev = psc->sc_xhci.sc_dev; 603 const int phandle = psc->sc_phandle; 604 struct fdtbus_regulator *reg; 605 int n, error; 606 607 for (n = 0; n < psc->sc_txd->txd_nsupplies; n++) { 608 if (!of_hasprop(phandle, psc->sc_txd->txd_supplies[n])) 609 continue; 610 reg = fdtbus_regulator_acquire(phandle, psc->sc_txd->txd_supplies[n]); 611 if (reg == NULL) { 612 aprint_error_dev(dev, "couldn't acquire supply '%s'\n", 613 psc->sc_txd->txd_supplies[n]); 614 continue; 615 } 616 error = fdtbus_regulator_enable(reg); 617 if (error != 0) 618 aprint_error_dev(dev, "couldn't enable supply '%s': %d\n", 619 psc->sc_txd->txd_supplies[n], error); 620 } 621 } 622 623 static void 624 tegra_xusb_init(struct tegra_xusb_softc * const psc) 625 { 626 struct xhci_softc * const sc = &psc->sc_xhci; 627 const bus_space_tag_t bst = sc->sc_iot; 628 const bus_space_handle_t ipfsh = psc->sc_bsh_ipfs; 629 const bus_space_handle_t fpcih = psc->sc_bsh_fpci; 630 631 DPRINTF(sc->sc_dev, "%s()\n", __func__); 632 633 DPRINTF(sc->sc_dev, "%s ipfs 0x0 = 0x%x\n", __func__, 634 bus_space_read_4(bst, ipfsh, 0x0)); 635 636 DPRINTF(sc->sc_dev, "%s ipfs 0x40 = 0x%x\n", __func__, 637 bus_space_read_4(bst, ipfsh, 0x40)); 638 639 DPRINTF(sc->sc_dev, "%s ipfs 0x80 = 0x%x\n", __func__, 640 bus_space_read_4(bst, ipfsh, 0x80)); 641 /* FPCI_BAR0_START and FPCI_BAR0_ACCESS_TYPE */ 642 bus_space_write_4(bst, ipfsh, 0x80, 0x00100000); 643 DPRINTF(sc->sc_dev, "%s ipfs 0x80 = 0x%x\n", __func__, 644 bus_space_read_4(bst, ipfsh, 0x80)); 645 646 DPRINTF(sc->sc_dev, "%s ipfs 0x180 = 0x%x\n", __func__, 647 bus_space_read_4(bst, ipfsh, 0x180)); 648 /* EN_FPCI */ 649 tegra_reg_set_clear(bst, ipfsh, 0x180, 1, 0); 650 DPRINTF(sc->sc_dev, "%s ipfs 0x180 = 0x%x\n", __func__, 651 bus_space_read_4(bst, ipfsh, 0x180)); 652 653 DPRINTF(sc->sc_dev, "%s fpci PCI_COMMAND_STATUS_REG = 0x%x\n", 654 __func__, bus_space_read_4(bst, fpcih, PCI_COMMAND_STATUS_REG)); 655 tegra_reg_set_clear(bst, fpcih, PCI_COMMAND_STATUS_REG, 656 PCI_COMMAND_MASTER_ENABLE|PCI_COMMAND_MEM_ENABLE, 0x0); 657 DPRINTF(sc->sc_dev, "%s fpci PCI_COMMAND_STATUS_REG = 0x%x\n", 658 __func__, bus_space_read_4(bst, fpcih, PCI_COMMAND_STATUS_REG)); 659 660 DPRINTF(sc->sc_dev, "%s fpci PCI_BAR0 = 0x%x\n", __func__, 661 bus_space_read_4(bst, fpcih, PCI_BAR0)); 662 /* match FPCI BAR0 to above */ 663 bus_space_write_4(bst, fpcih, PCI_BAR0, 0x10000000); 664 DPRINTF(sc->sc_dev, "%s fpci PCI_BAR0 = 0x%x\n", __func__, 665 bus_space_read_4(bst, fpcih, PCI_BAR0)); 666 667 DPRINTF(sc->sc_dev, "%s ipfs 0x188 = 0x%x\n", __func__, 668 bus_space_read_4(bst, ipfsh, 0x188)); 669 tegra_reg_set_clear(bst, ipfsh, 0x188, __BIT(16), 0); 670 DPRINTF(sc->sc_dev, "%s ipfs 0x188 = 0x%x\n", __func__, 671 bus_space_read_4(bst, ipfsh, 0x188)); 672 673 DPRINTF(sc->sc_dev, "%s fpci 0x1bc = 0x%x\n", __func__, 674 bus_space_read_4(bst, fpcih, 0x1bc)); 675 bus_space_write_4(bst, fpcih, 0x1bc, 0x80); 676 DPRINTF(sc->sc_dev, "%s fpci 0x1bc = 0x%x\n", __func__, 677 bus_space_read_4(bst, fpcih, 0x1bc)); 678 } 679 680 static int 681 fw_dma_alloc(struct tegra_xusb_softc * const psc, size_t size, size_t align, 682 struct fw_dma * const p) 683 { 684 struct xhci_softc * const sc = &psc->sc_xhci; 685 const bus_dma_tag_t dmat = sc->sc_bus.ub_dmatag; 686 int err; 687 688 p->size = size; 689 err = bus_dmamem_alloc(dmat, p->size, align, 0, p->segs, 690 sizeof(p->segs) / sizeof(p->segs[0]), &p->nsegs, BUS_DMA_NOWAIT); 691 if (err) 692 return err; 693 err = bus_dmamem_map(dmat, p->segs, p->nsegs, p->size, &p->addr, 694 BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 695 if (err) 696 goto free; 697 err = bus_dmamap_create(dmat, p->size, 1, p->size, 0, BUS_DMA_NOWAIT, 698 &p->map); 699 if (err) 700 goto unmap; 701 err = bus_dmamap_load(dmat, p->map, p->addr, p->size, NULL, 702 BUS_DMA_NOWAIT); 703 if (err) 704 goto destroy; 705 706 return 0; 707 708 destroy: 709 bus_dmamap_destroy(dmat, p->map); 710 unmap: 711 bus_dmamem_unmap(dmat, p->addr, p->size); 712 free: 713 bus_dmamem_free(dmat, p->segs, p->nsegs); 714 715 return err; 716 } 717 718 static void 719 fw_dma_free(struct tegra_xusb_softc * const psc, struct fw_dma * const p) 720 { 721 const struct xhci_softc * const sc = &psc->sc_xhci; 722 const bus_dma_tag_t dmat = sc->sc_bus.ub_dmatag; 723 724 bus_dmamap_unload(dmat, p->map); 725 bus_dmamap_destroy(dmat, p->map); 726 bus_dmamem_unmap(dmat, p->addr, p->size); 727 bus_dmamem_free(dmat, p->segs, p->nsegs); 728 } 729 730 #define FWHEADER_BOOT_CODETAG 8 731 #define FWHEADER_BOOT_CODESIZE 12 732 #define FWHEADER_FWIMG_LEN 100 733 #define FWHEADER__LEN 256 734 735 static int 736 tegra_xusb_open_fw(struct tegra_xusb_softc * const psc) 737 { 738 struct xhci_softc * const sc = &psc->sc_xhci; 739 firmware_handle_t fw; 740 size_t firmware_size = 0; 741 void *firmware_image; 742 const char *fw_path = NULL; 743 void *fw_static = NULL; 744 int error; 745 746 switch (psc->sc_txd->txd_type) { 747 case XUSB_T124: 748 #if defined(TEGRA124_XUSB_BIN_STATIC) 749 firmware_size = (uintptr_t)&_binary_tegra124_xusb_bin_end 750 - (uintptr_t)&_binary_tegra124_xusb_bin_start; 751 fw_static = __UNCONST(_binary_tegra124_xusb_bin_start); 752 #else 753 fw_path = "nvidia/tegra124"; 754 #endif 755 break; 756 case XUSB_T210: 757 #if defined(TEGRA210_XUSB_BIN_STATIC) 758 firmware_size = (uintptr_t)&_binary_tegra210_xusb_bin_end 759 - (uintptr_t)&_binary_tegra210_xusb_bin_start; 760 fw_static = __UNCONST(_binary_tegra210_xusb_bin_start); 761 #else 762 fw_path = "nvidia/tegra210"; 763 #endif 764 break; 765 default: 766 return EINVAL; 767 } 768 769 if (fw_path != NULL) { 770 error = firmware_open(fw_path, "xusb.bin", &fw); 771 if (error != 0) { 772 aprint_error_dev(sc->sc_dev, 773 "couldn't load firmware from %s/xusb.bin: %d\n", 774 fw_path, error); 775 return error; 776 } 777 firmware_size = firmware_get_size(fw); 778 } 779 780 error = fw_dma_alloc(psc, firmware_size, PAGE_SIZE, 781 &psc->sc_fw_dma); 782 if (error != 0) 783 return error; 784 firmware_image = psc->sc_fw_dma.addr; 785 786 if (fw_path != NULL) { 787 error = firmware_read(fw, 0, firmware_image, firmware_size); 788 if (error != 0) { 789 fw_dma_free(psc, &psc->sc_fw_dma); 790 firmware_close(fw); 791 return error; 792 } 793 firmware_close(fw); 794 } else { 795 memcpy(firmware_image, fw_static, firmware_size); 796 } 797 798 return tegra_xusb_load_fw(psc, firmware_image, firmware_size); 799 } 800 801 static int 802 tegra_xusb_load_fw(struct tegra_xusb_softc * const psc, void *firmware_image, 803 size_t firmware_size) 804 { 805 struct xhci_softc * const sc = &psc->sc_xhci; 806 const uint8_t *header; 807 808 header = firmware_image; 809 810 const uint32_t fwimg_len = le32dec(&header[FWHEADER_FWIMG_LEN]); 811 const uint32_t boot_codetag = le32dec(&header[FWHEADER_BOOT_CODETAG]); 812 const uint32_t boot_codesize = le32dec(&header[FWHEADER_BOOT_CODESIZE]); 813 814 if (fwimg_len != firmware_size) 815 aprint_error_dev(sc->sc_dev, "fwimg_len mismatch %u != %zu\n", 816 fwimg_len, firmware_size); 817 818 bus_dmamap_sync(sc->sc_bus.ub_dmatag, psc->sc_fw_dma.map, 0, 819 firmware_size, BUS_DMASYNC_PREWRITE); 820 821 DPRINTF(sc->sc_dev, "XUSB_FALC_CPUCTL 0x%x\n", 822 csb_read_4(psc, XUSB_CSB_FALCON_CPUCTL_REG)); 823 DPRINTF(sc->sc_dev, "XUSB_CSB_MP_ILOAD_BASE_LO 0x%x\n", 824 csb_read_4(psc, XUSB_CSB_MEMPOOL_ILOAD_BASE_LO_REG)); 825 826 DPRINTF(sc->sc_dev, "XUSB_CSB_MP_ILOAD_ATTR 0x%x\n", 827 csb_read_4(psc, XUSB_CSB_MEMPOOL_ILOAD_ATTR_REG)); 828 csb_write_4(psc, XUSB_CSB_MEMPOOL_ILOAD_ATTR_REG, 829 fwimg_len); 830 DPRINTF(sc->sc_dev, "XUSB_CSB_MP_ILOAD_ATTR 0x%x\n", 831 csb_read_4(psc, XUSB_CSB_MEMPOOL_ILOAD_ATTR_REG)); 832 833 const uint64_t fwbase = psc->sc_fw_dma.map->dm_segs[0].ds_addr + 834 FWHEADER__LEN; 835 836 csb_write_4(psc, XUSB_CSB_MEMPOOL_ILOAD_BASE_HI_REG, fwbase >> 32); 837 csb_write_4(psc, XUSB_CSB_MEMPOOL_ILOAD_BASE_LO_REG, fwbase); 838 DPRINTF(sc->sc_dev, "XUSB_CSB_MP_ILOAD_BASE_LO 0x%x\n", 839 csb_read_4(psc, XUSB_CSB_MEMPOOL_ILOAD_BASE_LO_REG)); 840 DPRINTF(sc->sc_dev, "XUSB_CSB_MP_ILOAD_BASE_HI 0x%x\n", 841 csb_read_4(psc, XUSB_CSB_MEMPOOL_ILOAD_BASE_HI_REG)); 842 843 DPRINTF(sc->sc_dev, "XUSB_CSB_MP_APMAP 0x%x\n", 844 csb_read_4(psc, XUSB_CSB_MEMPOOL_APMAP_REG)); 845 csb_write_4(psc, XUSB_CSB_MEMPOOL_APMAP_REG, 846 XUSB_CSB_MEMPOOL_APMAP_BOOTPATH); 847 DPRINTF(sc->sc_dev, "XUSB_CSB_MP_APMAP 0x%x\n", 848 csb_read_4(psc, XUSB_CSB_MEMPOOL_APMAP_REG)); 849 850 DPRINTF(sc->sc_dev, "XUSB_CSB_MP_L2IMEMOP_TRIG 0x%x\n", 851 csb_read_4(psc, XUSB_CSB_MEMPOOL_L2IMEMOP_TRIG_REG)); 852 csb_write_4(psc, XUSB_CSB_MEMPOOL_L2IMEMOP_TRIG_REG, 853 __SHIFTIN(ACTION_L2IMEM_INVALIDATE_ALL, 854 XUSB_CSB_MEMPOOL_L2IMEMOP_TRIG_ACTION)); 855 DPRINTF(sc->sc_dev, "XUSB_CSB_MP_L2IMEMOP_TRIG 0x%x\n", 856 csb_read_4(psc, XUSB_CSB_MEMPOOL_L2IMEMOP_TRIG_REG)); 857 858 const u_int code_tag_blocks = 859 howmany(boot_codetag, IMEM_BLOCK_SIZE); 860 const u_int code_size_blocks = 861 howmany(boot_codesize, IMEM_BLOCK_SIZE); 862 const u_int code_blocks = code_tag_blocks + code_size_blocks; 863 864 DPRINTF(sc->sc_dev, "XUSB_CSB_MP_L2IMEMOP_SIZE 0x%x\n", 865 csb_read_4(psc, XUSB_CSB_MEMPOOL_L2IMEMOP_SIZE_REG)); 866 csb_write_4(psc, XUSB_CSB_MEMPOOL_L2IMEMOP_SIZE_REG, 867 __SHIFTIN(code_tag_blocks, 868 XUSB_CSB_MEMPOOL_L2IMEMOP_SIZE_SRC_OFFSET) | 869 __SHIFTIN(code_size_blocks, 870 XUSB_CSB_MEMPOOL_L2IMEMOP_SIZE_SRC_COUNT)); 871 DPRINTF(sc->sc_dev, "XUSB_CSB_MP_L2IMEMOP_SIZE 0x%x\n", 872 csb_read_4(psc, XUSB_CSB_MEMPOOL_L2IMEMOP_SIZE_REG)); 873 874 DPRINTF(sc->sc_dev, "XUSB_CSB_MP_L2IMEMOP_TRIG 0x%x\n", 875 csb_read_4(psc, XUSB_CSB_MEMPOOL_L2IMEMOP_TRIG_REG)); 876 csb_write_4(psc, XUSB_CSB_MEMPOOL_L2IMEMOP_TRIG_REG, 877 __SHIFTIN(ACTION_L2IMEM_LOAD_LOCKED_RESULT, 878 XUSB_CSB_MEMPOOL_L2IMEMOP_TRIG_ACTION)); 879 DPRINTF(sc->sc_dev, "XUSB_CSB_MP_L2IMEMOP_TRIG 0x%x\n", 880 csb_read_4(psc, XUSB_CSB_MEMPOOL_L2IMEMOP_TRIG_REG)); 881 882 DPRINTF(sc->sc_dev, "XUSB_FALC_IMFILLCTL 0x%x\n", 883 csb_read_4(psc, XUSB_CSB_FALCON_IMFILLCTL_REG)); 884 csb_write_4(psc, XUSB_CSB_FALCON_IMFILLCTL_REG, code_size_blocks); 885 DPRINTF(sc->sc_dev, "XUSB_FALC_IMFILLCTL 0x%x\n", 886 csb_read_4(psc, XUSB_CSB_FALCON_IMFILLCTL_REG)); 887 888 DPRINTF(sc->sc_dev, "XUSB_FALC_IMFILLRNG1 0x%x\n", 889 csb_read_4(psc, XUSB_CSB_FALCON_IMFILLRNG1_REG)); 890 csb_write_4(psc, XUSB_CSB_FALCON_IMFILLRNG1_REG, 891 __SHIFTIN(code_tag_blocks, XUSB_CSB_FALCON_IMFILLRNG1_TAG_LO) | 892 __SHIFTIN(code_blocks, XUSB_CSB_FALCON_IMFILLRNG1_TAG_HI)); 893 DPRINTF(sc->sc_dev, "XUSB_FALC_IMFILLRNG1 0x%x\n", 894 csb_read_4(psc, XUSB_CSB_FALCON_IMFILLRNG1_REG)); 895 896 DPRINTF(sc->sc_dev, "XUSB_FALC_DMACTL 0x%x\n", 897 csb_read_4(psc, XUSB_CSB_FALCON_DMACTL_REG)); 898 csb_write_4(psc, XUSB_CSB_FALCON_DMACTL_REG, 0); 899 DPRINTF(sc->sc_dev, "XUSB_FALC_DMACTL 0x%x\n", 900 csb_read_4(psc, XUSB_CSB_FALCON_DMACTL_REG)); 901 902 DPRINTF(sc->sc_dev, "XUSB_FALC_BOOTVEC 0x%x\n", 903 csb_read_4(psc, XUSB_CSB_FALCON_BOOTVEC_REG)); 904 csb_write_4(psc, XUSB_CSB_FALCON_BOOTVEC_REG, 905 boot_codetag); 906 DPRINTF(sc->sc_dev, "XUSB_FALC_BOOTVEC 0x%x\n", 907 csb_read_4(psc, XUSB_CSB_FALCON_BOOTVEC_REG)); 908 909 DPRINTF(sc->sc_dev, "XUSB_FALC_CPUCTL 0x%x\n", 910 csb_read_4(psc, XUSB_CSB_FALCON_CPUCTL_REG)); 911 csb_write_4(psc, XUSB_CSB_FALCON_CPUCTL_REG, 912 XUSB_CSB_FALCON_CPUCTL_STARTCPU); 913 DPRINTF(sc->sc_dev, "XUSB_FALC_CPUCTL 0x%x\n", 914 csb_read_4(psc, XUSB_CSB_FALCON_CPUCTL_REG)); 915 916 return 0; 917 } 918 919 static uint32_t 920 csb_read_4(struct tegra_xusb_softc * const psc, bus_size_t csb_offset) 921 { 922 const uint32_t range = __SHIFTOUT(csb_offset, XUSB_CSB_RANGE); 923 const bus_size_t offset = __SHIFTOUT(csb_offset, XUSB_CSB_OFFSET); 924 const bus_space_tag_t bst = psc->sc_xhci.sc_iot; 925 const bus_space_handle_t fpcih = psc->sc_bsh_fpci; 926 927 bus_space_write_4(bst, fpcih, T_XUSB_CFG_ARU_C11_CSBRANGE_REG, range); 928 return bus_space_read_4(bst, fpcih, T_XUSB_CFG_CSB_BASE_ADDR + offset); 929 } 930 931 static void 932 csb_write_4(struct tegra_xusb_softc * const psc, bus_size_t csb_offset, 933 uint32_t value) 934 { 935 const uint32_t range = __SHIFTOUT(csb_offset, XUSB_CSB_RANGE); 936 const bus_size_t offset = __SHIFTOUT(csb_offset, XUSB_CSB_OFFSET); 937 const bus_space_tag_t bst = psc->sc_xhci.sc_iot; 938 const bus_space_handle_t fpcih = psc->sc_bsh_fpci; 939 940 bus_space_write_4(bst, fpcih, T_XUSB_CFG_ARU_C11_CSBRANGE_REG, range); 941 bus_space_write_4(bst, fpcih, T_XUSB_CFG_CSB_BASE_ADDR + offset, value); 942 } 943 944 static int 945 xusb_mailbox_send(struct tegra_xusb_softc * const psc, uint32_t msg) 946 { 947 struct xhci_softc * const sc = &psc->sc_xhci; 948 const bus_space_tag_t bst = psc->sc_xhci.sc_iot; 949 const bus_space_handle_t fpcih = psc->sc_bsh_fpci; 950 uint32_t val; 951 bool wait = false; 952 953 const uint8_t type = __SHIFTOUT(msg, MAILBOX_DATA_TYPE); 954 955 if (!(type == 128 || type == 129)) { 956 val = bus_space_read_4(bst, fpcih, 957 T_XUSB_CFG_ARU_MAILBOX_OWNER_REG); 958 DPRINTF(sc->sc_dev, "XUSB_CFG_ARU_MBOX_OWNER 0x%x\n", 959 val); 960 if (val != MAILBOX_OWNER_NONE) { 961 return EBUSY; 962 } 963 964 bus_space_write_4(bst, fpcih, T_XUSB_CFG_ARU_MAILBOX_OWNER_REG, 965 MAILBOX_OWNER_SW); 966 967 val = bus_space_read_4(bst, fpcih, 968 T_XUSB_CFG_ARU_MAILBOX_OWNER_REG); 969 DPRINTF(sc->sc_dev, "XUSB_CFG_ARU_MBOX_OWNER 0x%x\n", 970 val); 971 if (val != MAILBOX_OWNER_SW) { 972 return EBUSY; 973 } 974 975 wait = true; 976 } 977 978 bus_space_write_4(bst, fpcih, T_XUSB_CFG_ARU_MAILBOX_DATA_IN_REG, msg); 979 980 tegra_reg_set_clear(bst, fpcih, T_XUSB_CFG_ARU_MAILBOX_CMD_REG, 981 T_XUSB_CFG_ARU_MAILBOX_CMD_INT_EN | 982 T_XUSB_CFG_ARU_MAILBOX_CMD_DEST_FALCON, 0); 983 984 if (wait) { 985 986 for (u_int i = 0; i < 2500; i++) { 987 val = bus_space_read_4(bst, fpcih, 988 T_XUSB_CFG_ARU_MAILBOX_OWNER_REG); 989 DPRINTF(sc->sc_dev, 990 "XUSB_CFG_ARU_MBOX_OWNER 0x%x\n", val); 991 if (val == MAILBOX_OWNER_NONE) { 992 break; 993 } 994 DELAY(10); 995 } 996 997 val = bus_space_read_4(bst, fpcih, 998 T_XUSB_CFG_ARU_MAILBOX_OWNER_REG); 999 DPRINTF(sc->sc_dev, 1000 "XUSB_CFG_ARU_MBOX_OWNER 0x%x\n", val); 1001 if (val != MAILBOX_OWNER_NONE) { 1002 aprint_error_dev(sc->sc_dev, 1003 "timeout, XUSB_CFG_ARU_MBOX_OWNER 0x%x\n", val); 1004 } 1005 } 1006 1007 return 0; 1008 } 1009
Indexes created Thu Sep 25 16:09:42 GMT 2025