tegra_xusb.c revision 1.3
1 /* $NetBSD: tegra_xusb.c,v 1.3 2017/02/27 12:38:00 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 2016 Jonathan A. Kollasch 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR 20 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 21 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 22 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 23 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 25 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 26 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include "locators.h" 30 #include "opt_tegra.h" 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: tegra_xusb.c,v 1.3 2017/02/27 12:38:00 skrll Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/bus.h> 37 #include <sys/device.h> 38 #include <sys/intr.h> 39 #include <sys/systm.h> 40 #include <sys/kernel.h> 41 42 #include <arm/nvidia/tegra_reg.h> 43 #include <arm/nvidia/tegra_var.h> 44 45 #include <arm/nvidia/tegra_xusbreg.h> 46 #include <dev/pci/pcireg.h> 47 48 #include <dev/fdt/fdtvar.h> 49 50 #include <dev/firmload.h> 51 52 #include <dev/usb/usb.h> 53 #include <dev/usb/usbdi.h> 54 #include <dev/usb/usbdivar.h> 55 #include <dev/usb/usb_mem.h> 56 57 #include <dev/usb/xhcireg.h> 58 #include <dev/usb/xhcivar.h> 59 60 static int tegra_xusb_match(device_t, cfdata_t, void *); 61 static void tegra_xusb_attach(device_t, device_t, void *); 62 static void tegra_xusb_mountroot(device_t); 63 64 static int tegra_xusb_intr_mbox(void *); 65 66 #ifdef TEGRA124_XUSB_BIN_STATIC 67 extern const char _binary_tegra124_xusb_bin_size[]; 68 extern const char _binary_tegra124_xusb_bin_start[]; 69 #endif 70 71 struct fw_dma { 72 bus_dmamap_t map; 73 void * addr; 74 bus_dma_segment_t segs[1]; 75 int nsegs; 76 size_t size; 77 }; 78 79 struct tegra_xusb_softc { 80 struct xhci_softc sc_xhci; 81 int sc_phandle; 82 bus_space_handle_t sc_bsh_xhci; 83 bus_space_handle_t sc_bsh_fpci; 84 bus_space_handle_t sc_bsh_ipfs; 85 void *sc_ih; 86 void *sc_ih_mbox; 87 struct fw_dma sc_fw_dma; 88 struct clk *sc_clk_ss_src; 89 }; 90 91 static uint32_t csb_read_4(struct tegra_xusb_softc * const, bus_size_t); 92 static void csb_write_4(struct tegra_xusb_softc * const, bus_size_t, 93 uint32_t); 94 95 static void tegra_xusb_init(struct tegra_xusb_softc * const); 96 static void tegra_xusb_load_fw(struct tegra_xusb_softc * const); 97 98 static int xusb_mailbox_send(struct tegra_xusb_softc * const, uint32_t); 99 100 CFATTACH_DECL_NEW(tegra_xusb, sizeof(struct tegra_xusb_softc), 101 tegra_xusb_match, tegra_xusb_attach, NULL, NULL); 102 103 static int 104 tegra_xusb_match(device_t parent, cfdata_t cf, void *aux) 105 { 106 const char * const compatible[] = { "nvidia,tegra124-xusb", NULL }; 107 struct fdt_attach_args * const faa = aux; 108 109 return of_match_compatible(faa->faa_phandle, compatible); 110 } 111 112 #define tegra_xusb_attach_check(sc, cond, fmt, ...) \ 113 do { \ 114 if (cond) { \ 115 aprint_error_dev(sc->sc_dev, fmt, ## __VA_ARGS__); \ 116 return; \ 117 } \ 118 } while (0) 119 120 static void 121 tegra_xusb_attach(device_t parent, device_t self, void *aux) 122 { 123 struct tegra_xusb_softc * const psc = device_private(self); 124 struct xhci_softc * const sc = &psc->sc_xhci; 125 struct fdt_attach_args * const faa = aux; 126 char intrstr[128]; 127 bus_addr_t addr; 128 bus_size_t size; 129 int error; 130 struct clk *clk; 131 uint32_t rate; 132 struct fdtbus_reset *rst; 133 134 aprint_naive("\n"); 135 aprint_normal(": XUSB\n"); 136 137 sc->sc_dev = self; 138 sc->sc_iot = faa->faa_bst; 139 sc->sc_bus.ub_hcpriv = sc; 140 sc->sc_bus.ub_dmatag = faa->faa_dmat; 141 psc->sc_phandle = faa->faa_phandle; 142 143 if (fdtbus_get_reg(faa->faa_phandle, 0, &addr, &size) != 0) { 144 aprint_error(": couldn't get registers\n"); 145 return; 146 } 147 error = bus_space_map(sc->sc_iot, addr, size, 0, &sc->sc_ioh); 148 if (error) { 149 aprint_error(": couldn't map %#llx: %d", (uint64_t)addr, error); 150 return; 151 } 152 printf("mapped %#llx\n", (uint64_t)addr); 153 154 if (fdtbus_get_reg(faa->faa_phandle, 1, &addr, &size) != 0) { 155 aprint_error(": couldn't get registers\n"); 156 return; 157 } 158 error = bus_space_map(sc->sc_iot, addr, size, 0, &psc->sc_bsh_fpci); 159 if (error) { 160 aprint_error(": couldn't map %#llx: %d", (uint64_t)addr, error); 161 return; 162 } 163 printf("mapped %#llx\n", (uint64_t)addr); 164 165 if (fdtbus_get_reg(faa->faa_phandle, 2, &addr, &size) != 0) { 166 aprint_error(": couldn't get registers\n"); 167 return; 168 } 169 error = bus_space_map(sc->sc_iot, addr, size, 0, &psc->sc_bsh_ipfs); 170 if (error) { 171 aprint_error(": couldn't map %#llx: %d", (uint64_t)addr, error); 172 return; 173 } 174 printf("mapped %#llx\n", (uint64_t)addr); 175 176 if (!fdtbus_intr_str(faa->faa_phandle, 0, intrstr, sizeof(intrstr))) { 177 aprint_error_dev(self, "failed to decode interrupt\n"); 178 return; 179 } 180 181 psc->sc_ih = fdtbus_intr_establish(faa->faa_phandle, 0, IPL_USB, 182 0, xhci_intr, sc); 183 if (psc->sc_ih == NULL) { 184 aprint_error_dev(self, "failed to establish interrupt on %s\n", 185 intrstr); 186 return; 187 } 188 aprint_normal_dev(self, "interrupting on %s\n", intrstr); 189 190 if (!fdtbus_intr_str(faa->faa_phandle, 1, intrstr, sizeof(intrstr))) { 191 aprint_error_dev(self, "failed to decode interrupt\n"); 192 return; 193 } 194 195 psc->sc_ih_mbox = fdtbus_intr_establish(faa->faa_phandle, 1, IPL_VM, 196 0, tegra_xusb_intr_mbox, psc); 197 if (psc->sc_ih_mbox == NULL) { 198 aprint_error_dev(self, "failed to establish interrupt on %s\n", 199 intrstr); 200 return; 201 } 202 aprint_normal_dev(self, "interrupting on %s\n", intrstr); 203 204 struct clk * const pll_p_out0 = clk_get("pll_p_out0"); 205 KASSERT(pll_p_out0 != NULL); 206 207 struct clk * const pll_u_48 = clk_get("pll_u_48"); 208 KASSERT(pll_u_48 != NULL); 209 210 struct clk * const pll_u_480 = clk_get("pll_u_480"); 211 KASSERT(pll_u_480 != NULL); 212 213 clk = fdtbus_clock_get(faa->faa_phandle, "pll_e"); 214 rate = clk_get_rate(clk); 215 error = clk_enable(clk); /* XXX set frequency */ 216 device_printf(sc->sc_dev, "rate %u error %d\n", rate, error); 217 tegra_xusb_attach_check(sc, error, "failed to enable pll_e clock"); 218 219 clk = fdtbus_clock_get(faa->faa_phandle, "xusb_host_src"); 220 error = clk_set_parent(clk, pll_p_out0); 221 tegra_xusb_attach_check(sc, error, "failed to set xusb_host_src clock parent"); 222 223 rate = clk_get_rate(clk); 224 device_printf(sc->sc_dev, "rate %u error %d\n", rate, error); 225 error = clk_set_rate(clk, 102000000); 226 tegra_xusb_attach_check(sc, error, "failed to set xusb_host_src clock rate"); 227 228 rate = clk_get_rate(clk); 229 error = clk_enable(clk); /* XXX set frequency */ 230 device_printf(sc->sc_dev, "rate %u error %d\n", rate, error); 231 tegra_xusb_attach_check(sc, error, "failed to enable xusb_host_src clock"); 232 233 clk = fdtbus_clock_get(faa->faa_phandle, "xusb_falcon_src"); 234 error = clk_set_parent(clk, pll_p_out0); 235 tegra_xusb_attach_check(sc, error, "failed to set xusb_falcon_src clock parent"); 236 237 rate = clk_get_rate(clk); 238 device_printf(sc->sc_dev, "rate %u error %d\n", rate, error); 239 error = clk_set_rate(clk, 204000000); 240 tegra_xusb_attach_check(sc, error, "failed to set xusb_falcon_src clock rate"); 241 242 rate = clk_get_rate(clk); 243 error = clk_enable(clk); 244 device_printf(sc->sc_dev, "rate %u error %d\n", rate, error); 245 tegra_xusb_attach_check(sc, error, "failed to enable xusb_falcon_src clock"); 246 247 clk = fdtbus_clock_get(faa->faa_phandle, "xusb_host"); 248 rate = clk_get_rate(clk); 249 error = clk_enable(clk); /* XXX set frequency */ 250 device_printf(sc->sc_dev, "rate %u error %d\n", rate, error); 251 252 clk = fdtbus_clock_get(faa->faa_phandle, "xusb_ss"); 253 rate = clk_get_rate(clk); 254 error = clk_enable(clk); /* XXX set frequency */ 255 device_printf(sc->sc_dev, "xusb_ss rate %u error %d\n", rate, error); 256 tegra_xusb_attach_check(sc, error, "failed to enable xusb_ss clock"); 257 258 psc->sc_clk_ss_src = fdtbus_clock_get(faa->faa_phandle, "xusb_ss_src"); 259 tegra_xusb_attach_check(sc, psc->sc_clk_ss_src == NULL, 260 "failed to get xusb_ss_src clock"); 261 rate = clk_get_rate(psc->sc_clk_ss_src); 262 device_printf(sc->sc_dev, "xusb_ss_src rate %u\n", rate); 263 264 error = clk_set_rate(psc->sc_clk_ss_src, 2000000); 265 rate = clk_get_rate(psc->sc_clk_ss_src); 266 device_printf(sc->sc_dev, "xusb_ss_src rate %u error %d\n", rate, 267 error); 268 tegra_xusb_attach_check(sc, error, "failed to get xusb_ss_src clock rate"); 269 270 error = clk_set_parent(psc->sc_clk_ss_src, pll_u_480); 271 tegra_xusb_attach_check(sc, error, "failed to set xusb_ss_src clock parent"); 272 273 rate = clk_get_rate(psc->sc_clk_ss_src); 274 device_printf(sc->sc_dev, "ss_src rate %u\n", rate); 275 tegra_xusb_attach_check(sc, error, "failed to set xusb_ss_src clock rate"); 276 277 error = clk_set_rate(psc->sc_clk_ss_src, 120000000); 278 rate = clk_get_rate(psc->sc_clk_ss_src); 279 device_printf(sc->sc_dev, "ss_src rate %u error %d\n", rate, error); 280 tegra_xusb_attach_check(sc, error, "failed to get xusb_ss_src clock rate"); 281 282 error = clk_enable(psc->sc_clk_ss_src); 283 device_printf(sc->sc_dev, "ss_src rate %u error %d\n", rate, error); 284 tegra_xusb_attach_check(sc, error, "failed to enable xusb_ss_src clock"); 285 286 #if 0 287 clk = fdtbus_clock_get(faa->faa_phandle, "xusb_hs_src"); 288 error = 0; 289 rate = clk_get_rate(clk); 290 device_printf(sc->sc_dev, "rate %u error %d\n", rate, error); 291 #endif 292 293 clk = fdtbus_clock_get(faa->faa_phandle, "xusb_fs_src"); 294 error = clk_set_parent(clk, pll_u_48); 295 tegra_xusb_attach_check(sc, error, "failed to set xusb_fs_src clock parent"); 296 297 rate = clk_get_rate(clk); 298 error = clk_enable(clk); /* XXX set frequency */ 299 device_printf(sc->sc_dev, "rate %u error %d\n", rate, error); 300 tegra_xusb_attach_check(sc, error, "failed to enable xusb_fs_src clock"); 301 302 rst = fdtbus_reset_get(faa->faa_phandle, "xusb_host"); 303 fdtbus_reset_deassert(rst); 304 305 rst = fdtbus_reset_get(faa->faa_phandle, "xusb_src"); 306 fdtbus_reset_deassert(rst); 307 308 rst = fdtbus_reset_get(faa->faa_phandle, "xusb_ss"); 309 fdtbus_reset_deassert(rst); 310 311 DELAY(1); 312 313 tegra_xusb_init(psc); 314 315 #if defined(TEGRA124_XUSB_BIN_STATIC) 316 tegra_xusb_mountroot(sc->sc_dev); 317 #else 318 config_mountroot(sc->sc_dev, tegra_xusb_mountroot); 319 #endif 320 } 321 322 static void 323 tegra_xusb_mountroot(device_t self) 324 { 325 struct tegra_xusb_softc * const psc = device_private(self); 326 struct xhci_softc * const sc = &psc->sc_xhci; 327 const bus_space_tag_t bst = sc->sc_iot; 328 const bus_space_handle_t ipfsh = psc->sc_bsh_ipfs; 329 struct clk *clk; 330 struct fdtbus_reset *rst; 331 uint32_t rate; 332 uint32_t val; 333 int error; 334 335 device_printf(sc->sc_dev, "%s()\n", __func__); 336 337 val = bus_space_read_4(bst, ipfsh, 0x0); 338 device_printf(sc->sc_dev, "%s ipfs 0x0 = 0x%x\n", __func__, val); 339 340 tegra_xusb_load_fw(psc); 341 device_printf(sc->sc_dev, "post fw\n"); 342 343 clk = fdtbus_clock_get(psc->sc_phandle, "xusb_falcon_src"); 344 rate = clk_get_rate(clk); 345 error = clk_enable(clk); 346 device_printf(sc->sc_dev, "rate %u error %d\n", rate, error); 347 348 clk = fdtbus_clock_get(psc->sc_phandle, "xusb_host_src"); 349 rate = clk_get_rate(clk); 350 error = clk_enable(clk); 351 device_printf(sc->sc_dev, "rate %u error %d\n", rate, error); 352 353 val = bus_space_read_4(bst, ipfsh, 0x0); 354 device_printf(sc->sc_dev, "%s ipfs 0x0 = 0x%x\n", __func__, val); 355 356 rst = fdtbus_reset_get(psc->sc_phandle, "xusb_host"); 357 fdtbus_reset_deassert(rst); 358 359 rst = fdtbus_reset_get(psc->sc_phandle, "xusb_src"); 360 fdtbus_reset_deassert(rst); 361 362 rst = fdtbus_reset_get(psc->sc_phandle, "xusb_ss"); 363 fdtbus_reset_deassert(rst); 364 365 val = csb_read_4(psc, XUSB_CSB_FALCON_CPUCTL_REG); 366 device_printf(sc->sc_dev, "XUSB_FALC_CPUCTL 0x%x\n", val); 367 368 369 error = xhci_init(sc); 370 if (error) { 371 aprint_error_dev(self, "init failed, error=%d\n", error); 372 return; 373 } 374 375 sc->sc_child = config_found(self, &sc->sc_bus, usbctlprint); 376 377 sc->sc_child2 = config_found(self, &sc->sc_bus2, usbctlprint); 378 379 error = xusb_mailbox_send(psc, 0x01000000); 380 if (error) { 381 aprint_error_dev(self, "send failed, error=%d\n", error); 382 } 383 } 384 385 static int 386 tegra_xusb_intr_mbox(void *v) 387 { 388 struct tegra_xusb_softc * const psc = v; 389 struct xhci_softc * const sc = &psc->sc_xhci; 390 const bus_space_tag_t bst = sc->sc_iot; 391 const bus_space_handle_t fpcih = psc->sc_bsh_fpci; 392 uint32_t val; 393 uint32_t irv; 394 uint32_t msg; 395 int error; 396 397 device_printf(sc->sc_dev, "%s()\n", __func__); 398 399 irv = bus_space_read_4(bst, fpcih, T_XUSB_CFG_ARU_SMI_INTR_REG); 400 device_printf(sc->sc_dev, "XUSB_CFG_ARU_SMI_INTR 0x%x\n", irv); 401 bus_space_write_4(bst, fpcih, T_XUSB_CFG_ARU_SMI_INTR_REG, irv); 402 403 if (irv & T_XUSB_CFG_ARU_SMI_INTR_FW_HANG) 404 device_printf(sc->sc_dev, "firmware hang\n"); 405 406 msg = bus_space_read_4(bst, fpcih, T_XUSB_CFG_ARU_MAILBOX_DATA_OUT_REG); 407 device_printf(sc->sc_dev, "XUSB_CFG_ARU_MBOX_DATA_OUT 0x%x\n", msg); 408 409 val = bus_space_read_4(bst, fpcih, T_XUSB_CFG_ARU_MAILBOX_CMD_REG); 410 device_printf(sc->sc_dev, "XUSB_CFG_ARU_MBOX_CMD 0x%x\n", val); 411 val &= ~T_XUSB_CFG_ARU_MAILBOX_CMD_DEST_SMI; 412 bus_space_write_4(bst, fpcih, T_XUSB_CFG_ARU_MAILBOX_CMD_REG, val); 413 414 bool sendresp = true; 415 u_int rate; 416 417 const uint32_t data = __SHIFTOUT(msg, MAILBOX_DATA_DATA); 418 const uint8_t type = __SHIFTOUT(msg, MAILBOX_DATA_TYPE); 419 420 switch (type) { 421 case 2: 422 case 3: 423 device_printf(sc->sc_dev, "FALC_CLOCK %u\n", data * 1000); 424 break; 425 case 4: 426 case 5: 427 device_printf(sc->sc_dev, "SSPI_CLOCK %u\n", data * 1000); 428 rate = clk_get_rate(psc->sc_clk_ss_src); 429 device_printf(sc->sc_dev, "rate of psc->sc_clk_ss_src %u\n", 430 rate); 431 error = clk_set_rate(psc->sc_clk_ss_src, data * 1000); 432 if (error != 0) 433 goto clk_fail; 434 rate = clk_get_rate(psc->sc_clk_ss_src); 435 device_printf(sc->sc_dev, 436 "rate of psc->sc_clk_ss_src %u after\n", rate); 437 if (data == (rate / 1000)) { 438 msg = __SHIFTIN(128, MAILBOX_DATA_TYPE) | 439 __SHIFTIN(rate / 1000, MAILBOX_DATA_DATA); 440 } else 441 clk_fail: 442 msg = __SHIFTIN(129, MAILBOX_DATA_TYPE) | 443 __SHIFTIN(rate / 1000, MAILBOX_DATA_DATA); 444 xusb_mailbox_send(psc, msg); 445 break; 446 case 9: 447 msg = __SHIFTIN(data, MAILBOX_DATA_DATA) | 448 __SHIFTIN(128, MAILBOX_DATA_TYPE); 449 xusb_mailbox_send(psc, msg); 450 break; 451 case 6: 452 case 128: 453 case 129: 454 sendresp = false; 455 break; 456 default: 457 sendresp = false; 458 break; 459 } 460 461 if (sendresp == false) 462 bus_space_write_4(bst, fpcih, T_XUSB_CFG_ARU_MAILBOX_OWNER_REG, 463 MAILBOX_OWNER_NONE); 464 465 return irv; 466 } 467 468 static void 469 tegra_xusb_init(struct tegra_xusb_softc * const psc) 470 { 471 struct xhci_softc * const sc = &psc->sc_xhci; 472 const bus_space_tag_t bst = sc->sc_iot; 473 const bus_space_handle_t ipfsh = psc->sc_bsh_ipfs; 474 const bus_space_handle_t fpcih = psc->sc_bsh_fpci; 475 476 device_printf(sc->sc_dev, "%s()\n", __func__); 477 478 device_printf(sc->sc_dev, "%s ipfs 0x0 = 0x%x\n", __func__, 479 bus_space_read_4(bst, ipfsh, 0x0)); 480 481 device_printf(sc->sc_dev, "%s ipfs 0x40 = 0x%x\n", __func__, 482 bus_space_read_4(bst, ipfsh, 0x40)); 483 484 device_printf(sc->sc_dev, "%s ipfs 0x80 = 0x%x\n", __func__, 485 bus_space_read_4(bst, ipfsh, 0x80)); 486 /* FPCI_BAR0_START and FPCI_BAR0_ACCESS_TYPE */ 487 bus_space_write_4(bst, ipfsh, 0x80, 0x00100000); 488 device_printf(sc->sc_dev, "%s ipfs 0x80 = 0x%x\n", __func__, 489 bus_space_read_4(bst, ipfsh, 0x80)); 490 491 device_printf(sc->sc_dev, "%s ipfs 0x180 = 0x%x\n", __func__, 492 bus_space_read_4(bst, ipfsh, 0x180)); 493 /* EN_FPCI */ 494 tegra_reg_set_clear(bst, ipfsh, 0x180, 1, 0); 495 device_printf(sc->sc_dev, "%s ipfs 0x180 = 0x%x\n", __func__, 496 bus_space_read_4(bst, ipfsh, 0x180)); 497 498 device_printf(sc->sc_dev, "%s fpci PCI_COMMAND_STATUS_REG = 0x%x\n", 499 __func__, bus_space_read_4(bst, fpcih, PCI_COMMAND_STATUS_REG)); 500 tegra_reg_set_clear(bst, fpcih, PCI_COMMAND_STATUS_REG, 501 PCI_COMMAND_MASTER_ENABLE|PCI_COMMAND_MEM_ENABLE, 0x0); 502 device_printf(sc->sc_dev, "%s fpci PCI_COMMAND_STATUS_REG = 0x%x\n", 503 __func__, bus_space_read_4(bst, fpcih, PCI_COMMAND_STATUS_REG)); 504 505 device_printf(sc->sc_dev, "%s fpci PCI_BAR0 = 0x%x\n", __func__, 506 bus_space_read_4(bst, fpcih, PCI_BAR0)); 507 /* match FPCI BAR0 to above */ 508 bus_space_write_4(bst, fpcih, PCI_BAR0, 0x10000000); 509 device_printf(sc->sc_dev, "%s fpci PCI_BAR0 = 0x%x\n", __func__, 510 bus_space_read_4(bst, fpcih, PCI_BAR0)); 511 512 device_printf(sc->sc_dev, "%s ipfs 0x188 = 0x%x\n", __func__, 513 bus_space_read_4(bst, ipfsh, 0x188)); 514 tegra_reg_set_clear(bst, ipfsh, 0x188, __BIT(16), 0); 515 device_printf(sc->sc_dev, "%s ipfs 0x188 = 0x%x\n", __func__, 516 bus_space_read_4(bst, ipfsh, 0x188)); 517 518 device_printf(sc->sc_dev, "%s fpci 0x1bc = 0x%x\n", __func__, 519 bus_space_read_4(bst, fpcih, 0x1bc)); 520 bus_space_write_4(bst, fpcih, 0x1bc, 0x80); 521 device_printf(sc->sc_dev, "%s fpci 0x1bc = 0x%x\n", __func__, 522 bus_space_read_4(bst, fpcih, 0x1bc)); 523 } 524 525 static int 526 fw_dma_alloc(struct tegra_xusb_softc * const psc, size_t size, size_t align, 527 struct fw_dma * const p) 528 { 529 struct xhci_softc * const sc = &psc->sc_xhci; 530 const bus_dma_tag_t dmat = sc->sc_bus.ub_dmatag; 531 int err; 532 533 p->size = size; 534 err = bus_dmamem_alloc(dmat, p->size, align, 0, p->segs, 535 sizeof(p->segs) / sizeof(p->segs[0]), &p->nsegs, BUS_DMA_NOWAIT); 536 if (err) 537 return err; 538 err = bus_dmamem_map(dmat, p->segs, p->nsegs, p->size, &p->addr, 539 BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 540 if (err) 541 goto free; 542 err = bus_dmamap_create(dmat, p->size, 1, p->size, 0, BUS_DMA_NOWAIT, 543 &p->map); 544 if (err) 545 goto unmap; 546 err = bus_dmamap_load(dmat, p->map, p->addr, p->size, NULL, 547 BUS_DMA_NOWAIT); 548 if (err) 549 goto destroy; 550 551 return 0; 552 553 destroy: 554 bus_dmamap_destroy(dmat, p->map); 555 unmap: 556 bus_dmamem_unmap(dmat, p->addr, p->size); 557 free: 558 bus_dmamem_free(dmat, p->segs, p->nsegs); 559 560 return err; 561 } 562 563 #if !defined(TEGRA124_XUSB_BIN_STATIC) 564 static void 565 fw_dma_free(struct tegra_xusb_softc * const psc, struct fw_dma * const p) 566 { 567 const struct xhci_softc * const sc = &psc->sc_xhci; 568 const bus_dma_tag_t dmat = sc->sc_bus.ub_dmatag; 569 570 bus_dmamap_unload(dmat, p->map); 571 bus_dmamap_destroy(dmat, p->map); 572 bus_dmamem_unmap(dmat, p->addr, p->size); 573 bus_dmamem_free(dmat, p->segs, p->nsegs); 574 } 575 #endif 576 577 #define FWHEADER_BOOT_CODETAG 8 578 #define FWHEADER_BOOT_CODESIZE 12 579 #define FWHEADER_FWIMG_LEN 100 580 #define FWHEADER__LEN 256 581 582 static void 583 tegra_xusb_load_fw(struct tegra_xusb_softc * const psc) 584 { 585 struct xhci_softc * const sc = &psc->sc_xhci; 586 #if !defined(TEGRA124_XUSB_BIN_STATIC) 587 firmware_handle_t fw; 588 #endif 589 int error; 590 size_t firmware_size; 591 void * firmware_image; 592 const uint8_t *header; 593 594 #if defined(TEGRA124_XUSB_BIN_STATIC) 595 firmware_size = (uintptr_t)&_binary_tegra124_xusb_bin_size; 596 #else 597 if ((error = firmware_open("nvidia/tegra124", "xusb.bin", &fw)) != 0) { 598 aprint_error_dev(sc->sc_dev, 599 "could not open firmware file %s: %d\n", "xusb.bin", error); 600 return; 601 } 602 firmware_size = firmware_get_size(fw); 603 #endif 604 605 error = fw_dma_alloc(psc, firmware_size, PAGE_SIZE, &psc->sc_fw_dma); 606 if (error != 0) { 607 #if !defined(TEGRA124_XUSB_BIN_STATIC) 608 firmware_close(fw); 609 #endif 610 return; 611 } 612 613 firmware_image = psc->sc_fw_dma.addr; 614 device_printf(sc->sc_dev, "blob %p len %zu\n", firmware_image, 615 firmware_size); 616 617 #if defined(TEGRA124_XUSB_BIN_STATIC) 618 memcpy(firmware_image, _binary_tegra124_xusb_bin_start, firmware_size); 619 #else 620 error = firmware_read(fw, 0, firmware_image, firmware_size); 621 if (error != 0) { 622 fw_dma_free(psc, &psc->sc_fw_dma); 623 firmware_close(fw); 624 return; 625 } 626 firmware_close(fw); 627 #endif 628 629 header = firmware_image; 630 631 const uint32_t fwimg_len = le32dec(&header[FWHEADER_FWIMG_LEN]); 632 const uint32_t boot_codetag = le32dec(&header[FWHEADER_BOOT_CODETAG]); 633 const uint32_t boot_codesize = le32dec(&header[FWHEADER_BOOT_CODESIZE]); 634 635 if (fwimg_len != firmware_size) 636 device_printf(sc->sc_dev, "fwimg_len mismatch %u != %zu\n", 637 fwimg_len, firmware_size); 638 639 bus_dmamap_sync(sc->sc_bus.ub_dmatag, psc->sc_fw_dma.map, 0, 640 firmware_size, BUS_DMASYNC_PREWRITE); 641 642 device_printf(sc->sc_dev, "XUSB_FALC_CPUCTL 0x%x\n", 643 csb_read_4(psc, XUSB_CSB_FALCON_CPUCTL_REG)); 644 device_printf(sc->sc_dev, "XUSB_CSB_MP_ILOAD_BASE_LO 0x%x\n", 645 csb_read_4(psc, XUSB_CSB_MEMPOOL_ILOAD_BASE_LO_REG)); 646 647 device_printf(sc->sc_dev, "XUSB_CSB_MP_ILOAD_ATTR 0x%x\n", 648 csb_read_4(psc, XUSB_CSB_MEMPOOL_ILOAD_ATTR_REG)); 649 csb_write_4(psc, XUSB_CSB_MEMPOOL_ILOAD_ATTR_REG, 650 fwimg_len); 651 device_printf(sc->sc_dev, "XUSB_CSB_MP_ILOAD_ATTR 0x%x\n", 652 csb_read_4(psc, XUSB_CSB_MEMPOOL_ILOAD_ATTR_REG)); 653 654 const uint64_t fwbase = psc->sc_fw_dma.map->dm_segs[0].ds_addr + 655 FWHEADER__LEN; 656 657 csb_write_4(psc, XUSB_CSB_MEMPOOL_ILOAD_BASE_HI_REG, fwbase >> 32); 658 csb_write_4(psc, XUSB_CSB_MEMPOOL_ILOAD_BASE_LO_REG, fwbase); 659 device_printf(sc->sc_dev, "XUSB_CSB_MP_ILOAD_BASE_LO 0x%x\n", 660 csb_read_4(psc, XUSB_CSB_MEMPOOL_ILOAD_BASE_LO_REG)); 661 device_printf(sc->sc_dev, "XUSB_CSB_MP_ILOAD_BASE_HI 0x%x\n", 662 csb_read_4(psc, XUSB_CSB_MEMPOOL_ILOAD_BASE_HI_REG)); 663 664 device_printf(sc->sc_dev, "XUSB_CSB_MP_APMAP 0x%x\n", 665 csb_read_4(psc, XUSB_CSB_MEMPOOL_APMAP_REG)); 666 csb_write_4(psc, XUSB_CSB_MEMPOOL_APMAP_REG, 667 XUSB_CSB_MEMPOOL_APMAP_BOOTPATH); 668 device_printf(sc->sc_dev, "XUSB_CSB_MP_APMAP 0x%x\n", 669 csb_read_4(psc, XUSB_CSB_MEMPOOL_APMAP_REG)); 670 671 device_printf(sc->sc_dev, "XUSB_CSB_MP_L2IMEMOP_TRIG 0x%x\n", 672 csb_read_4(psc, XUSB_CSB_MEMPOOL_L2IMEMOP_TRIG_REG)); 673 csb_write_4(psc, XUSB_CSB_MEMPOOL_L2IMEMOP_TRIG_REG, 674 __SHIFTIN(ACTION_L2IMEM_INVALIDATE_ALL, 675 XUSB_CSB_MEMPOOL_L2IMEMOP_TRIG_ACTION)); 676 device_printf(sc->sc_dev, "XUSB_CSB_MP_L2IMEMOP_TRIG 0x%x\n", 677 csb_read_4(psc, XUSB_CSB_MEMPOOL_L2IMEMOP_TRIG_REG)); 678 679 const u_int code_tag_blocks = 680 howmany(boot_codetag, IMEM_BLOCK_SIZE); 681 const u_int code_size_blocks = 682 howmany(boot_codesize, IMEM_BLOCK_SIZE); 683 const u_int code_blocks = code_tag_blocks + code_size_blocks; 684 685 device_printf(sc->sc_dev, "XUSB_CSB_MP_L2IMEMOP_SIZE 0x%x\n", 686 csb_read_4(psc, XUSB_CSB_MEMPOOL_L2IMEMOP_SIZE_REG)); 687 csb_write_4(psc, XUSB_CSB_MEMPOOL_L2IMEMOP_SIZE_REG, 688 __SHIFTIN(code_tag_blocks, 689 XUSB_CSB_MEMPOOL_L2IMEMOP_SIZE_SRC_OFFSET) | 690 __SHIFTIN(code_size_blocks, 691 XUSB_CSB_MEMPOOL_L2IMEMOP_SIZE_SRC_COUNT)); 692 device_printf(sc->sc_dev, "XUSB_CSB_MP_L2IMEMOP_SIZE 0x%x\n", 693 csb_read_4(psc, XUSB_CSB_MEMPOOL_L2IMEMOP_SIZE_REG)); 694 695 device_printf(sc->sc_dev, "XUSB_CSB_MP_L2IMEMOP_TRIG 0x%x\n", 696 csb_read_4(psc, XUSB_CSB_MEMPOOL_L2IMEMOP_TRIG_REG)); 697 csb_write_4(psc, XUSB_CSB_MEMPOOL_L2IMEMOP_TRIG_REG, 698 __SHIFTIN(ACTION_L2IMEM_LOAD_LOCKED_RESULT, 699 XUSB_CSB_MEMPOOL_L2IMEMOP_TRIG_ACTION)); 700 device_printf(sc->sc_dev, "XUSB_CSB_MP_L2IMEMOP_TRIG 0x%x\n", 701 csb_read_4(psc, XUSB_CSB_MEMPOOL_L2IMEMOP_TRIG_REG)); 702 703 device_printf(sc->sc_dev, "XUSB_FALC_IMFILLCTL 0x%x\n", 704 csb_read_4(psc, XUSB_CSB_FALCON_IMFILLCTL_REG)); 705 csb_write_4(psc, XUSB_CSB_FALCON_IMFILLCTL_REG, code_size_blocks); 706 device_printf(sc->sc_dev, "XUSB_FALC_IMFILLCTL 0x%x\n", 707 csb_read_4(psc, XUSB_CSB_FALCON_IMFILLCTL_REG)); 708 709 device_printf(sc->sc_dev, "XUSB_FALC_IMFILLRNG1 0x%x\n", 710 csb_read_4(psc, XUSB_CSB_FALCON_IMFILLRNG1_REG)); 711 csb_write_4(psc, XUSB_CSB_FALCON_IMFILLRNG1_REG, 712 __SHIFTIN(code_tag_blocks, XUSB_CSB_FALCON_IMFILLRNG1_TAG_LO) | 713 __SHIFTIN(code_blocks, XUSB_CSB_FALCON_IMFILLRNG1_TAG_HI)); 714 device_printf(sc->sc_dev, "XUSB_FALC_IMFILLRNG1 0x%x\n", 715 csb_read_4(psc, XUSB_CSB_FALCON_IMFILLRNG1_REG)); 716 717 device_printf(sc->sc_dev, "XUSB_FALC_DMACTL 0x%x\n", 718 csb_read_4(psc, XUSB_CSB_FALCON_DMACTL_REG)); 719 csb_write_4(psc, XUSB_CSB_FALCON_DMACTL_REG, 0); 720 device_printf(sc->sc_dev, "XUSB_FALC_DMACTL 0x%x\n", 721 csb_read_4(psc, XUSB_CSB_FALCON_DMACTL_REG)); 722 723 device_printf(sc->sc_dev, "XUSB_FALC_BOOTVEC 0x%x\n", 724 csb_read_4(psc, XUSB_CSB_FALCON_BOOTVEC_REG)); 725 csb_write_4(psc, XUSB_CSB_FALCON_BOOTVEC_REG, 726 boot_codetag); 727 device_printf(sc->sc_dev, "XUSB_FALC_BOOTVEC 0x%x\n", 728 csb_read_4(psc, XUSB_CSB_FALCON_BOOTVEC_REG)); 729 730 device_printf(sc->sc_dev, "XUSB_FALC_CPUCTL 0x%x\n", 731 csb_read_4(psc, XUSB_CSB_FALCON_CPUCTL_REG)); 732 csb_write_4(psc, XUSB_CSB_FALCON_CPUCTL_REG, 733 XUSB_CSB_FALCON_CPUCTL_STARTCPU); 734 device_printf(sc->sc_dev, "XUSB_FALC_CPUCTL 0x%x\n", 735 csb_read_4(psc, XUSB_CSB_FALCON_CPUCTL_REG)); 736 } 737 738 static uint32_t 739 csb_read_4(struct tegra_xusb_softc * const psc, bus_size_t csb_offset) 740 { 741 const uint32_t range = __SHIFTOUT(csb_offset, XUSB_CSB_RANGE); 742 const bus_size_t offset = __SHIFTOUT(csb_offset, XUSB_CSB_OFFSET); 743 const bus_space_tag_t bst = psc->sc_xhci.sc_iot; 744 const bus_space_handle_t fpcih = psc->sc_bsh_fpci; 745 746 bus_space_write_4(bst, fpcih, T_XUSB_CFG_ARU_C11_CSBRANGE_REG, range); 747 return bus_space_read_4(bst, fpcih, T_XUSB_CFG_CSB_BASE_ADDR + offset); 748 } 749 750 static void 751 csb_write_4(struct tegra_xusb_softc * const psc, bus_size_t csb_offset, 752 uint32_t value) 753 { 754 const uint32_t range = __SHIFTOUT(csb_offset, XUSB_CSB_RANGE); 755 const bus_size_t offset = __SHIFTOUT(csb_offset, XUSB_CSB_OFFSET); 756 const bus_space_tag_t bst = psc->sc_xhci.sc_iot; 757 const bus_space_handle_t fpcih = psc->sc_bsh_fpci; 758 759 bus_space_write_4(bst, fpcih, T_XUSB_CFG_ARU_C11_CSBRANGE_REG, range); 760 bus_space_write_4(bst, fpcih, T_XUSB_CFG_CSB_BASE_ADDR + offset, value); 761 } 762 763 static int 764 xusb_mailbox_send(struct tegra_xusb_softc * const psc, uint32_t msg) 765 { 766 struct xhci_softc * const sc = &psc->sc_xhci; 767 const bus_space_tag_t bst = psc->sc_xhci.sc_iot; 768 const bus_space_handle_t fpcih = psc->sc_bsh_fpci; 769 uint32_t val; 770 bool wait = false; 771 772 const uint8_t type = __SHIFTOUT(msg, MAILBOX_DATA_TYPE); 773 774 if (!(type == 128 || type == 129)) { 775 val = bus_space_read_4(bst, fpcih, 776 T_XUSB_CFG_ARU_MAILBOX_OWNER_REG); 777 device_printf(sc->sc_dev, "XUSB_CFG_ARU_MBOX_OWNER 0x%x\n", 778 val); 779 if (val != MAILBOX_OWNER_NONE) { 780 return EBUSY; 781 } 782 783 bus_space_write_4(bst, fpcih, T_XUSB_CFG_ARU_MAILBOX_OWNER_REG, 784 MAILBOX_OWNER_SW); 785 786 val = bus_space_read_4(bst, fpcih, 787 T_XUSB_CFG_ARU_MAILBOX_OWNER_REG); 788 device_printf(sc->sc_dev, "XUSB_CFG_ARU_MBOX_OWNER 0x%x\n", 789 val); 790 if (val != MAILBOX_OWNER_SW) { 791 return EBUSY; 792 } 793 794 wait = true; 795 } 796 797 bus_space_write_4(bst, fpcih, T_XUSB_CFG_ARU_MAILBOX_DATA_IN_REG, msg); 798 799 tegra_reg_set_clear(bst, fpcih, T_XUSB_CFG_ARU_MAILBOX_CMD_REG, 800 T_XUSB_CFG_ARU_MAILBOX_CMD_INT_EN | 801 T_XUSB_CFG_ARU_MAILBOX_CMD_DEST_FALCON, 0); 802 803 if (wait) { 804 805 for (u_int i = 0; i < 2500; i++) { 806 val = bus_space_read_4(bst, fpcih, 807 T_XUSB_CFG_ARU_MAILBOX_OWNER_REG); 808 device_printf(sc->sc_dev, 809 "XUSB_CFG_ARU_MBOX_OWNER 0x%x\n", val); 810 if (val == MAILBOX_OWNER_NONE) { 811 break; 812 } 813 DELAY(10); 814 } 815 816 val = bus_space_read_4(bst, fpcih, 817 T_XUSB_CFG_ARU_MAILBOX_OWNER_REG); 818 device_printf(sc->sc_dev, 819 "XUSB_CFG_ARU_MBOX_OWNER 0x%x\n", val); 820 if (val != MAILBOX_OWNER_NONE) { 821 device_printf(sc->sc_dev, 822 "timeout, XUSB_CFG_ARU_MBOX_OWNER 0x%x\n", val); 823 } 824 } 825 826 return 0; 827 } 828
Indexes created Wed Sep 24 22:09:59 GMT 2025