tegra_xusb.c revision 1.6
1 /* $NetBSD: tegra_xusb.c,v 1.6 2017/04/28 09:46:49 jmcneill Exp $ */ 2 3 /* 4 * Copyright (c) 2016 Jonathan A. Kollasch 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR 20 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 21 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 22 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 23 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 25 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 26 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include "locators.h" 30 #include "opt_tegra.h" 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: tegra_xusb.c,v 1.6 2017/04/28 09:46:49 jmcneill Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/bus.h> 37 #include <sys/device.h> 38 #include <sys/intr.h> 39 #include <sys/systm.h> 40 #include <sys/kernel.h> 41 42 #include <arm/nvidia/tegra_reg.h> 43 #include <arm/nvidia/tegra_var.h> 44 45 #include <arm/nvidia/tegra_xusbreg.h> 46 #include <dev/pci/pcireg.h> 47 48 #include <dev/fdt/fdtvar.h> 49 50 #include <dev/firmload.h> 51 52 #include <dev/usb/usb.h> 53 #include <dev/usb/usbdi.h> 54 #include <dev/usb/usbdivar.h> 55 #include <dev/usb/usb_mem.h> 56 57 #include <dev/usb/xhcireg.h> 58 #include <dev/usb/xhcivar.h> 59 60 #ifdef TEGRA_XUSB_DEBUG 61 int tegra_xusb_debug = 1; 62 #else 63 int tegra_xusb_debug = 0; 64 #endif 65 66 #define DPRINTF(...) if (tegra_xusb_debug) device_printf(__VA_ARGS__) 67 68 static int tegra_xusb_match(device_t, cfdata_t, void *); 69 static void tegra_xusb_attach(device_t, device_t, void *); 70 static void tegra_xusb_mountroot(device_t); 71 72 static int tegra_xusb_intr_mbox(void *); 73 74 #ifdef TEGRA124_XUSB_BIN_STATIC 75 extern const char _binary_tegra124_xusb_bin_size[]; 76 extern const char _binary_tegra124_xusb_bin_start[]; 77 #endif 78 79 struct fw_dma { 80 bus_dmamap_t map; 81 void * addr; 82 bus_dma_segment_t segs[1]; 83 int nsegs; 84 size_t size; 85 }; 86 87 struct tegra_xusb_softc { 88 struct xhci_softc sc_xhci; 89 int sc_phandle; 90 bus_space_handle_t sc_bsh_xhci; 91 bus_space_handle_t sc_bsh_fpci; 92 bus_space_handle_t sc_bsh_ipfs; 93 void *sc_ih; 94 void *sc_ih_mbox; 95 struct fw_dma sc_fw_dma; 96 struct clk *sc_clk_ss_src; 97 }; 98 99 static uint32_t csb_read_4(struct tegra_xusb_softc * const, bus_size_t); 100 static void csb_write_4(struct tegra_xusb_softc * const, bus_size_t, 101 uint32_t); 102 103 static void tegra_xusb_init(struct tegra_xusb_softc * const); 104 static int tegra_xusb_load_fw(struct tegra_xusb_softc * const); 105 106 static int xusb_mailbox_send(struct tegra_xusb_softc * const, uint32_t); 107 108 CFATTACH_DECL_NEW(tegra_xusb, sizeof(struct tegra_xusb_softc), 109 tegra_xusb_match, tegra_xusb_attach, NULL, NULL); 110 111 static int 112 tegra_xusb_match(device_t parent, cfdata_t cf, void *aux) 113 { 114 const char * const compatible[] = { "nvidia,tegra124-xusb", NULL }; 115 struct fdt_attach_args * const faa = aux; 116 117 return of_match_compatible(faa->faa_phandle, compatible); 118 } 119 120 #define tegra_xusb_attach_check(sc, cond, fmt, ...) \ 121 do { \ 122 if (cond) { \ 123 aprint_error_dev(sc->sc_dev, fmt, ## __VA_ARGS__); \ 124 return; \ 125 } \ 126 } while (0) 127 128 static void 129 tegra_xusb_attach(device_t parent, device_t self, void *aux) 130 { 131 struct tegra_xusb_softc * const psc = device_private(self); 132 struct xhci_softc * const sc = &psc->sc_xhci; 133 struct fdt_attach_args * const faa = aux; 134 char intrstr[128]; 135 bus_addr_t addr; 136 bus_size_t size; 137 struct fdtbus_reset *rst; 138 struct clk *clk; 139 uint32_t rate; 140 int error; 141 142 aprint_naive("\n"); 143 aprint_normal(": XUSB\n"); 144 145 sc->sc_dev = self; 146 sc->sc_iot = faa->faa_bst; 147 sc->sc_bus.ub_hcpriv = sc; 148 sc->sc_bus.ub_dmatag = faa->faa_dmat; 149 psc->sc_phandle = faa->faa_phandle; 150 151 if (fdtbus_get_reg(faa->faa_phandle, 0, &addr, &size) != 0) { 152 aprint_error(": couldn't get registers\n"); 153 return; 154 } 155 error = bus_space_map(sc->sc_iot, addr, size, 0, &sc->sc_ioh); 156 if (error) { 157 aprint_error(": couldn't map %#llx: %d", (uint64_t)addr, error); 158 return; 159 } 160 DPRINTF(sc->sc_dev, "mapped %#llx\n", (uint64_t)addr); 161 162 if (fdtbus_get_reg(faa->faa_phandle, 1, &addr, &size) != 0) { 163 aprint_error(": couldn't get registers\n"); 164 return; 165 } 166 error = bus_space_map(sc->sc_iot, addr, size, 0, &psc->sc_bsh_fpci); 167 if (error) { 168 aprint_error(": couldn't map %#llx: %d", (uint64_t)addr, error); 169 return; 170 } 171 DPRINTF(sc->sc_dev, "mapped %#llx\n", (uint64_t)addr); 172 173 if (fdtbus_get_reg(faa->faa_phandle, 2, &addr, &size) != 0) { 174 aprint_error(": couldn't get registers\n"); 175 return; 176 } 177 error = bus_space_map(sc->sc_iot, addr, size, 0, &psc->sc_bsh_ipfs); 178 if (error) { 179 aprint_error(": couldn't map %#llx: %d", (uint64_t)addr, error); 180 return; 181 } 182 DPRINTF(sc->sc_dev, "mapped %#llx\n", (uint64_t)addr); 183 184 if (!fdtbus_intr_str(faa->faa_phandle, 0, intrstr, sizeof(intrstr))) { 185 aprint_error_dev(self, "failed to decode interrupt\n"); 186 return; 187 } 188 189 psc->sc_ih = fdtbus_intr_establish(faa->faa_phandle, 0, IPL_USB, 190 0, xhci_intr, sc); 191 if (psc->sc_ih == NULL) { 192 aprint_error_dev(self, "failed to establish interrupt on %s\n", 193 intrstr); 194 return; 195 } 196 aprint_normal_dev(self, "interrupting on %s\n", intrstr); 197 198 if (!fdtbus_intr_str(faa->faa_phandle, 1, intrstr, sizeof(intrstr))) { 199 aprint_error_dev(self, "failed to decode interrupt\n"); 200 return; 201 } 202 203 psc->sc_ih_mbox = fdtbus_intr_establish(faa->faa_phandle, 1, IPL_VM, 204 0, tegra_xusb_intr_mbox, psc); 205 if (psc->sc_ih_mbox == NULL) { 206 aprint_error_dev(self, "failed to establish interrupt on %s\n", 207 intrstr); 208 return; 209 } 210 aprint_normal_dev(self, "interrupting on %s\n", intrstr); 211 212 clk = fdtbus_clock_get(faa->faa_phandle, "pll_e"); 213 rate = clk_get_rate(clk); 214 error = clk_enable(clk); /* XXX set frequency */ 215 DPRINTF(sc->sc_dev, "rate %u error %d\n", rate, error); 216 tegra_xusb_attach_check(sc, error, "failed to enable pll_e clock"); 217 218 clk = fdtbus_clock_get(faa->faa_phandle, "xusb_host_src"); 219 rate = clk_get_rate(clk); 220 DPRINTF(sc->sc_dev, "rate %u error %d\n", rate, error); 221 error = clk_set_rate(clk, 102000000); 222 tegra_xusb_attach_check(sc, error, "failed to set xusb_host_src clock rate"); 223 224 rate = clk_get_rate(clk); 225 error = clk_enable(clk); /* XXX set frequency */ 226 DPRINTF(sc->sc_dev, "rate %u error %d\n", rate, error); 227 tegra_xusb_attach_check(sc, error, "failed to enable xusb_host_src clock"); 228 229 clk = fdtbus_clock_get(faa->faa_phandle, "xusb_falcon_src"); 230 rate = clk_get_rate(clk); 231 DPRINTF(sc->sc_dev, "rate %u error %d\n", rate, error); 232 error = clk_set_rate(clk, 204000000); 233 tegra_xusb_attach_check(sc, error, "failed to set xusb_falcon_src clock rate"); 234 235 rate = clk_get_rate(clk); 236 error = clk_enable(clk); 237 DPRINTF(sc->sc_dev, "rate %u error %d\n", rate, error); 238 tegra_xusb_attach_check(sc, error, "failed to enable xusb_falcon_src clock"); 239 240 clk = fdtbus_clock_get(faa->faa_phandle, "xusb_host"); 241 rate = clk_get_rate(clk); 242 error = clk_enable(clk); /* XXX set frequency */ 243 DPRINTF(sc->sc_dev, "rate %u error %d\n", rate, error); 244 245 clk = fdtbus_clock_get(faa->faa_phandle, "xusb_ss"); 246 rate = clk_get_rate(clk); 247 error = clk_enable(clk); /* XXX set frequency */ 248 DPRINTF(sc->sc_dev, "xusb_ss rate %u error %d\n", rate, error); 249 tegra_xusb_attach_check(sc, error, "failed to enable xusb_ss clock"); 250 251 psc->sc_clk_ss_src = fdtbus_clock_get(faa->faa_phandle, "xusb_ss_src"); 252 tegra_xusb_attach_check(sc, psc->sc_clk_ss_src == NULL, 253 "failed to get xusb_ss_src clock"); 254 255 rate = clk_get_rate(psc->sc_clk_ss_src); 256 DPRINTF(sc->sc_dev, "xusb_ss_src rate %u\n", rate); 257 error = clk_set_rate(psc->sc_clk_ss_src, 2000000); 258 rate = clk_get_rate(psc->sc_clk_ss_src); 259 DPRINTF(sc->sc_dev, "xusb_ss_src rate %u error %d\n", rate, error); 260 tegra_xusb_attach_check(sc, error, "failed to get xusb_ss_src clock rate"); 261 262 rate = clk_get_rate(psc->sc_clk_ss_src); 263 DPRINTF(sc->sc_dev, "ss_src rate %u\n", rate); 264 tegra_xusb_attach_check(sc, error, "failed to set xusb_ss_src clock rate"); 265 266 error = clk_set_rate(psc->sc_clk_ss_src, 120000000); 267 rate = clk_get_rate(psc->sc_clk_ss_src); 268 DPRINTF(sc->sc_dev, "ss_src rate %u error %d\n", rate, error); 269 tegra_xusb_attach_check(sc, error, "failed to get xusb_ss_src clock rate"); 270 271 error = clk_enable(psc->sc_clk_ss_src); 272 DPRINTF(sc->sc_dev, "ss_src rate %u error %d\n", rate, error); 273 tegra_xusb_attach_check(sc, error, "failed to enable xusb_ss_src clock"); 274 275 #if 0 276 clk = fdtbus_clock_get(faa->faa_phandle, "xusb_hs_src"); 277 error = 0; 278 rate = clk_get_rate(clk); 279 DPRINTF(sc->sc_dev, "rate %u error %d\n", rate, error); 280 #endif 281 282 clk = fdtbus_clock_get(faa->faa_phandle, "xusb_fs_src"); 283 rate = clk_get_rate(clk); 284 error = clk_enable(clk); /* XXX set frequency */ 285 DPRINTF(sc->sc_dev, "rate %u error %d\n", rate, error); 286 tegra_xusb_attach_check(sc, error, "failed to enable xusb_fs_src clock"); 287 288 rst = fdtbus_reset_get(faa->faa_phandle, "xusb_host"); 289 fdtbus_reset_deassert(rst); 290 291 rst = fdtbus_reset_get(faa->faa_phandle, "xusb_src"); 292 fdtbus_reset_deassert(rst); 293 294 rst = fdtbus_reset_get(faa->faa_phandle, "xusb_ss"); 295 fdtbus_reset_deassert(rst); 296 297 DELAY(1); 298 299 tegra_xusb_init(psc); 300 301 #if defined(TEGRA124_XUSB_BIN_STATIC) 302 tegra_xusb_mountroot(sc->sc_dev); 303 #else 304 config_mountroot(sc->sc_dev, tegra_xusb_mountroot); 305 #endif 306 } 307 308 static void 309 tegra_xusb_mountroot(device_t self) 310 { 311 struct tegra_xusb_softc * const psc = device_private(self); 312 struct xhci_softc * const sc = &psc->sc_xhci; 313 const bus_space_tag_t bst = sc->sc_iot; 314 const bus_space_handle_t ipfsh = psc->sc_bsh_ipfs; 315 struct clk *clk; 316 struct fdtbus_reset *rst; 317 uint32_t rate; 318 uint32_t val; 319 int error; 320 321 DPRINTF(sc->sc_dev, "%s()\n", __func__); 322 323 val = bus_space_read_4(bst, ipfsh, 0x0); 324 DPRINTF(sc->sc_dev, "%s ipfs 0x0 = 0x%x\n", __func__, val); 325 326 if (tegra_xusb_load_fw(psc) != 0) 327 return; 328 DPRINTF(sc->sc_dev, "post fw\n"); 329 330 tegra_xusbpad_xhci_enable(); 331 332 clk = fdtbus_clock_get(psc->sc_phandle, "xusb_falcon_src"); 333 rate = clk_get_rate(clk); 334 error = clk_enable(clk); 335 DPRINTF(sc->sc_dev, "rate %u error %d\n", rate, error); 336 337 clk = fdtbus_clock_get(psc->sc_phandle, "xusb_host_src"); 338 rate = clk_get_rate(clk); 339 error = clk_enable(clk); 340 DPRINTF(sc->sc_dev, "rate %u error %d\n", rate, error); 341 342 val = bus_space_read_4(bst, ipfsh, 0x0); 343 DPRINTF(sc->sc_dev, "%s ipfs 0x0 = 0x%x\n", __func__, val); 344 345 rst = fdtbus_reset_get(psc->sc_phandle, "xusb_host"); 346 fdtbus_reset_deassert(rst); 347 348 rst = fdtbus_reset_get(psc->sc_phandle, "xusb_src"); 349 fdtbus_reset_deassert(rst); 350 351 rst = fdtbus_reset_get(psc->sc_phandle, "xusb_ss"); 352 fdtbus_reset_deassert(rst); 353 354 val = csb_read_4(psc, XUSB_CSB_FALCON_CPUCTL_REG); 355 DPRINTF(sc->sc_dev, "XUSB_FALC_CPUCTL 0x%x\n", val); 356 357 358 error = xhci_init(sc); 359 if (error) { 360 aprint_error_dev(self, "init failed, error=%d\n", error); 361 return; 362 } 363 364 sc->sc_child = config_found(self, &sc->sc_bus, usbctlprint); 365 366 sc->sc_child2 = config_found(self, &sc->sc_bus2, usbctlprint); 367 368 error = xusb_mailbox_send(psc, 0x01000000); 369 if (error) { 370 aprint_error_dev(self, "send failed, error=%d\n", error); 371 } 372 } 373 374 static int 375 tegra_xusb_intr_mbox(void *v) 376 { 377 struct tegra_xusb_softc * const psc = v; 378 struct xhci_softc * const sc = &psc->sc_xhci; 379 const bus_space_tag_t bst = sc->sc_iot; 380 const bus_space_handle_t fpcih = psc->sc_bsh_fpci; 381 uint32_t val; 382 uint32_t irv; 383 uint32_t msg; 384 int error; 385 386 DPRINTF(sc->sc_dev, "%s()\n", __func__); 387 388 irv = bus_space_read_4(bst, fpcih, T_XUSB_CFG_ARU_SMI_INTR_REG); 389 DPRINTF(sc->sc_dev, "XUSB_CFG_ARU_SMI_INTR 0x%x\n", irv); 390 bus_space_write_4(bst, fpcih, T_XUSB_CFG_ARU_SMI_INTR_REG, irv); 391 392 if (irv & T_XUSB_CFG_ARU_SMI_INTR_FW_HANG) 393 aprint_error_dev(sc->sc_dev, "firmware hang\n"); 394 395 msg = bus_space_read_4(bst, fpcih, T_XUSB_CFG_ARU_MAILBOX_DATA_OUT_REG); 396 DPRINTF(sc->sc_dev, "XUSB_CFG_ARU_MBOX_DATA_OUT 0x%x\n", msg); 397 398 val = bus_space_read_4(bst, fpcih, T_XUSB_CFG_ARU_MAILBOX_CMD_REG); 399 DPRINTF(sc->sc_dev, "XUSB_CFG_ARU_MBOX_CMD 0x%x\n", val); 400 val &= ~T_XUSB_CFG_ARU_MAILBOX_CMD_DEST_SMI; 401 bus_space_write_4(bst, fpcih, T_XUSB_CFG_ARU_MAILBOX_CMD_REG, val); 402 403 bool sendresp = true; 404 u_int rate; 405 406 const uint32_t data = __SHIFTOUT(msg, MAILBOX_DATA_DATA); 407 const uint8_t type = __SHIFTOUT(msg, MAILBOX_DATA_TYPE); 408 409 switch (type) { 410 case 2: 411 case 3: 412 DPRINTF(sc->sc_dev, "FALC_CLOCK %u\n", data * 1000); 413 break; 414 case 4: 415 case 5: 416 DPRINTF(sc->sc_dev, "SSPI_CLOCK %u\n", data * 1000); 417 rate = clk_get_rate(psc->sc_clk_ss_src); 418 DPRINTF(sc->sc_dev, "rate of psc->sc_clk_ss_src %u\n", 419 rate); 420 error = clk_set_rate(psc->sc_clk_ss_src, data * 1000); 421 if (error != 0) 422 goto clk_fail; 423 rate = clk_get_rate(psc->sc_clk_ss_src); 424 DPRINTF(sc->sc_dev, 425 "rate of psc->sc_clk_ss_src %u after\n", rate); 426 if (data == (rate / 1000)) { 427 msg = __SHIFTIN(128, MAILBOX_DATA_TYPE) | 428 __SHIFTIN(rate / 1000, MAILBOX_DATA_DATA); 429 } else 430 clk_fail: 431 msg = __SHIFTIN(129, MAILBOX_DATA_TYPE) | 432 __SHIFTIN(rate / 1000, MAILBOX_DATA_DATA); 433 xusb_mailbox_send(psc, msg); 434 break; 435 case 9: 436 msg = __SHIFTIN(data, MAILBOX_DATA_DATA) | 437 __SHIFTIN(128, MAILBOX_DATA_TYPE); 438 xusb_mailbox_send(psc, msg); 439 break; 440 case 6: 441 case 128: 442 case 129: 443 sendresp = false; 444 break; 445 default: 446 sendresp = false; 447 break; 448 } 449 450 if (sendresp == false) 451 bus_space_write_4(bst, fpcih, T_XUSB_CFG_ARU_MAILBOX_OWNER_REG, 452 MAILBOX_OWNER_NONE); 453 454 return irv; 455 } 456 457 static void 458 tegra_xusb_init(struct tegra_xusb_softc * const psc) 459 { 460 struct xhci_softc * const sc = &psc->sc_xhci; 461 const bus_space_tag_t bst = sc->sc_iot; 462 const bus_space_handle_t ipfsh = psc->sc_bsh_ipfs; 463 const bus_space_handle_t fpcih = psc->sc_bsh_fpci; 464 465 DPRINTF(sc->sc_dev, "%s()\n", __func__); 466 467 DPRINTF(sc->sc_dev, "%s ipfs 0x0 = 0x%x\n", __func__, 468 bus_space_read_4(bst, ipfsh, 0x0)); 469 470 DPRINTF(sc->sc_dev, "%s ipfs 0x40 = 0x%x\n", __func__, 471 bus_space_read_4(bst, ipfsh, 0x40)); 472 473 DPRINTF(sc->sc_dev, "%s ipfs 0x80 = 0x%x\n", __func__, 474 bus_space_read_4(bst, ipfsh, 0x80)); 475 /* FPCI_BAR0_START and FPCI_BAR0_ACCESS_TYPE */ 476 bus_space_write_4(bst, ipfsh, 0x80, 0x00100000); 477 DPRINTF(sc->sc_dev, "%s ipfs 0x80 = 0x%x\n", __func__, 478 bus_space_read_4(bst, ipfsh, 0x80)); 479 480 DPRINTF(sc->sc_dev, "%s ipfs 0x180 = 0x%x\n", __func__, 481 bus_space_read_4(bst, ipfsh, 0x180)); 482 /* EN_FPCI */ 483 tegra_reg_set_clear(bst, ipfsh, 0x180, 1, 0); 484 DPRINTF(sc->sc_dev, "%s ipfs 0x180 = 0x%x\n", __func__, 485 bus_space_read_4(bst, ipfsh, 0x180)); 486 487 DPRINTF(sc->sc_dev, "%s fpci PCI_COMMAND_STATUS_REG = 0x%x\n", 488 __func__, bus_space_read_4(bst, fpcih, PCI_COMMAND_STATUS_REG)); 489 tegra_reg_set_clear(bst, fpcih, PCI_COMMAND_STATUS_REG, 490 PCI_COMMAND_MASTER_ENABLE|PCI_COMMAND_MEM_ENABLE, 0x0); 491 DPRINTF(sc->sc_dev, "%s fpci PCI_COMMAND_STATUS_REG = 0x%x\n", 492 __func__, bus_space_read_4(bst, fpcih, PCI_COMMAND_STATUS_REG)); 493 494 DPRINTF(sc->sc_dev, "%s fpci PCI_BAR0 = 0x%x\n", __func__, 495 bus_space_read_4(bst, fpcih, PCI_BAR0)); 496 /* match FPCI BAR0 to above */ 497 bus_space_write_4(bst, fpcih, PCI_BAR0, 0x10000000); 498 DPRINTF(sc->sc_dev, "%s fpci PCI_BAR0 = 0x%x\n", __func__, 499 bus_space_read_4(bst, fpcih, PCI_BAR0)); 500 501 DPRINTF(sc->sc_dev, "%s ipfs 0x188 = 0x%x\n", __func__, 502 bus_space_read_4(bst, ipfsh, 0x188)); 503 tegra_reg_set_clear(bst, ipfsh, 0x188, __BIT(16), 0); 504 DPRINTF(sc->sc_dev, "%s ipfs 0x188 = 0x%x\n", __func__, 505 bus_space_read_4(bst, ipfsh, 0x188)); 506 507 DPRINTF(sc->sc_dev, "%s fpci 0x1bc = 0x%x\n", __func__, 508 bus_space_read_4(bst, fpcih, 0x1bc)); 509 bus_space_write_4(bst, fpcih, 0x1bc, 0x80); 510 DPRINTF(sc->sc_dev, "%s fpci 0x1bc = 0x%x\n", __func__, 511 bus_space_read_4(bst, fpcih, 0x1bc)); 512 } 513 514 static int 515 fw_dma_alloc(struct tegra_xusb_softc * const psc, size_t size, size_t align, 516 struct fw_dma * const p) 517 { 518 struct xhci_softc * const sc = &psc->sc_xhci; 519 const bus_dma_tag_t dmat = sc->sc_bus.ub_dmatag; 520 int err; 521 522 p->size = size; 523 err = bus_dmamem_alloc(dmat, p->size, align, 0, p->segs, 524 sizeof(p->segs) / sizeof(p->segs[0]), &p->nsegs, BUS_DMA_NOWAIT); 525 if (err) 526 return err; 527 err = bus_dmamem_map(dmat, p->segs, p->nsegs, p->size, &p->addr, 528 BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 529 if (err) 530 goto free; 531 err = bus_dmamap_create(dmat, p->size, 1, p->size, 0, BUS_DMA_NOWAIT, 532 &p->map); 533 if (err) 534 goto unmap; 535 err = bus_dmamap_load(dmat, p->map, p->addr, p->size, NULL, 536 BUS_DMA_NOWAIT); 537 if (err) 538 goto destroy; 539 540 return 0; 541 542 destroy: 543 bus_dmamap_destroy(dmat, p->map); 544 unmap: 545 bus_dmamem_unmap(dmat, p->addr, p->size); 546 free: 547 bus_dmamem_free(dmat, p->segs, p->nsegs); 548 549 return err; 550 } 551 552 #if !defined(TEGRA124_XUSB_BIN_STATIC) 553 static void 554 fw_dma_free(struct tegra_xusb_softc * const psc, struct fw_dma * const p) 555 { 556 const struct xhci_softc * const sc = &psc->sc_xhci; 557 const bus_dma_tag_t dmat = sc->sc_bus.ub_dmatag; 558 559 bus_dmamap_unload(dmat, p->map); 560 bus_dmamap_destroy(dmat, p->map); 561 bus_dmamem_unmap(dmat, p->addr, p->size); 562 bus_dmamem_free(dmat, p->segs, p->nsegs); 563 } 564 #endif 565 566 #define FWHEADER_BOOT_CODETAG 8 567 #define FWHEADER_BOOT_CODESIZE 12 568 #define FWHEADER_FWIMG_LEN 100 569 #define FWHEADER__LEN 256 570 571 static int 572 tegra_xusb_load_fw(struct tegra_xusb_softc * const psc) 573 { 574 struct xhci_softc * const sc = &psc->sc_xhci; 575 #if !defined(TEGRA124_XUSB_BIN_STATIC) 576 firmware_handle_t fw; 577 #endif 578 int error; 579 size_t firmware_size; 580 void * firmware_image; 581 const uint8_t *header; 582 583 #if defined(TEGRA124_XUSB_BIN_STATIC) 584 firmware_size = (uintptr_t)&_binary_tegra124_xusb_bin_size; 585 #else 586 if ((error = firmware_open("nvidia/tegra124", "xusb.bin", &fw)) != 0) { 587 aprint_error_dev(sc->sc_dev, 588 "couldn't load firmware from 'nvidia/tegra124/xusb.bin': %d\n", error); 589 return error; 590 } 591 firmware_size = firmware_get_size(fw); 592 #endif 593 594 error = fw_dma_alloc(psc, firmware_size, PAGE_SIZE, &psc->sc_fw_dma); 595 if (error != 0) { 596 #if !defined(TEGRA124_XUSB_BIN_STATIC) 597 firmware_close(fw); 598 #endif 599 return error; 600 } 601 602 firmware_image = psc->sc_fw_dma.addr; 603 DPRINTF(sc->sc_dev, "blob %p len %zu\n", firmware_image, 604 firmware_size); 605 606 #if defined(TEGRA124_XUSB_BIN_STATIC) 607 memcpy(firmware_image, _binary_tegra124_xusb_bin_start, firmware_size); 608 #else 609 error = firmware_read(fw, 0, firmware_image, firmware_size); 610 if (error != 0) { 611 fw_dma_free(psc, &psc->sc_fw_dma); 612 firmware_close(fw); 613 return error; 614 } 615 firmware_close(fw); 616 #endif 617 618 header = firmware_image; 619 620 const uint32_t fwimg_len = le32dec(&header[FWHEADER_FWIMG_LEN]); 621 const uint32_t boot_codetag = le32dec(&header[FWHEADER_BOOT_CODETAG]); 622 const uint32_t boot_codesize = le32dec(&header[FWHEADER_BOOT_CODESIZE]); 623 624 if (fwimg_len != firmware_size) 625 aprint_error_dev(sc->sc_dev, "fwimg_len mismatch %u != %zu\n", 626 fwimg_len, firmware_size); 627 628 bus_dmamap_sync(sc->sc_bus.ub_dmatag, psc->sc_fw_dma.map, 0, 629 firmware_size, BUS_DMASYNC_PREWRITE); 630 631 DPRINTF(sc->sc_dev, "XUSB_FALC_CPUCTL 0x%x\n", 632 csb_read_4(psc, XUSB_CSB_FALCON_CPUCTL_REG)); 633 DPRINTF(sc->sc_dev, "XUSB_CSB_MP_ILOAD_BASE_LO 0x%x\n", 634 csb_read_4(psc, XUSB_CSB_MEMPOOL_ILOAD_BASE_LO_REG)); 635 636 DPRINTF(sc->sc_dev, "XUSB_CSB_MP_ILOAD_ATTR 0x%x\n", 637 csb_read_4(psc, XUSB_CSB_MEMPOOL_ILOAD_ATTR_REG)); 638 csb_write_4(psc, XUSB_CSB_MEMPOOL_ILOAD_ATTR_REG, 639 fwimg_len); 640 DPRINTF(sc->sc_dev, "XUSB_CSB_MP_ILOAD_ATTR 0x%x\n", 641 csb_read_4(psc, XUSB_CSB_MEMPOOL_ILOAD_ATTR_REG)); 642 643 const uint64_t fwbase = psc->sc_fw_dma.map->dm_segs[0].ds_addr + 644 FWHEADER__LEN; 645 646 csb_write_4(psc, XUSB_CSB_MEMPOOL_ILOAD_BASE_HI_REG, fwbase >> 32); 647 csb_write_4(psc, XUSB_CSB_MEMPOOL_ILOAD_BASE_LO_REG, fwbase); 648 DPRINTF(sc->sc_dev, "XUSB_CSB_MP_ILOAD_BASE_LO 0x%x\n", 649 csb_read_4(psc, XUSB_CSB_MEMPOOL_ILOAD_BASE_LO_REG)); 650 DPRINTF(sc->sc_dev, "XUSB_CSB_MP_ILOAD_BASE_HI 0x%x\n", 651 csb_read_4(psc, XUSB_CSB_MEMPOOL_ILOAD_BASE_HI_REG)); 652 653 DPRINTF(sc->sc_dev, "XUSB_CSB_MP_APMAP 0x%x\n", 654 csb_read_4(psc, XUSB_CSB_MEMPOOL_APMAP_REG)); 655 csb_write_4(psc, XUSB_CSB_MEMPOOL_APMAP_REG, 656 XUSB_CSB_MEMPOOL_APMAP_BOOTPATH); 657 DPRINTF(sc->sc_dev, "XUSB_CSB_MP_APMAP 0x%x\n", 658 csb_read_4(psc, XUSB_CSB_MEMPOOL_APMAP_REG)); 659 660 DPRINTF(sc->sc_dev, "XUSB_CSB_MP_L2IMEMOP_TRIG 0x%x\n", 661 csb_read_4(psc, XUSB_CSB_MEMPOOL_L2IMEMOP_TRIG_REG)); 662 csb_write_4(psc, XUSB_CSB_MEMPOOL_L2IMEMOP_TRIG_REG, 663 __SHIFTIN(ACTION_L2IMEM_INVALIDATE_ALL, 664 XUSB_CSB_MEMPOOL_L2IMEMOP_TRIG_ACTION)); 665 DPRINTF(sc->sc_dev, "XUSB_CSB_MP_L2IMEMOP_TRIG 0x%x\n", 666 csb_read_4(psc, XUSB_CSB_MEMPOOL_L2IMEMOP_TRIG_REG)); 667 668 const u_int code_tag_blocks = 669 howmany(boot_codetag, IMEM_BLOCK_SIZE); 670 const u_int code_size_blocks = 671 howmany(boot_codesize, IMEM_BLOCK_SIZE); 672 const u_int code_blocks = code_tag_blocks + code_size_blocks; 673 674 DPRINTF(sc->sc_dev, "XUSB_CSB_MP_L2IMEMOP_SIZE 0x%x\n", 675 csb_read_4(psc, XUSB_CSB_MEMPOOL_L2IMEMOP_SIZE_REG)); 676 csb_write_4(psc, XUSB_CSB_MEMPOOL_L2IMEMOP_SIZE_REG, 677 __SHIFTIN(code_tag_blocks, 678 XUSB_CSB_MEMPOOL_L2IMEMOP_SIZE_SRC_OFFSET) | 679 __SHIFTIN(code_size_blocks, 680 XUSB_CSB_MEMPOOL_L2IMEMOP_SIZE_SRC_COUNT)); 681 DPRINTF(sc->sc_dev, "XUSB_CSB_MP_L2IMEMOP_SIZE 0x%x\n", 682 csb_read_4(psc, XUSB_CSB_MEMPOOL_L2IMEMOP_SIZE_REG)); 683 684 DPRINTF(sc->sc_dev, "XUSB_CSB_MP_L2IMEMOP_TRIG 0x%x\n", 685 csb_read_4(psc, XUSB_CSB_MEMPOOL_L2IMEMOP_TRIG_REG)); 686 csb_write_4(psc, XUSB_CSB_MEMPOOL_L2IMEMOP_TRIG_REG, 687 __SHIFTIN(ACTION_L2IMEM_LOAD_LOCKED_RESULT, 688 XUSB_CSB_MEMPOOL_L2IMEMOP_TRIG_ACTION)); 689 DPRINTF(sc->sc_dev, "XUSB_CSB_MP_L2IMEMOP_TRIG 0x%x\n", 690 csb_read_4(psc, XUSB_CSB_MEMPOOL_L2IMEMOP_TRIG_REG)); 691 692 DPRINTF(sc->sc_dev, "XUSB_FALC_IMFILLCTL 0x%x\n", 693 csb_read_4(psc, XUSB_CSB_FALCON_IMFILLCTL_REG)); 694 csb_write_4(psc, XUSB_CSB_FALCON_IMFILLCTL_REG, code_size_blocks); 695 DPRINTF(sc->sc_dev, "XUSB_FALC_IMFILLCTL 0x%x\n", 696 csb_read_4(psc, XUSB_CSB_FALCON_IMFILLCTL_REG)); 697 698 DPRINTF(sc->sc_dev, "XUSB_FALC_IMFILLRNG1 0x%x\n", 699 csb_read_4(psc, XUSB_CSB_FALCON_IMFILLRNG1_REG)); 700 csb_write_4(psc, XUSB_CSB_FALCON_IMFILLRNG1_REG, 701 __SHIFTIN(code_tag_blocks, XUSB_CSB_FALCON_IMFILLRNG1_TAG_LO) | 702 __SHIFTIN(code_blocks, XUSB_CSB_FALCON_IMFILLRNG1_TAG_HI)); 703 DPRINTF(sc->sc_dev, "XUSB_FALC_IMFILLRNG1 0x%x\n", 704 csb_read_4(psc, XUSB_CSB_FALCON_IMFILLRNG1_REG)); 705 706 DPRINTF(sc->sc_dev, "XUSB_FALC_DMACTL 0x%x\n", 707 csb_read_4(psc, XUSB_CSB_FALCON_DMACTL_REG)); 708 csb_write_4(psc, XUSB_CSB_FALCON_DMACTL_REG, 0); 709 DPRINTF(sc->sc_dev, "XUSB_FALC_DMACTL 0x%x\n", 710 csb_read_4(psc, XUSB_CSB_FALCON_DMACTL_REG)); 711 712 DPRINTF(sc->sc_dev, "XUSB_FALC_BOOTVEC 0x%x\n", 713 csb_read_4(psc, XUSB_CSB_FALCON_BOOTVEC_REG)); 714 csb_write_4(psc, XUSB_CSB_FALCON_BOOTVEC_REG, 715 boot_codetag); 716 DPRINTF(sc->sc_dev, "XUSB_FALC_BOOTVEC 0x%x\n", 717 csb_read_4(psc, XUSB_CSB_FALCON_BOOTVEC_REG)); 718 719 DPRINTF(sc->sc_dev, "XUSB_FALC_CPUCTL 0x%x\n", 720 csb_read_4(psc, XUSB_CSB_FALCON_CPUCTL_REG)); 721 csb_write_4(psc, XUSB_CSB_FALCON_CPUCTL_REG, 722 XUSB_CSB_FALCON_CPUCTL_STARTCPU); 723 DPRINTF(sc->sc_dev, "XUSB_FALC_CPUCTL 0x%x\n", 724 csb_read_4(psc, XUSB_CSB_FALCON_CPUCTL_REG)); 725 726 return 0; 727 } 728 729 static uint32_t 730 csb_read_4(struct tegra_xusb_softc * const psc, bus_size_t csb_offset) 731 { 732 const uint32_t range = __SHIFTOUT(csb_offset, XUSB_CSB_RANGE); 733 const bus_size_t offset = __SHIFTOUT(csb_offset, XUSB_CSB_OFFSET); 734 const bus_space_tag_t bst = psc->sc_xhci.sc_iot; 735 const bus_space_handle_t fpcih = psc->sc_bsh_fpci; 736 737 bus_space_write_4(bst, fpcih, T_XUSB_CFG_ARU_C11_CSBRANGE_REG, range); 738 return bus_space_read_4(bst, fpcih, T_XUSB_CFG_CSB_BASE_ADDR + offset); 739 } 740 741 static void 742 csb_write_4(struct tegra_xusb_softc * const psc, bus_size_t csb_offset, 743 uint32_t value) 744 { 745 const uint32_t range = __SHIFTOUT(csb_offset, XUSB_CSB_RANGE); 746 const bus_size_t offset = __SHIFTOUT(csb_offset, XUSB_CSB_OFFSET); 747 const bus_space_tag_t bst = psc->sc_xhci.sc_iot; 748 const bus_space_handle_t fpcih = psc->sc_bsh_fpci; 749 750 bus_space_write_4(bst, fpcih, T_XUSB_CFG_ARU_C11_CSBRANGE_REG, range); 751 bus_space_write_4(bst, fpcih, T_XUSB_CFG_CSB_BASE_ADDR + offset, value); 752 } 753 754 static int 755 xusb_mailbox_send(struct tegra_xusb_softc * const psc, uint32_t msg) 756 { 757 struct xhci_softc * const sc = &psc->sc_xhci; 758 const bus_space_tag_t bst = psc->sc_xhci.sc_iot; 759 const bus_space_handle_t fpcih = psc->sc_bsh_fpci; 760 uint32_t val; 761 bool wait = false; 762 763 const uint8_t type = __SHIFTOUT(msg, MAILBOX_DATA_TYPE); 764 765 if (!(type == 128 || type == 129)) { 766 val = bus_space_read_4(bst, fpcih, 767 T_XUSB_CFG_ARU_MAILBOX_OWNER_REG); 768 DPRINTF(sc->sc_dev, "XUSB_CFG_ARU_MBOX_OWNER 0x%x\n", 769 val); 770 if (val != MAILBOX_OWNER_NONE) { 771 return EBUSY; 772 } 773 774 bus_space_write_4(bst, fpcih, T_XUSB_CFG_ARU_MAILBOX_OWNER_REG, 775 MAILBOX_OWNER_SW); 776 777 val = bus_space_read_4(bst, fpcih, 778 T_XUSB_CFG_ARU_MAILBOX_OWNER_REG); 779 DPRINTF(sc->sc_dev, "XUSB_CFG_ARU_MBOX_OWNER 0x%x\n", 780 val); 781 if (val != MAILBOX_OWNER_SW) { 782 return EBUSY; 783 } 784 785 wait = true; 786 } 787 788 bus_space_write_4(bst, fpcih, T_XUSB_CFG_ARU_MAILBOX_DATA_IN_REG, msg); 789 790 tegra_reg_set_clear(bst, fpcih, T_XUSB_CFG_ARU_MAILBOX_CMD_REG, 791 T_XUSB_CFG_ARU_MAILBOX_CMD_INT_EN | 792 T_XUSB_CFG_ARU_MAILBOX_CMD_DEST_FALCON, 0); 793 794 if (wait) { 795 796 for (u_int i = 0; i < 2500; i++) { 797 val = bus_space_read_4(bst, fpcih, 798 T_XUSB_CFG_ARU_MAILBOX_OWNER_REG); 799 DPRINTF(sc->sc_dev, 800 "XUSB_CFG_ARU_MBOX_OWNER 0x%x\n", val); 801 if (val == MAILBOX_OWNER_NONE) { 802 break; 803 } 804 DELAY(10); 805 } 806 807 val = bus_space_read_4(bst, fpcih, 808 T_XUSB_CFG_ARU_MAILBOX_OWNER_REG); 809 DPRINTF(sc->sc_dev, 810 "XUSB_CFG_ARU_MBOX_OWNER 0x%x\n", val); 811 if (val != MAILBOX_OWNER_NONE) { 812 aprint_error_dev(sc->sc_dev, 813 "timeout, XUSB_CFG_ARU_MBOX_OWNER 0x%x\n", val); 814 } 815 } 816 817 return 0; 818 } 819
Indexes created Sat Sep 27 22:09:54 GMT 2025