tegra_xusb.c revision 1.7
1 /* $NetBSD: tegra_xusb.c,v 1.7 2017/09/19 20:46:12 jmcneill Exp $ */ 2 3 /* 4 * Copyright (c) 2016 Jonathan A. Kollasch 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR 20 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 21 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 22 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 23 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 25 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 26 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include "locators.h" 30 #include "opt_tegra.h" 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: tegra_xusb.c,v 1.7 2017/09/19 20:46:12 jmcneill Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/bus.h> 37 #include <sys/device.h> 38 #include <sys/intr.h> 39 #include <sys/systm.h> 40 #include <sys/kernel.h> 41 42 #include <arm/nvidia/tegra_reg.h> 43 #include <arm/nvidia/tegra_var.h> 44 #include <arm/nvidia/tegra_xusbpad.h> 45 46 #include <arm/nvidia/tegra_xusbreg.h> 47 #include <dev/pci/pcireg.h> 48 49 #include <dev/fdt/fdtvar.h> 50 51 #include <dev/firmload.h> 52 53 #include <dev/usb/usb.h> 54 #include <dev/usb/usbdi.h> 55 #include <dev/usb/usbdivar.h> 56 #include <dev/usb/usb_mem.h> 57 58 #include <dev/usb/xhcireg.h> 59 #include <dev/usb/xhcivar.h> 60 61 #ifdef TEGRA_XUSB_DEBUG 62 int tegra_xusb_debug = 1; 63 #else 64 int tegra_xusb_debug = 0; 65 #endif 66 67 #define DPRINTF(...) if (tegra_xusb_debug) device_printf(__VA_ARGS__) 68 69 static int tegra_xusb_match(device_t, cfdata_t, void *); 70 static void tegra_xusb_attach(device_t, device_t, void *); 71 static void tegra_xusb_mountroot(device_t); 72 73 static int tegra_xusb_intr_mbox(void *); 74 75 #ifdef TEGRA124_XUSB_BIN_STATIC 76 extern const char _binary_tegra124_xusb_bin_size[]; 77 extern const char _binary_tegra124_xusb_bin_start[]; 78 #endif 79 80 #ifdef TEGRA210_XUSB_BIN_STATIC 81 extern const char _binary_tegra210_xusb_bin_size[]; 82 extern const char _binary_tegra210_xusb_bin_start[]; 83 #endif 84 85 enum xusb_type { 86 XUSB_T124 = 1, 87 XUSB_T210 88 }; 89 90 static const struct of_compat_data compat_data[] = { 91 { "nvidia,tegra124-xusb", XUSB_T124 }, 92 #if notyet 93 { "nvidia,tegra210-xusb", XUSB_T210 }, 94 #endif 95 { NULL } 96 }; 97 98 struct fw_dma { 99 bus_dmamap_t map; 100 void * addr; 101 bus_dma_segment_t segs[1]; 102 int nsegs; 103 size_t size; 104 }; 105 106 struct tegra_xusb_softc { 107 struct xhci_softc sc_xhci; 108 int sc_phandle; 109 bus_space_handle_t sc_bsh_xhci; 110 bus_space_handle_t sc_bsh_fpci; 111 bus_space_handle_t sc_bsh_ipfs; 112 void *sc_ih; 113 void *sc_ih_mbox; 114 struct fw_dma sc_fw_dma; 115 struct clk *sc_clk_ss_src; 116 enum xusb_type sc_type; 117 }; 118 119 static uint32_t csb_read_4(struct tegra_xusb_softc * const, bus_size_t); 120 static void csb_write_4(struct tegra_xusb_softc * const, bus_size_t, 121 uint32_t); 122 123 static void tegra_xusb_init(struct tegra_xusb_softc * const); 124 static int tegra_xusb_open_fw(struct tegra_xusb_softc * const); 125 static int tegra_xusb_load_fw(struct tegra_xusb_softc * const, void *, 126 size_t); 127 128 static int xusb_mailbox_send(struct tegra_xusb_softc * const, uint32_t); 129 130 CFATTACH_DECL_NEW(tegra_xusb, sizeof(struct tegra_xusb_softc), 131 tegra_xusb_match, tegra_xusb_attach, NULL, NULL); 132 133 static int 134 tegra_xusb_match(device_t parent, cfdata_t cf, void *aux) 135 { 136 struct fdt_attach_args * const faa = aux; 137 138 return of_match_compat_data(faa->faa_phandle, compat_data); 139 } 140 141 #define tegra_xusb_attach_check(sc, cond, fmt, ...) \ 142 do { \ 143 if (cond) { \ 144 aprint_error_dev(sc->sc_dev, fmt, ## __VA_ARGS__); \ 145 return; \ 146 } \ 147 } while (0) 148 149 static void 150 tegra_xusb_attach(device_t parent, device_t self, void *aux) 151 { 152 struct tegra_xusb_softc * const psc = device_private(self); 153 struct xhci_softc * const sc = &psc->sc_xhci; 154 struct fdt_attach_args * const faa = aux; 155 bool wait_for_root = true; 156 char intrstr[128]; 157 bus_addr_t addr; 158 bus_size_t size; 159 struct fdtbus_reset *rst; 160 struct clk *clk; 161 uint32_t rate; 162 int error; 163 164 aprint_naive("\n"); 165 aprint_normal(": XUSB\n"); 166 167 sc->sc_dev = self; 168 sc->sc_iot = faa->faa_bst; 169 sc->sc_bus.ub_hcpriv = sc; 170 sc->sc_bus.ub_dmatag = faa->faa_dmat; 171 psc->sc_phandle = faa->faa_phandle; 172 psc->sc_type = of_search_compatible(faa->faa_phandle, compat_data)->data; 173 174 if (fdtbus_get_reg(faa->faa_phandle, 0, &addr, &size) != 0) { 175 aprint_error(": couldn't get registers\n"); 176 return; 177 } 178 error = bus_space_map(sc->sc_iot, addr, size, 0, &sc->sc_ioh); 179 if (error) { 180 aprint_error(": couldn't map %#llx: %d", (uint64_t)addr, error); 181 return; 182 } 183 DPRINTF(sc->sc_dev, "mapped %#llx\n", (uint64_t)addr); 184 185 if (fdtbus_get_reg(faa->faa_phandle, 1, &addr, &size) != 0) { 186 aprint_error(": couldn't get registers\n"); 187 return; 188 } 189 error = bus_space_map(sc->sc_iot, addr, size, 0, &psc->sc_bsh_fpci); 190 if (error) { 191 aprint_error(": couldn't map %#llx: %d", (uint64_t)addr, error); 192 return; 193 } 194 DPRINTF(sc->sc_dev, "mapped %#llx\n", (uint64_t)addr); 195 196 if (fdtbus_get_reg(faa->faa_phandle, 2, &addr, &size) != 0) { 197 aprint_error(": couldn't get registers\n"); 198 return; 199 } 200 error = bus_space_map(sc->sc_iot, addr, size, 0, &psc->sc_bsh_ipfs); 201 if (error) { 202 aprint_error(": couldn't map %#llx: %d", (uint64_t)addr, error); 203 return; 204 } 205 DPRINTF(sc->sc_dev, "mapped %#llx\n", (uint64_t)addr); 206 207 if (!fdtbus_intr_str(faa->faa_phandle, 0, intrstr, sizeof(intrstr))) { 208 aprint_error_dev(self, "failed to decode interrupt\n"); 209 return; 210 } 211 212 psc->sc_ih = fdtbus_intr_establish(faa->faa_phandle, 0, IPL_USB, 213 0, xhci_intr, sc); 214 if (psc->sc_ih == NULL) { 215 aprint_error_dev(self, "failed to establish interrupt on %s\n", 216 intrstr); 217 return; 218 } 219 aprint_normal_dev(self, "interrupting on %s\n", intrstr); 220 221 if (!fdtbus_intr_str(faa->faa_phandle, 1, intrstr, sizeof(intrstr))) { 222 aprint_error_dev(self, "failed to decode interrupt\n"); 223 return; 224 } 225 226 psc->sc_ih_mbox = fdtbus_intr_establish(faa->faa_phandle, 1, IPL_VM, 227 0, tegra_xusb_intr_mbox, psc); 228 if (psc->sc_ih_mbox == NULL) { 229 aprint_error_dev(self, "failed to establish interrupt on %s\n", 230 intrstr); 231 return; 232 } 233 aprint_normal_dev(self, "interrupting on %s\n", intrstr); 234 235 clk = fdtbus_clock_get(faa->faa_phandle, "pll_e"); 236 rate = clk_get_rate(clk); 237 error = clk_enable(clk); /* XXX set frequency */ 238 DPRINTF(sc->sc_dev, "rate %u error %d\n", rate, error); 239 tegra_xusb_attach_check(sc, error, "failed to enable pll_e clock"); 240 241 clk = fdtbus_clock_get(faa->faa_phandle, "xusb_host_src"); 242 rate = clk_get_rate(clk); 243 DPRINTF(sc->sc_dev, "rate %u error %d\n", rate, error); 244 error = clk_set_rate(clk, 102000000); 245 tegra_xusb_attach_check(sc, error, "failed to set xusb_host_src clock rate"); 246 247 rate = clk_get_rate(clk); 248 error = clk_enable(clk); /* XXX set frequency */ 249 DPRINTF(sc->sc_dev, "rate %u error %d\n", rate, error); 250 tegra_xusb_attach_check(sc, error, "failed to enable xusb_host_src clock"); 251 252 clk = fdtbus_clock_get(faa->faa_phandle, "xusb_falcon_src"); 253 rate = clk_get_rate(clk); 254 DPRINTF(sc->sc_dev, "rate %u error %d\n", rate, error); 255 error = clk_set_rate(clk, 204000000); 256 tegra_xusb_attach_check(sc, error, "failed to set xusb_falcon_src clock rate"); 257 258 rate = clk_get_rate(clk); 259 error = clk_enable(clk); 260 DPRINTF(sc->sc_dev, "rate %u error %d\n", rate, error); 261 tegra_xusb_attach_check(sc, error, "failed to enable xusb_falcon_src clock"); 262 263 clk = fdtbus_clock_get(faa->faa_phandle, "xusb_host"); 264 rate = clk_get_rate(clk); 265 error = clk_enable(clk); /* XXX set frequency */ 266 DPRINTF(sc->sc_dev, "rate %u error %d\n", rate, error); 267 268 clk = fdtbus_clock_get(faa->faa_phandle, "xusb_ss"); 269 rate = clk_get_rate(clk); 270 error = clk_enable(clk); /* XXX set frequency */ 271 DPRINTF(sc->sc_dev, "xusb_ss rate %u error %d\n", rate, error); 272 tegra_xusb_attach_check(sc, error, "failed to enable xusb_ss clock"); 273 274 psc->sc_clk_ss_src = fdtbus_clock_get(faa->faa_phandle, "xusb_ss_src"); 275 tegra_xusb_attach_check(sc, psc->sc_clk_ss_src == NULL, 276 "failed to get xusb_ss_src clock"); 277 278 if (psc->sc_type == XUSB_T124) { 279 rate = clk_get_rate(psc->sc_clk_ss_src); 280 DPRINTF(sc->sc_dev, "xusb_ss_src rate %u\n", rate); 281 error = clk_set_rate(psc->sc_clk_ss_src, 2000000); 282 rate = clk_get_rate(psc->sc_clk_ss_src); 283 DPRINTF(sc->sc_dev, "xusb_ss_src rate %u error %d\n", rate, error); 284 tegra_xusb_attach_check(sc, error, "failed to get xusb_ss_src clock rate"); 285 286 rate = clk_get_rate(psc->sc_clk_ss_src); 287 DPRINTF(sc->sc_dev, "ss_src rate %u\n", rate); 288 tegra_xusb_attach_check(sc, error, "failed to set xusb_ss_src clock rate"); 289 290 error = clk_set_rate(psc->sc_clk_ss_src, 120000000); 291 rate = clk_get_rate(psc->sc_clk_ss_src); 292 DPRINTF(sc->sc_dev, "ss_src rate %u error %d\n", rate, error); 293 tegra_xusb_attach_check(sc, error, "failed to get xusb_ss_src clock rate"); 294 } 295 296 rate = clk_get_rate(psc->sc_clk_ss_src); 297 error = clk_enable(psc->sc_clk_ss_src); 298 DPRINTF(sc->sc_dev, "ss_src rate %u error %d\n", rate, error); 299 tegra_xusb_attach_check(sc, error, "failed to enable xusb_ss_src clock"); 300 301 #if 0 302 clk = fdtbus_clock_get(faa->faa_phandle, "xusb_hs_src"); 303 error = 0; 304 rate = clk_get_rate(clk); 305 DPRINTF(sc->sc_dev, "rate %u error %d\n", rate, error); 306 #endif 307 308 clk = fdtbus_clock_get(faa->faa_phandle, "xusb_fs_src"); 309 rate = clk_get_rate(clk); 310 error = clk_enable(clk); /* XXX set frequency */ 311 DPRINTF(sc->sc_dev, "rate %u error %d\n", rate, error); 312 tegra_xusb_attach_check(sc, error, "failed to enable xusb_fs_src clock"); 313 314 rst = fdtbus_reset_get(faa->faa_phandle, "xusb_host"); 315 fdtbus_reset_deassert(rst); 316 317 rst = fdtbus_reset_get(faa->faa_phandle, "xusb_src"); 318 fdtbus_reset_deassert(rst); 319 320 rst = fdtbus_reset_get(faa->faa_phandle, "xusb_ss"); 321 fdtbus_reset_deassert(rst); 322 323 DELAY(1); 324 325 tegra_xusb_init(psc); 326 327 #if defined(TEGRA124_XUSB_BIN_STATIC) 328 if (psc->sc_type == XUSB_T124) 329 wait_for_root = false; 330 #endif 331 #if defined(TEGRA210_XUSB_BIN_STATIC) 332 if (psc->sc_type == XUSB_T210) 333 wait_for_root = false; 334 #endif 335 336 if (wait_for_root) 337 config_mountroot(sc->sc_dev, tegra_xusb_mountroot); 338 else 339 tegra_xusb_mountroot(sc->sc_dev); 340 } 341 342 static void 343 tegra_xusb_mountroot(device_t self) 344 { 345 struct tegra_xusb_softc * const psc = device_private(self); 346 struct xhci_softc * const sc = &psc->sc_xhci; 347 const bus_space_tag_t bst = sc->sc_iot; 348 const bus_space_handle_t ipfsh = psc->sc_bsh_ipfs; 349 struct clk *clk; 350 struct fdtbus_reset *rst; 351 uint32_t rate; 352 uint32_t val; 353 int error; 354 355 DPRINTF(sc->sc_dev, "%s()\n", __func__); 356 357 val = bus_space_read_4(bst, ipfsh, 0x0); 358 DPRINTF(sc->sc_dev, "%s ipfs 0x0 = 0x%x\n", __func__, val); 359 360 if (tegra_xusb_open_fw(psc) != 0) 361 return; 362 DPRINTF(sc->sc_dev, "post fw\n"); 363 364 tegra_xusbpad_xhci_enable(); 365 366 clk = fdtbus_clock_get(psc->sc_phandle, "xusb_falcon_src"); 367 rate = clk_get_rate(clk); 368 error = clk_enable(clk); 369 DPRINTF(sc->sc_dev, "rate %u error %d\n", rate, error); 370 371 clk = fdtbus_clock_get(psc->sc_phandle, "xusb_host_src"); 372 rate = clk_get_rate(clk); 373 error = clk_enable(clk); 374 DPRINTF(sc->sc_dev, "rate %u error %d\n", rate, error); 375 376 val = bus_space_read_4(bst, ipfsh, 0x0); 377 DPRINTF(sc->sc_dev, "%s ipfs 0x0 = 0x%x\n", __func__, val); 378 379 rst = fdtbus_reset_get(psc->sc_phandle, "xusb_host"); 380 fdtbus_reset_deassert(rst); 381 382 rst = fdtbus_reset_get(psc->sc_phandle, "xusb_src"); 383 fdtbus_reset_deassert(rst); 384 385 rst = fdtbus_reset_get(psc->sc_phandle, "xusb_ss"); 386 fdtbus_reset_deassert(rst); 387 388 val = csb_read_4(psc, XUSB_CSB_FALCON_CPUCTL_REG); 389 DPRINTF(sc->sc_dev, "XUSB_FALC_CPUCTL 0x%x\n", val); 390 391 392 error = xhci_init(sc); 393 if (error) { 394 aprint_error_dev(self, "init failed, error=%d\n", error); 395 return; 396 } 397 398 sc->sc_child = config_found(self, &sc->sc_bus, usbctlprint); 399 400 sc->sc_child2 = config_found(self, &sc->sc_bus2, usbctlprint); 401 402 error = xusb_mailbox_send(psc, 0x01000000); 403 if (error) { 404 aprint_error_dev(self, "send failed, error=%d\n", error); 405 } 406 } 407 408 static int 409 tegra_xusb_intr_mbox(void *v) 410 { 411 struct tegra_xusb_softc * const psc = v; 412 struct xhci_softc * const sc = &psc->sc_xhci; 413 const bus_space_tag_t bst = sc->sc_iot; 414 const bus_space_handle_t fpcih = psc->sc_bsh_fpci; 415 uint32_t val; 416 uint32_t irv; 417 uint32_t msg; 418 int error; 419 420 DPRINTF(sc->sc_dev, "%s()\n", __func__); 421 422 irv = bus_space_read_4(bst, fpcih, T_XUSB_CFG_ARU_SMI_INTR_REG); 423 DPRINTF(sc->sc_dev, "XUSB_CFG_ARU_SMI_INTR 0x%x\n", irv); 424 bus_space_write_4(bst, fpcih, T_XUSB_CFG_ARU_SMI_INTR_REG, irv); 425 426 if (irv & T_XUSB_CFG_ARU_SMI_INTR_FW_HANG) 427 aprint_error_dev(sc->sc_dev, "firmware hang\n"); 428 429 msg = bus_space_read_4(bst, fpcih, T_XUSB_CFG_ARU_MAILBOX_DATA_OUT_REG); 430 DPRINTF(sc->sc_dev, "XUSB_CFG_ARU_MBOX_DATA_OUT 0x%x\n", msg); 431 432 val = bus_space_read_4(bst, fpcih, T_XUSB_CFG_ARU_MAILBOX_CMD_REG); 433 DPRINTF(sc->sc_dev, "XUSB_CFG_ARU_MBOX_CMD 0x%x\n", val); 434 val &= ~T_XUSB_CFG_ARU_MAILBOX_CMD_DEST_SMI; 435 bus_space_write_4(bst, fpcih, T_XUSB_CFG_ARU_MAILBOX_CMD_REG, val); 436 437 bool sendresp = true; 438 u_int rate; 439 440 const uint32_t data = __SHIFTOUT(msg, MAILBOX_DATA_DATA); 441 const uint8_t type = __SHIFTOUT(msg, MAILBOX_DATA_TYPE); 442 443 switch (type) { 444 case 2: 445 case 3: 446 DPRINTF(sc->sc_dev, "FALC_CLOCK %u\n", data * 1000); 447 break; 448 case 4: 449 case 5: 450 DPRINTF(sc->sc_dev, "SSPI_CLOCK %u\n", data * 1000); 451 rate = clk_get_rate(psc->sc_clk_ss_src); 452 DPRINTF(sc->sc_dev, "rate of psc->sc_clk_ss_src %u\n", 453 rate); 454 error = clk_set_rate(psc->sc_clk_ss_src, data * 1000); 455 if (error != 0) 456 goto clk_fail; 457 rate = clk_get_rate(psc->sc_clk_ss_src); 458 DPRINTF(sc->sc_dev, 459 "rate of psc->sc_clk_ss_src %u after\n", rate); 460 if (data == (rate / 1000)) { 461 msg = __SHIFTIN(128, MAILBOX_DATA_TYPE) | 462 __SHIFTIN(rate / 1000, MAILBOX_DATA_DATA); 463 } else 464 clk_fail: 465 msg = __SHIFTIN(129, MAILBOX_DATA_TYPE) | 466 __SHIFTIN(rate / 1000, MAILBOX_DATA_DATA); 467 xusb_mailbox_send(psc, msg); 468 break; 469 case 9: 470 msg = __SHIFTIN(data, MAILBOX_DATA_DATA) | 471 __SHIFTIN(128, MAILBOX_DATA_TYPE); 472 xusb_mailbox_send(psc, msg); 473 break; 474 case 6: 475 case 128: 476 case 129: 477 sendresp = false; 478 break; 479 default: 480 sendresp = false; 481 break; 482 } 483 484 if (sendresp == false) 485 bus_space_write_4(bst, fpcih, T_XUSB_CFG_ARU_MAILBOX_OWNER_REG, 486 MAILBOX_OWNER_NONE); 487 488 return irv; 489 } 490 491 static void 492 tegra_xusb_init(struct tegra_xusb_softc * const psc) 493 { 494 struct xhci_softc * const sc = &psc->sc_xhci; 495 const bus_space_tag_t bst = sc->sc_iot; 496 const bus_space_handle_t ipfsh = psc->sc_bsh_ipfs; 497 const bus_space_handle_t fpcih = psc->sc_bsh_fpci; 498 499 DPRINTF(sc->sc_dev, "%s()\n", __func__); 500 501 DPRINTF(sc->sc_dev, "%s ipfs 0x0 = 0x%x\n", __func__, 502 bus_space_read_4(bst, ipfsh, 0x0)); 503 504 DPRINTF(sc->sc_dev, "%s ipfs 0x40 = 0x%x\n", __func__, 505 bus_space_read_4(bst, ipfsh, 0x40)); 506 507 DPRINTF(sc->sc_dev, "%s ipfs 0x80 = 0x%x\n", __func__, 508 bus_space_read_4(bst, ipfsh, 0x80)); 509 /* FPCI_BAR0_START and FPCI_BAR0_ACCESS_TYPE */ 510 bus_space_write_4(bst, ipfsh, 0x80, 0x00100000); 511 DPRINTF(sc->sc_dev, "%s ipfs 0x80 = 0x%x\n", __func__, 512 bus_space_read_4(bst, ipfsh, 0x80)); 513 514 DPRINTF(sc->sc_dev, "%s ipfs 0x180 = 0x%x\n", __func__, 515 bus_space_read_4(bst, ipfsh, 0x180)); 516 /* EN_FPCI */ 517 tegra_reg_set_clear(bst, ipfsh, 0x180, 1, 0); 518 DPRINTF(sc->sc_dev, "%s ipfs 0x180 = 0x%x\n", __func__, 519 bus_space_read_4(bst, ipfsh, 0x180)); 520 521 DPRINTF(sc->sc_dev, "%s fpci PCI_COMMAND_STATUS_REG = 0x%x\n", 522 __func__, bus_space_read_4(bst, fpcih, PCI_COMMAND_STATUS_REG)); 523 tegra_reg_set_clear(bst, fpcih, PCI_COMMAND_STATUS_REG, 524 PCI_COMMAND_MASTER_ENABLE|PCI_COMMAND_MEM_ENABLE, 0x0); 525 DPRINTF(sc->sc_dev, "%s fpci PCI_COMMAND_STATUS_REG = 0x%x\n", 526 __func__, bus_space_read_4(bst, fpcih, PCI_COMMAND_STATUS_REG)); 527 528 DPRINTF(sc->sc_dev, "%s fpci PCI_BAR0 = 0x%x\n", __func__, 529 bus_space_read_4(bst, fpcih, PCI_BAR0)); 530 /* match FPCI BAR0 to above */ 531 bus_space_write_4(bst, fpcih, PCI_BAR0, 0x10000000); 532 DPRINTF(sc->sc_dev, "%s fpci PCI_BAR0 = 0x%x\n", __func__, 533 bus_space_read_4(bst, fpcih, PCI_BAR0)); 534 535 DPRINTF(sc->sc_dev, "%s ipfs 0x188 = 0x%x\n", __func__, 536 bus_space_read_4(bst, ipfsh, 0x188)); 537 tegra_reg_set_clear(bst, ipfsh, 0x188, __BIT(16), 0); 538 DPRINTF(sc->sc_dev, "%s ipfs 0x188 = 0x%x\n", __func__, 539 bus_space_read_4(bst, ipfsh, 0x188)); 540 541 DPRINTF(sc->sc_dev, "%s fpci 0x1bc = 0x%x\n", __func__, 542 bus_space_read_4(bst, fpcih, 0x1bc)); 543 bus_space_write_4(bst, fpcih, 0x1bc, 0x80); 544 DPRINTF(sc->sc_dev, "%s fpci 0x1bc = 0x%x\n", __func__, 545 bus_space_read_4(bst, fpcih, 0x1bc)); 546 } 547 548 static int 549 fw_dma_alloc(struct tegra_xusb_softc * const psc, size_t size, size_t align, 550 struct fw_dma * const p) 551 { 552 struct xhci_softc * const sc = &psc->sc_xhci; 553 const bus_dma_tag_t dmat = sc->sc_bus.ub_dmatag; 554 int err; 555 556 p->size = size; 557 err = bus_dmamem_alloc(dmat, p->size, align, 0, p->segs, 558 sizeof(p->segs) / sizeof(p->segs[0]), &p->nsegs, BUS_DMA_NOWAIT); 559 if (err) 560 return err; 561 err = bus_dmamem_map(dmat, p->segs, p->nsegs, p->size, &p->addr, 562 BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 563 if (err) 564 goto free; 565 err = bus_dmamap_create(dmat, p->size, 1, p->size, 0, BUS_DMA_NOWAIT, 566 &p->map); 567 if (err) 568 goto unmap; 569 err = bus_dmamap_load(dmat, p->map, p->addr, p->size, NULL, 570 BUS_DMA_NOWAIT); 571 if (err) 572 goto destroy; 573 574 return 0; 575 576 destroy: 577 bus_dmamap_destroy(dmat, p->map); 578 unmap: 579 bus_dmamem_unmap(dmat, p->addr, p->size); 580 free: 581 bus_dmamem_free(dmat, p->segs, p->nsegs); 582 583 return err; 584 } 585 586 #if !defined(TEGRA124_XUSB_BIN_STATIC) 587 static void 588 fw_dma_free(struct tegra_xusb_softc * const psc, struct fw_dma * const p) 589 { 590 const struct xhci_softc * const sc = &psc->sc_xhci; 591 const bus_dma_tag_t dmat = sc->sc_bus.ub_dmatag; 592 593 bus_dmamap_unload(dmat, p->map); 594 bus_dmamap_destroy(dmat, p->map); 595 bus_dmamem_unmap(dmat, p->addr, p->size); 596 bus_dmamem_free(dmat, p->segs, p->nsegs); 597 } 598 #endif 599 600 #define FWHEADER_BOOT_CODETAG 8 601 #define FWHEADER_BOOT_CODESIZE 12 602 #define FWHEADER_FWIMG_LEN 100 603 #define FWHEADER__LEN 256 604 605 static int 606 tegra_xusb_open_fw(struct tegra_xusb_softc * const psc) 607 { 608 struct xhci_softc * const sc = &psc->sc_xhci; 609 firmware_handle_t fw; 610 size_t firmware_size = 0; 611 void *firmware_image; 612 const char *fw_path = NULL; 613 void *fw_static = NULL; 614 int error; 615 616 switch (psc->sc_type) { 617 case XUSB_T124: 618 #if defined(TEGRA124_XUSB_BIN_STATIC) 619 firmware_size = (uintptr_t)&_binary_tegra124_xusb_bin_size; 620 fw_static = _binary_tegra124_xusb_bin_start; 621 #else 622 fw_path = "nvidia/tegra124"; 623 #endif 624 break; 625 case XUSB_T210: 626 #if defined(TEGRA210_XUSB_BIN_STATIC) 627 firmware_size = (uintptr_t)&_binary_tegra210_xusb_bin_size; 628 fw_static = _binary_tegra210_xusb_bin_start; 629 #else 630 fw_path = "nvidia/tegra210"; 631 #endif 632 break; 633 default: 634 return EINVAL; 635 } 636 637 if (fw_path != NULL) { 638 error = firmware_open(fw_path, "xusb.bin", &fw); 639 if (error != 0) { 640 aprint_error_dev(sc->sc_dev, 641 "couldn't load firmware from %s/xusb.bin: %d\n", 642 fw_path, error); 643 return error; 644 } 645 firmware_size = firmware_get_size(fw); 646 } 647 648 error = fw_dma_alloc(psc, firmware_size, PAGE_SIZE, 649 &psc->sc_fw_dma); 650 if (error != 0) 651 return error; 652 firmware_image = psc->sc_fw_dma.addr; 653 654 if (fw_path != NULL) { 655 error = firmware_read(fw, 0, firmware_image, firmware_size); 656 if (error != 0) { 657 fw_dma_free(psc, &psc->sc_fw_dma); 658 firmware_close(fw); 659 return error; 660 } 661 firmware_close(fw); 662 } else { 663 memcpy(firmware_image, fw_static, firmware_size); 664 } 665 666 return tegra_xusb_load_fw(psc, firmware_image, firmware_size); 667 } 668 669 static int 670 tegra_xusb_load_fw(struct tegra_xusb_softc * const psc, void *firmware_image, 671 size_t firmware_size) 672 { 673 struct xhci_softc * const sc = &psc->sc_xhci; 674 const uint8_t *header; 675 676 header = firmware_image; 677 678 const uint32_t fwimg_len = le32dec(&header[FWHEADER_FWIMG_LEN]); 679 const uint32_t boot_codetag = le32dec(&header[FWHEADER_BOOT_CODETAG]); 680 const uint32_t boot_codesize = le32dec(&header[FWHEADER_BOOT_CODESIZE]); 681 682 if (fwimg_len != firmware_size) 683 aprint_error_dev(sc->sc_dev, "fwimg_len mismatch %u != %zu\n", 684 fwimg_len, firmware_size); 685 686 bus_dmamap_sync(sc->sc_bus.ub_dmatag, psc->sc_fw_dma.map, 0, 687 firmware_size, BUS_DMASYNC_PREWRITE); 688 689 DPRINTF(sc->sc_dev, "XUSB_FALC_CPUCTL 0x%x\n", 690 csb_read_4(psc, XUSB_CSB_FALCON_CPUCTL_REG)); 691 DPRINTF(sc->sc_dev, "XUSB_CSB_MP_ILOAD_BASE_LO 0x%x\n", 692 csb_read_4(psc, XUSB_CSB_MEMPOOL_ILOAD_BASE_LO_REG)); 693 694 DPRINTF(sc->sc_dev, "XUSB_CSB_MP_ILOAD_ATTR 0x%x\n", 695 csb_read_4(psc, XUSB_CSB_MEMPOOL_ILOAD_ATTR_REG)); 696 csb_write_4(psc, XUSB_CSB_MEMPOOL_ILOAD_ATTR_REG, 697 fwimg_len); 698 DPRINTF(sc->sc_dev, "XUSB_CSB_MP_ILOAD_ATTR 0x%x\n", 699 csb_read_4(psc, XUSB_CSB_MEMPOOL_ILOAD_ATTR_REG)); 700 701 const uint64_t fwbase = psc->sc_fw_dma.map->dm_segs[0].ds_addr + 702 FWHEADER__LEN; 703 704 csb_write_4(psc, XUSB_CSB_MEMPOOL_ILOAD_BASE_HI_REG, fwbase >> 32); 705 csb_write_4(psc, XUSB_CSB_MEMPOOL_ILOAD_BASE_LO_REG, fwbase); 706 DPRINTF(sc->sc_dev, "XUSB_CSB_MP_ILOAD_BASE_LO 0x%x\n", 707 csb_read_4(psc, XUSB_CSB_MEMPOOL_ILOAD_BASE_LO_REG)); 708 DPRINTF(sc->sc_dev, "XUSB_CSB_MP_ILOAD_BASE_HI 0x%x\n", 709 csb_read_4(psc, XUSB_CSB_MEMPOOL_ILOAD_BASE_HI_REG)); 710 711 DPRINTF(sc->sc_dev, "XUSB_CSB_MP_APMAP 0x%x\n", 712 csb_read_4(psc, XUSB_CSB_MEMPOOL_APMAP_REG)); 713 csb_write_4(psc, XUSB_CSB_MEMPOOL_APMAP_REG, 714 XUSB_CSB_MEMPOOL_APMAP_BOOTPATH); 715 DPRINTF(sc->sc_dev, "XUSB_CSB_MP_APMAP 0x%x\n", 716 csb_read_4(psc, XUSB_CSB_MEMPOOL_APMAP_REG)); 717 718 DPRINTF(sc->sc_dev, "XUSB_CSB_MP_L2IMEMOP_TRIG 0x%x\n", 719 csb_read_4(psc, XUSB_CSB_MEMPOOL_L2IMEMOP_TRIG_REG)); 720 csb_write_4(psc, XUSB_CSB_MEMPOOL_L2IMEMOP_TRIG_REG, 721 __SHIFTIN(ACTION_L2IMEM_INVALIDATE_ALL, 722 XUSB_CSB_MEMPOOL_L2IMEMOP_TRIG_ACTION)); 723 DPRINTF(sc->sc_dev, "XUSB_CSB_MP_L2IMEMOP_TRIG 0x%x\n", 724 csb_read_4(psc, XUSB_CSB_MEMPOOL_L2IMEMOP_TRIG_REG)); 725 726 const u_int code_tag_blocks = 727 howmany(boot_codetag, IMEM_BLOCK_SIZE); 728 const u_int code_size_blocks = 729 howmany(boot_codesize, IMEM_BLOCK_SIZE); 730 const u_int code_blocks = code_tag_blocks + code_size_blocks; 731 732 DPRINTF(sc->sc_dev, "XUSB_CSB_MP_L2IMEMOP_SIZE 0x%x\n", 733 csb_read_4(psc, XUSB_CSB_MEMPOOL_L2IMEMOP_SIZE_REG)); 734 csb_write_4(psc, XUSB_CSB_MEMPOOL_L2IMEMOP_SIZE_REG, 735 __SHIFTIN(code_tag_blocks, 736 XUSB_CSB_MEMPOOL_L2IMEMOP_SIZE_SRC_OFFSET) | 737 __SHIFTIN(code_size_blocks, 738 XUSB_CSB_MEMPOOL_L2IMEMOP_SIZE_SRC_COUNT)); 739 DPRINTF(sc->sc_dev, "XUSB_CSB_MP_L2IMEMOP_SIZE 0x%x\n", 740 csb_read_4(psc, XUSB_CSB_MEMPOOL_L2IMEMOP_SIZE_REG)); 741 742 DPRINTF(sc->sc_dev, "XUSB_CSB_MP_L2IMEMOP_TRIG 0x%x\n", 743 csb_read_4(psc, XUSB_CSB_MEMPOOL_L2IMEMOP_TRIG_REG)); 744 csb_write_4(psc, XUSB_CSB_MEMPOOL_L2IMEMOP_TRIG_REG, 745 __SHIFTIN(ACTION_L2IMEM_LOAD_LOCKED_RESULT, 746 XUSB_CSB_MEMPOOL_L2IMEMOP_TRIG_ACTION)); 747 DPRINTF(sc->sc_dev, "XUSB_CSB_MP_L2IMEMOP_TRIG 0x%x\n", 748 csb_read_4(psc, XUSB_CSB_MEMPOOL_L2IMEMOP_TRIG_REG)); 749 750 DPRINTF(sc->sc_dev, "XUSB_FALC_IMFILLCTL 0x%x\n", 751 csb_read_4(psc, XUSB_CSB_FALCON_IMFILLCTL_REG)); 752 csb_write_4(psc, XUSB_CSB_FALCON_IMFILLCTL_REG, code_size_blocks); 753 DPRINTF(sc->sc_dev, "XUSB_FALC_IMFILLCTL 0x%x\n", 754 csb_read_4(psc, XUSB_CSB_FALCON_IMFILLCTL_REG)); 755 756 DPRINTF(sc->sc_dev, "XUSB_FALC_IMFILLRNG1 0x%x\n", 757 csb_read_4(psc, XUSB_CSB_FALCON_IMFILLRNG1_REG)); 758 csb_write_4(psc, XUSB_CSB_FALCON_IMFILLRNG1_REG, 759 __SHIFTIN(code_tag_blocks, XUSB_CSB_FALCON_IMFILLRNG1_TAG_LO) | 760 __SHIFTIN(code_blocks, XUSB_CSB_FALCON_IMFILLRNG1_TAG_HI)); 761 DPRINTF(sc->sc_dev, "XUSB_FALC_IMFILLRNG1 0x%x\n", 762 csb_read_4(psc, XUSB_CSB_FALCON_IMFILLRNG1_REG)); 763 764 DPRINTF(sc->sc_dev, "XUSB_FALC_DMACTL 0x%x\n", 765 csb_read_4(psc, XUSB_CSB_FALCON_DMACTL_REG)); 766 csb_write_4(psc, XUSB_CSB_FALCON_DMACTL_REG, 0); 767 DPRINTF(sc->sc_dev, "XUSB_FALC_DMACTL 0x%x\n", 768 csb_read_4(psc, XUSB_CSB_FALCON_DMACTL_REG)); 769 770 DPRINTF(sc->sc_dev, "XUSB_FALC_BOOTVEC 0x%x\n", 771 csb_read_4(psc, XUSB_CSB_FALCON_BOOTVEC_REG)); 772 csb_write_4(psc, XUSB_CSB_FALCON_BOOTVEC_REG, 773 boot_codetag); 774 DPRINTF(sc->sc_dev, "XUSB_FALC_BOOTVEC 0x%x\n", 775 csb_read_4(psc, XUSB_CSB_FALCON_BOOTVEC_REG)); 776 777 DPRINTF(sc->sc_dev, "XUSB_FALC_CPUCTL 0x%x\n", 778 csb_read_4(psc, XUSB_CSB_FALCON_CPUCTL_REG)); 779 csb_write_4(psc, XUSB_CSB_FALCON_CPUCTL_REG, 780 XUSB_CSB_FALCON_CPUCTL_STARTCPU); 781 DPRINTF(sc->sc_dev, "XUSB_FALC_CPUCTL 0x%x\n", 782 csb_read_4(psc, XUSB_CSB_FALCON_CPUCTL_REG)); 783 784 return 0; 785 } 786 787 static uint32_t 788 csb_read_4(struct tegra_xusb_softc * const psc, bus_size_t csb_offset) 789 { 790 const uint32_t range = __SHIFTOUT(csb_offset, XUSB_CSB_RANGE); 791 const bus_size_t offset = __SHIFTOUT(csb_offset, XUSB_CSB_OFFSET); 792 const bus_space_tag_t bst = psc->sc_xhci.sc_iot; 793 const bus_space_handle_t fpcih = psc->sc_bsh_fpci; 794 795 bus_space_write_4(bst, fpcih, T_XUSB_CFG_ARU_C11_CSBRANGE_REG, range); 796 return bus_space_read_4(bst, fpcih, T_XUSB_CFG_CSB_BASE_ADDR + offset); 797 } 798 799 static void 800 csb_write_4(struct tegra_xusb_softc * const psc, bus_size_t csb_offset, 801 uint32_t value) 802 { 803 const uint32_t range = __SHIFTOUT(csb_offset, XUSB_CSB_RANGE); 804 const bus_size_t offset = __SHIFTOUT(csb_offset, XUSB_CSB_OFFSET); 805 const bus_space_tag_t bst = psc->sc_xhci.sc_iot; 806 const bus_space_handle_t fpcih = psc->sc_bsh_fpci; 807 808 bus_space_write_4(bst, fpcih, T_XUSB_CFG_ARU_C11_CSBRANGE_REG, range); 809 bus_space_write_4(bst, fpcih, T_XUSB_CFG_CSB_BASE_ADDR + offset, value); 810 } 811 812 static int 813 xusb_mailbox_send(struct tegra_xusb_softc * const psc, uint32_t msg) 814 { 815 struct xhci_softc * const sc = &psc->sc_xhci; 816 const bus_space_tag_t bst = psc->sc_xhci.sc_iot; 817 const bus_space_handle_t fpcih = psc->sc_bsh_fpci; 818 uint32_t val; 819 bool wait = false; 820 821 const uint8_t type = __SHIFTOUT(msg, MAILBOX_DATA_TYPE); 822 823 if (!(type == 128 || type == 129)) { 824 val = bus_space_read_4(bst, fpcih, 825 T_XUSB_CFG_ARU_MAILBOX_OWNER_REG); 826 DPRINTF(sc->sc_dev, "XUSB_CFG_ARU_MBOX_OWNER 0x%x\n", 827 val); 828 if (val != MAILBOX_OWNER_NONE) { 829 return EBUSY; 830 } 831 832 bus_space_write_4(bst, fpcih, T_XUSB_CFG_ARU_MAILBOX_OWNER_REG, 833 MAILBOX_OWNER_SW); 834 835 val = bus_space_read_4(bst, fpcih, 836 T_XUSB_CFG_ARU_MAILBOX_OWNER_REG); 837 DPRINTF(sc->sc_dev, "XUSB_CFG_ARU_MBOX_OWNER 0x%x\n", 838 val); 839 if (val != MAILBOX_OWNER_SW) { 840 return EBUSY; 841 } 842 843 wait = true; 844 } 845 846 bus_space_write_4(bst, fpcih, T_XUSB_CFG_ARU_MAILBOX_DATA_IN_REG, msg); 847 848 tegra_reg_set_clear(bst, fpcih, T_XUSB_CFG_ARU_MAILBOX_CMD_REG, 849 T_XUSB_CFG_ARU_MAILBOX_CMD_INT_EN | 850 T_XUSB_CFG_ARU_MAILBOX_CMD_DEST_FALCON, 0); 851 852 if (wait) { 853 854 for (u_int i = 0; i < 2500; i++) { 855 val = bus_space_read_4(bst, fpcih, 856 T_XUSB_CFG_ARU_MAILBOX_OWNER_REG); 857 DPRINTF(sc->sc_dev, 858 "XUSB_CFG_ARU_MBOX_OWNER 0x%x\n", val); 859 if (val == MAILBOX_OWNER_NONE) { 860 break; 861 } 862 DELAY(10); 863 } 864 865 val = bus_space_read_4(bst, fpcih, 866 T_XUSB_CFG_ARU_MAILBOX_OWNER_REG); 867 DPRINTF(sc->sc_dev, 868 "XUSB_CFG_ARU_MBOX_OWNER 0x%x\n", val); 869 if (val != MAILBOX_OWNER_NONE) { 870 aprint_error_dev(sc->sc_dev, 871 "timeout, XUSB_CFG_ARU_MBOX_OWNER 0x%x\n", val); 872 } 873 } 874 875 return 0; 876 } 877
Indexes created Mon Sep 29 21:09:56 GMT 2025