tegra_xusbpad.c revision 1.1 1 /* $NetBSD: tegra_xusbpad.c,v 1.1 2015/05/15 11:49:10 jmcneill Exp $ */
2
3 /*-
4 * Copyright (c) 2015 Jared D. McNeill <jmcneill (at) invisible.ca>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29 #include "locators.h"
30
31 #include <sys/cdefs.h>
32 __KERNEL_RCSID(0, "$NetBSD: tegra_xusbpad.c,v 1.1 2015/05/15 11:49:10 jmcneill Exp $");
33
34 #include <sys/param.h>
35 #include <sys/bus.h>
36 #include <sys/device.h>
37 #include <sys/intr.h>
38 #include <sys/systm.h>
39 #include <sys/kernel.h>
40
41 #include <arm/nvidia/tegra_reg.h>
42 #include <arm/nvidia/tegra_xusbpadreg.h>
43 #include <arm/nvidia/tegra_var.h>
44
45 static int tegra_xusbpad_match(device_t, cfdata_t, void *);
46 static void tegra_xusbpad_attach(device_t, device_t, void *);
47
48 struct tegra_xusbpad_softc {
49 device_t sc_dev;
50 bus_space_tag_t sc_bst;
51 bus_space_handle_t sc_bsh;
52 };
53
54 static struct tegra_xusbpad_softc *xusbpad_softc = NULL;
55
56 CFATTACH_DECL_NEW(tegra_xusbpad, sizeof(struct tegra_xusbpad_softc),
57 tegra_xusbpad_match, tegra_xusbpad_attach, NULL, NULL);
58
59 static int
60 tegra_xusbpad_match(device_t parent, cfdata_t cf, void *aux)
61 {
62 return 1;
63 }
64
65 static void
66 tegra_xusbpad_attach(device_t parent, device_t self, void *aux)
67 {
68 struct tegra_xusbpad_softc * const sc = device_private(self);
69 struct tegraio_attach_args * const tio = aux;
70 const struct tegra_locators * const loc = &tio->tio_loc;
71
72 sc->sc_dev = self;
73 sc->sc_bst = tio->tio_bst;
74 bus_space_subregion(tio->tio_bst, tio->tio_bsh,
75 loc->loc_offset, loc->loc_size, &sc->sc_bsh);
76
77 KASSERT(xusbpad_softc == NULL);
78 xusbpad_softc = sc;
79
80 aprint_naive("\n");
81 aprint_normal(": XUSB PADCTL\n");
82
83 }
84
85 static void
86 tegra_xusbpad_get_bs(bus_space_tag_t *pbst, bus_space_handle_t *pbsh)
87 {
88 if (xusbpad_softc) {
89 *pbst = xusbpad_softc->sc_bst;
90 *pbsh = xusbpad_softc->sc_bsh;
91 } else {
92 *pbst = &armv7_generic_bs_tag;
93 bus_space_subregion(*pbst, tegra_apb_bsh,
94 TEGRA_XUSB_PADCTL_OFFSET, TEGRA_XUSB_PADCTL_SIZE, pbsh);
95 }
96 }
97
98 void
99 tegra_xusbpad_sata_enable(void)
100 {
101 bus_space_tag_t bst;
102 bus_space_handle_t bsh;
103 int retry;
104
105 tegra_xusbpad_get_bs(&bst, &bsh);
106
107 tegra_reg_set_clear(bst, bsh, XUSB_PADCTL_USB3_PAD_MUX_REG,
108 __SHIFTIN(XUSB_PADCTL_USB3_PAD_MUX_SATA_PAD_LANE0_SATA,
109 XUSB_PADCTL_USB3_PAD_MUX_SATA_PAD_LANE0) |
110 XUSB_PADCTL_USB3_PAD_MUX_FORCE_SATA_PAD_IDDQ_DISABLE_MASK0,
111 XUSB_PADCTL_USB3_PAD_MUX_SATA_PAD_LANE0);
112
113 tegra_reg_set_clear(bst, bsh, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_REG,
114 0,
115 XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ |
116 XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ_OVRD);
117 tegra_reg_set_clear(bst, bsh, XUSB_PADCTL_IOPHY_PLL_S0_CTL1_REG,
118 0,
119 XUSB_PADCTL_IOPHY_PLL_S0_CTL1_IDDQ |
120 XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PWR_OVRD);
121 tegra_reg_set_clear(bst, bsh, XUSB_PADCTL_IOPHY_PLL_S0_CTL1_REG,
122 XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_MODE, 0);
123 tegra_reg_set_clear(bst, bsh, XUSB_PADCTL_IOPHY_PLL_S0_CTL1_REG,
124 XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_RST, 0);
125
126 for (retry = 1000; retry > 0; retry--) {
127 const uint32_t v = bus_space_read_4(bst, bsh,
128 XUSB_PADCTL_IOPHY_PLL_S0_CTL1_REG);
129 if (v & XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_LOCKDET)
130 break;
131 delay(100);
132 }
133 if (retry == 0) {
134 printf("WARNING: SATA PHY power-on failed\n");
135 }
136 }
137