tegra_xusbpad.c revision 1.2.2.1
1 /* $NetBSD: tegra_xusbpad.c,v 1.2.2.1 2017/03/20 06:57:11 pgoyette Exp $ */ 2 3 /*- 4 * Copyright (c) 2015 Jared D. McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: tegra_xusbpad.c,v 1.2.2.1 2017/03/20 06:57:11 pgoyette Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/bus.h> 34 #include <sys/device.h> 35 #include <sys/intr.h> 36 #include <sys/systm.h> 37 #include <sys/kernel.h> 38 39 #include <arm/nvidia/tegra_reg.h> 40 #include <arm/nvidia/tegra_xusbpadreg.h> 41 #include <arm/nvidia/tegra_var.h> 42 43 #include <dev/fdt/fdtvar.h> 44 45 #define TEGRA_FUSE_SKU_CALIB_REG 0xf0 46 47 static int tegra_xusbpad_match(device_t, cfdata_t, void *); 48 static void tegra_xusbpad_attach(device_t, device_t, void *); 49 50 struct tegra_xusbpad_softc { 51 device_t sc_dev; 52 bus_space_tag_t sc_bst; 53 bus_space_handle_t sc_bsh; 54 }; 55 56 void padregdump(void); 57 58 static void tegra_xusbpad_setup(struct tegra_xusbpad_softc * const); 59 60 static struct tegra_xusbpad_softc *xusbpad_softc = NULL; 61 62 CFATTACH_DECL_NEW(tegra_xusbpad, sizeof(struct tegra_xusbpad_softc), 63 tegra_xusbpad_match, tegra_xusbpad_attach, NULL, NULL); 64 65 static int 66 tegra_xusbpad_match(device_t parent, cfdata_t cf, void *aux) 67 { 68 const char * const compatible[] = 69 { "nvidia,tegra124-xusb-padctl", NULL }; 70 struct fdt_attach_args * const faa = aux; 71 72 return of_match_compatible(faa->faa_phandle, compatible); 73 } 74 75 static void 76 tegra_xusbpad_attach(device_t parent, device_t self, void *aux) 77 { 78 struct tegra_xusbpad_softc * const sc = device_private(self); 79 struct fdt_attach_args * const faa = aux; 80 bus_addr_t addr; 81 bus_size_t size; 82 int error; 83 84 if (fdtbus_get_reg(faa->faa_phandle, 0, &addr, &size) != 0) { 85 aprint_error(": couldn't get registers\n"); 86 return; 87 } 88 89 sc->sc_dev = self; 90 sc->sc_bst = faa->faa_bst; 91 error = bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh); 92 if (error) { 93 aprint_error(": couldn't map %#llx: %d", (uint64_t)addr, error); 94 return; 95 } 96 97 KASSERT(xusbpad_softc == NULL); 98 xusbpad_softc = sc; 99 100 aprint_naive("\n"); 101 aprint_normal(": XUSB PADCTL\n"); 102 103 padregdump(); 104 tegra_xusbpad_setup(sc); 105 padregdump(); 106 } 107 108 static void 109 tegra_xusbpad_get_bs(bus_space_tag_t *pbst, bus_space_handle_t *pbsh) 110 { 111 if (xusbpad_softc) { 112 *pbst = xusbpad_softc->sc_bst; 113 *pbsh = xusbpad_softc->sc_bsh; 114 } else { 115 *pbst = &armv7_generic_bs_tag; 116 bus_space_subregion(*pbst, tegra_apb_bsh, 117 TEGRA_XUSB_PADCTL_OFFSET, TEGRA_XUSB_PADCTL_SIZE, pbsh); 118 } 119 } 120 121 void 122 tegra_xusbpad_sata_enable(void) 123 { 124 bus_space_tag_t bst; 125 bus_space_handle_t bsh; 126 int retry; 127 128 tegra_xusbpad_get_bs(&bst, &bsh); 129 130 tegra_reg_set_clear(bst, bsh, XUSB_PADCTL_USB3_PAD_MUX_REG, 131 __SHIFTIN(XUSB_PADCTL_USB3_PAD_MUX_SATA_PAD_LANE0_SATA, 132 XUSB_PADCTL_USB3_PAD_MUX_SATA_PAD_LANE0) | 133 XUSB_PADCTL_USB3_PAD_MUX_FORCE_SATA_PAD_IDDQ_DISABLE_MASK0, 134 XUSB_PADCTL_USB3_PAD_MUX_SATA_PAD_LANE0); 135 136 tegra_reg_set_clear(bst, bsh, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_REG, 137 0, 138 XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ | 139 XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ_OVRD); 140 tegra_reg_set_clear(bst, bsh, XUSB_PADCTL_IOPHY_PLL_S0_CTL1_REG, 141 0, 142 XUSB_PADCTL_IOPHY_PLL_S0_CTL1_IDDQ | 143 XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PWR_OVRD); 144 tegra_reg_set_clear(bst, bsh, XUSB_PADCTL_IOPHY_PLL_S0_CTL1_REG, 145 XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_MODE, 0); 146 tegra_reg_set_clear(bst, bsh, XUSB_PADCTL_IOPHY_PLL_S0_CTL1_REG, 147 XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_RST, 0); 148 149 for (retry = 1000; retry > 0; retry--) { 150 const uint32_t v = bus_space_read_4(bst, bsh, 151 XUSB_PADCTL_IOPHY_PLL_S0_CTL1_REG); 152 if (v & XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_LOCKDET) 153 break; 154 delay(100); 155 } 156 if (retry == 0) { 157 printf("WARNING: SATA PHY power-on failed\n"); 158 } 159 } 160 161 void 162 padregdump(void) 163 { 164 bus_space_tag_t bst; 165 bus_space_handle_t bsh; 166 bus_size_t i; 167 u_int j; 168 169 tegra_xusbpad_get_bs(&bst, &bsh); 170 171 for (i = 0x000; i < 0x160; ) { 172 printf("0x%03jx:", (uintmax_t)i); 173 for (j = 0; i < 0x160 && j < 0x10; j += 4, i += 4) { 174 printf(" %08x", bus_space_read_4(bst, bsh, i)); 175 } 176 printf("\n"); 177 } 178 } 179 180 static void 181 tegra_xusbpad_setup(struct tegra_xusbpad_softc * const sc) 182 { 183 const uint32_t skucalib = tegra_fuse_read(TEGRA_FUSE_SKU_CALIB_REG); 184 uint32_t val; 185 186 printf("SKU CALIB 0x%x\n", skucalib); 187 const uint32_t hcl[3] = { 188 (skucalib >> 0) & 0x3f, 189 (skucalib >> 15) & 0x3f, 190 (skucalib >> 15) & 0x3f, 191 }; 192 const uint32_t hic = (skucalib >> 13) & 3; 193 const uint32_t hsl = (skucalib >> 11) & 3; 194 const uint32_t htra = (skucalib >> 7) & 0xf; 195 196 197 val = bus_space_read_4(sc->sc_bst, sc->sc_bsh, XUSB_PADCTL_USB2_PAD_MUX_REG); 198 device_printf(sc->sc_dev, "XUSB_PADCTL_USB2_PAD_MUX_REG is 0x%x\n", val); 199 val = bus_space_read_4(sc->sc_bst, sc->sc_bsh, XUSB_PADCTL_USB2_PORT_CAP_REG); 200 device_printf(sc->sc_dev, "XUSB_PADCTL_USB2_PORT_CAP_REG is 0x%x\n", val); 201 val = bus_space_read_4(sc->sc_bst, sc->sc_bsh, XUSB_PADCTL_SS_PORT_MAP_REG); 202 device_printf(sc->sc_dev, "XUSB_PADCTL_SS_PORT_MAP_REG is 0x%x\n", val); 203 204 bus_space_write_4(sc->sc_bst, sc->sc_bsh, XUSB_PADCTL_USB2_PAD_MUX_REG, (0<<0)|(0<<2)|(1<<4)); 205 bus_space_write_4(sc->sc_bst, sc->sc_bsh, XUSB_PADCTL_USB2_PORT_CAP_REG, (1<<0)|(1<<4)|(1<<8)); 206 bus_space_write_4(sc->sc_bst, sc->sc_bsh, XUSB_PADCTL_SS_PORT_MAP_REG, (2<<0)|(7<<4)); 207 208 tegra_reg_set_clear(sc->sc_bst, sc->sc_bsh, XUSB_PADCTL_USB2_BIAS_PAD_CTL0_REG, 209 __SHIFTIN(hsl, XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_SQUELCH_LEVEL) | 210 __SHIFTIN(XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_DISCON_LEVEL_VAL, 211 XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_DISCON_LEVEL), 212 XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_SQUELCH_LEVEL | 213 XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_DISCON_LEVEL); 214 215 tegra_reg_set_clear(sc->sc_bst, sc->sc_bsh, 216 XUSB_PADCTL_USB2_OTG_PAD0_CTL0_REG, 217 __SHIFTIN(hcl[0], 218 XUSB_PADCTL_USB2_OTG_PAD_CTL0_HS_CURR_LEVEL) | 219 __SHIFTIN(XUSB_PADCTL_USB2_OTG_PAD_CTL0_HS_SLEW_VAL, 220 XUSB_PADCTL_USB2_OTG_PAD_CTL0_HS_SLEW) | 221 __SHIFTIN(XUSB_PADCTL_USB2_OTG_PAD_CTL0_LS_RSLEW_VAL(0), 222 XUSB_PADCTL_USB2_OTG_PAD_CTL0_LS_RSLEW), 223 XUSB_PADCTL_USB2_OTG_PAD_CTL0_HS_CURR_LEVEL | 224 XUSB_PADCTL_USB2_OTG_PAD_CTL0_HS_SLEW | 225 XUSB_PADCTL_USB2_OTG_PAD_CTL0_LS_RSLEW | 226 XUSB_PADCTL_USB2_OTG_PAD_CTL0_PD | 227 XUSB_PADCTL_USB2_OTG_PAD_CTL0_PD2 | 228 XUSB_PADCTL_USB2_OTG_PAD_CTL0_PD_ZI); 229 tegra_reg_set_clear(sc->sc_bst, sc->sc_bsh, 230 XUSB_PADCTL_USB2_OTG_PAD1_CTL0_REG, 231 __SHIFTIN(hcl[1], 232 XUSB_PADCTL_USB2_OTG_PAD_CTL0_HS_CURR_LEVEL) | 233 __SHIFTIN(XUSB_PADCTL_USB2_OTG_PAD_CTL0_HS_SLEW_VAL, 234 XUSB_PADCTL_USB2_OTG_PAD_CTL0_HS_SLEW) | 235 __SHIFTIN(XUSB_PADCTL_USB2_OTG_PAD_CTL0_LS_RSLEW_VAL(1), 236 XUSB_PADCTL_USB2_OTG_PAD_CTL0_LS_RSLEW), 237 XUSB_PADCTL_USB2_OTG_PAD_CTL0_HS_CURR_LEVEL | 238 XUSB_PADCTL_USB2_OTG_PAD_CTL0_HS_SLEW | 239 XUSB_PADCTL_USB2_OTG_PAD_CTL0_LS_RSLEW | 240 XUSB_PADCTL_USB2_OTG_PAD_CTL0_PD | 241 XUSB_PADCTL_USB2_OTG_PAD_CTL0_PD2 | 242 XUSB_PADCTL_USB2_OTG_PAD_CTL0_PD_ZI); 243 tegra_reg_set_clear(sc->sc_bst, sc->sc_bsh, 244 XUSB_PADCTL_USB2_OTG_PAD2_CTL0_REG, 245 __SHIFTIN(hcl[2], 246 XUSB_PADCTL_USB2_OTG_PAD_CTL0_HS_CURR_LEVEL) | 247 __SHIFTIN(XUSB_PADCTL_USB2_OTG_PAD_CTL0_HS_SLEW_VAL, 248 XUSB_PADCTL_USB2_OTG_PAD_CTL0_HS_SLEW) | 249 __SHIFTIN(XUSB_PADCTL_USB2_OTG_PAD_CTL0_LS_RSLEW_VAL(2), 250 XUSB_PADCTL_USB2_OTG_PAD_CTL0_LS_RSLEW), 251 XUSB_PADCTL_USB2_OTG_PAD_CTL0_HS_CURR_LEVEL | 252 XUSB_PADCTL_USB2_OTG_PAD_CTL0_HS_SLEW | 253 XUSB_PADCTL_USB2_OTG_PAD_CTL0_LS_RSLEW | 254 XUSB_PADCTL_USB2_OTG_PAD_CTL0_PD | 255 XUSB_PADCTL_USB2_OTG_PAD_CTL0_PD2 | 256 XUSB_PADCTL_USB2_OTG_PAD_CTL0_PD_ZI); 257 258 tegra_reg_set_clear(sc->sc_bst, sc->sc_bsh, 259 XUSB_PADCTL_USB2_OTG_PAD0_CTL1_REG, 260 __SHIFTIN(htra, 261 XUSB_PADCTL_USB2_OTG_PAD_CTL1_TERM_RANGE_ADJ) | 262 __SHIFTIN(hic, 263 XUSB_PADCTL_USB2_OTG_PAD_CTL1_HS_IREF_CAP), 264 XUSB_PADCTL_USB2_OTG_PAD_CTL1_TERM_RANGE_ADJ | 265 XUSB_PADCTL_USB2_OTG_PAD_CTL1_HS_IREF_CAP | 266 XUSB_PADCTL_USB2_OTG_PAD_CTL1_PD_DR | 267 XUSB_PADCTL_USB2_OTG_PAD_CTL1_PD_CHRP_FORCE_POWERUP | 268 XUSB_PADCTL_USB2_OTG_PAD_CTL1_PD_DISC_FORCE_POWERUP); 269 tegra_reg_set_clear(sc->sc_bst, sc->sc_bsh, 270 XUSB_PADCTL_USB2_OTG_PAD1_CTL1_REG, 271 __SHIFTIN(htra, 272 XUSB_PADCTL_USB2_OTG_PAD_CTL1_TERM_RANGE_ADJ) | 273 __SHIFTIN(hic, 274 XUSB_PADCTL_USB2_OTG_PAD_CTL1_HS_IREF_CAP), 275 XUSB_PADCTL_USB2_OTG_PAD_CTL1_TERM_RANGE_ADJ | 276 XUSB_PADCTL_USB2_OTG_PAD_CTL1_HS_IREF_CAP | 277 XUSB_PADCTL_USB2_OTG_PAD_CTL1_PD_DR | 278 XUSB_PADCTL_USB2_OTG_PAD_CTL1_PD_CHRP_FORCE_POWERUP | 279 XUSB_PADCTL_USB2_OTG_PAD_CTL1_PD_DISC_FORCE_POWERUP); 280 tegra_reg_set_clear(sc->sc_bst, sc->sc_bsh, 281 XUSB_PADCTL_USB2_OTG_PAD2_CTL1_REG, 282 __SHIFTIN(htra, 283 XUSB_PADCTL_USB2_OTG_PAD_CTL1_TERM_RANGE_ADJ) | 284 __SHIFTIN(hic, 285 XUSB_PADCTL_USB2_OTG_PAD_CTL1_HS_IREF_CAP), 286 XUSB_PADCTL_USB2_OTG_PAD_CTL1_TERM_RANGE_ADJ | 287 XUSB_PADCTL_USB2_OTG_PAD_CTL1_HS_IREF_CAP | 288 XUSB_PADCTL_USB2_OTG_PAD_CTL1_PD_DR | 289 XUSB_PADCTL_USB2_OTG_PAD_CTL1_PD_CHRP_FORCE_POWERUP | 290 XUSB_PADCTL_USB2_OTG_PAD_CTL1_PD_DISC_FORCE_POWERUP); 291 292 //tegra_reg_set_clear(sc->sc_bst, sc->sc_bsh, XUSB_PADCTL_USB2_BATTERY_CHRG_BIASPAD_REG, 0, 1); /* PD_OTG */ 293 tegra_reg_set_clear(sc->sc_bst, sc->sc_bsh, XUSB_PADCTL_USB2_OTG_PAD0_CTL0_REG, 0, XUSB_PADCTL_USB2_OTG_PAD_CTL0_PD); 294 tegra_reg_set_clear(sc->sc_bst, sc->sc_bsh, XUSB_PADCTL_USB2_OTG_PAD1_CTL0_REG, 0, XUSB_PADCTL_USB2_OTG_PAD_CTL0_PD); 295 tegra_reg_set_clear(sc->sc_bst, sc->sc_bsh, XUSB_PADCTL_USB2_OTG_PAD2_CTL0_REG, 0, XUSB_PADCTL_USB2_OTG_PAD_CTL0_PD); 296 tegra_reg_set_clear(sc->sc_bst, sc->sc_bsh, XUSB_PADCTL_USB2_OTG_PAD0_CTL0_REG, 0, XUSB_PADCTL_USB2_OTG_PAD_CTL0_PD2); 297 tegra_reg_set_clear(sc->sc_bst, sc->sc_bsh, XUSB_PADCTL_USB2_OTG_PAD1_CTL0_REG, 0, XUSB_PADCTL_USB2_OTG_PAD_CTL0_PD2); 298 tegra_reg_set_clear(sc->sc_bst, sc->sc_bsh, XUSB_PADCTL_USB2_OTG_PAD2_CTL0_REG, 0, XUSB_PADCTL_USB2_OTG_PAD_CTL0_PD2); 299 tegra_reg_set_clear(sc->sc_bst, sc->sc_bsh, XUSB_PADCTL_USB2_OTG_PAD0_CTL0_REG, 0, XUSB_PADCTL_USB2_OTG_PAD_CTL0_PD_ZI); 300 tegra_reg_set_clear(sc->sc_bst, sc->sc_bsh, XUSB_PADCTL_USB2_OTG_PAD1_CTL0_REG, 0, XUSB_PADCTL_USB2_OTG_PAD_CTL0_PD_ZI); 301 tegra_reg_set_clear(sc->sc_bst, sc->sc_bsh, XUSB_PADCTL_USB2_OTG_PAD2_CTL0_REG, 0, XUSB_PADCTL_USB2_OTG_PAD_CTL0_PD_ZI); 302 tegra_reg_set_clear(sc->sc_bst, sc->sc_bsh, XUSB_PADCTL_USB2_OTG_PAD0_CTL1_REG, 0, XUSB_PADCTL_USB2_OTG_PAD_CTL1_PD_DR); 303 tegra_reg_set_clear(sc->sc_bst, sc->sc_bsh, XUSB_PADCTL_USB2_OTG_PAD1_CTL1_REG, 0, XUSB_PADCTL_USB2_OTG_PAD_CTL1_PD_DR); 304 tegra_reg_set_clear(sc->sc_bst, sc->sc_bsh, XUSB_PADCTL_USB2_OTG_PAD2_CTL1_REG, 0, XUSB_PADCTL_USB2_OTG_PAD_CTL1_PD_DR); 305 tegra_reg_set_clear(sc->sc_bst, sc->sc_bsh, XUSB_PADCTL_USB2_BIAS_PAD_CTL0_REG, 0, XUSB_PADCTL_USB2_BIAS_PAD_CTL0_PD); 306 tegra_reg_set_clear(sc->sc_bst, sc->sc_bsh, XUSB_PADCTL_USB2_BIAS_PAD_CTL0_REG, 0, XUSB_PADCTL_USB2_BIAS_PAD_CTL0_PD_TRK); 307 308 tegra_reg_set_clear(sc->sc_bst, sc->sc_bsh, XUSB_PADCTL_ELPG_PROGRAM_REG, 309 0, XUSB_PADCTL_ELPG_PROGRAM_SSP0_ELPG_CLAMP_EN); 310 tegra_reg_set_clear(sc->sc_bst, sc->sc_bsh, XUSB_PADCTL_ELPG_PROGRAM_REG, 311 0, XUSB_PADCTL_ELPG_PROGRAM_SSP0_ELPG_CLAMP_EN_EARLY); 312 tegra_reg_set_clear(sc->sc_bst, sc->sc_bsh, XUSB_PADCTL_ELPG_PROGRAM_REG, 313 0, XUSB_PADCTL_ELPG_PROGRAM_SSP0_ELPG_VCORE_DOWN); 314 315 DELAY(200); 316 tegra_reg_set_clear(sc->sc_bst, sc->sc_bsh, XUSB_PADCTL_ELPG_PROGRAM_REG, 0, __BIT(26)); 317 DELAY(200); 318 tegra_reg_set_clear(sc->sc_bst, sc->sc_bsh, XUSB_PADCTL_ELPG_PROGRAM_REG, 0, __BIT(25)); 319 DELAY(200); 320 tegra_reg_set_clear(sc->sc_bst, sc->sc_bsh, XUSB_PADCTL_ELPG_PROGRAM_REG, 0, __BIT(24)); 321 DELAY(200); 322 323 tegra_reg_set_clear(sc->sc_bst, sc->sc_bsh, XUSB_PADCTL_OC_DET_REG, 0, __BITS(22,16)); 324 tegra_reg_set_clear(sc->sc_bst, sc->sc_bsh, XUSB_PADCTL_OC_DET_REG, __BIT(4), 0); 325 tegra_reg_set_clear(sc->sc_bst, sc->sc_bsh, XUSB_PADCTL_OC_DET_REG, __BIT(8), 0); 326 tegra_reg_set_clear(sc->sc_bst, sc->sc_bsh, XUSB_PADCTL_OC_DET_REG, __BIT(9), 0); 327 328 val = bus_space_read_4(sc->sc_bst, sc->sc_bsh, XUSB_PADCTL_USB2_PAD_MUX_REG); 329 device_printf(sc->sc_dev, "XUSB_PADCTL_USB2_PAD_MUX_REG is 0x%x\n", val); 330 val = bus_space_read_4(sc->sc_bst, sc->sc_bsh, XUSB_PADCTL_USB2_PORT_CAP_REG); 331 device_printf(sc->sc_dev, "XUSB_PADCTL_USB2_PORT_CAP_REG is 0x%x\n", val); 332 val = bus_space_read_4(sc->sc_bst, sc->sc_bsh, XUSB_PADCTL_SS_PORT_MAP_REG); 333 device_printf(sc->sc_dev, "XUSB_PADCTL_SS_PORT_MAP_REG is 0x%x\n", val); 334 335 336 } 337
Indexes created Wed Oct 15 16:09:53 GMT 2025