tegra_xusbpad.c revision 1.4
1 /* $NetBSD: tegra_xusbpad.c,v 1.4 2017/04/11 11:32:51 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2015 Jared D. McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include "opt_tegra.h" 30 31 #include <sys/cdefs.h> 32 __KERNEL_RCSID(0, "$NetBSD: tegra_xusbpad.c,v 1.4 2017/04/11 11:32:51 jmcneill Exp $"); 33 34 #include <sys/param.h> 35 #include <sys/bus.h> 36 #include <sys/device.h> 37 #include <sys/intr.h> 38 #include <sys/systm.h> 39 #include <sys/kernel.h> 40 41 #include <arm/nvidia/tegra_reg.h> 42 #include <arm/nvidia/tegra_xusbpadreg.h> 43 #include <arm/nvidia/tegra_var.h> 44 45 #include <dev/fdt/fdtvar.h> 46 47 #define TEGRA_FUSE_SKU_CALIB_REG 0xf0 48 49 static int tegra_xusbpad_match(device_t, cfdata_t, void *); 50 static void tegra_xusbpad_attach(device_t, device_t, void *); 51 52 struct tegra_xusbpad_softc { 53 device_t sc_dev; 54 bus_space_tag_t sc_bst; 55 bus_space_handle_t sc_bsh; 56 }; 57 58 #ifdef TEGRA_XUSBPAD_DEBUG 59 static void padregdump(void); 60 #endif 61 62 static void tegra_xusbpad_setup(struct tegra_xusbpad_softc * const); 63 64 static struct tegra_xusbpad_softc *xusbpad_softc = NULL; 65 66 CFATTACH_DECL_NEW(tegra_xusbpad, sizeof(struct tegra_xusbpad_softc), 67 tegra_xusbpad_match, tegra_xusbpad_attach, NULL, NULL); 68 69 static int 70 tegra_xusbpad_match(device_t parent, cfdata_t cf, void *aux) 71 { 72 const char * const compatible[] = 73 { "nvidia,tegra124-xusb-padctl", NULL }; 74 struct fdt_attach_args * const faa = aux; 75 76 return of_match_compatible(faa->faa_phandle, compatible); 77 } 78 79 static void 80 tegra_xusbpad_attach(device_t parent, device_t self, void *aux) 81 { 82 struct tegra_xusbpad_softc * const sc = device_private(self); 83 struct fdt_attach_args * const faa = aux; 84 bus_addr_t addr; 85 bus_size_t size; 86 int error; 87 88 if (fdtbus_get_reg(faa->faa_phandle, 0, &addr, &size) != 0) { 89 aprint_error(": couldn't get registers\n"); 90 return; 91 } 92 93 sc->sc_dev = self; 94 sc->sc_bst = faa->faa_bst; 95 error = bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh); 96 if (error) { 97 aprint_error(": couldn't map %#llx: %d", (uint64_t)addr, error); 98 return; 99 } 100 101 KASSERT(xusbpad_softc == NULL); 102 xusbpad_softc = sc; 103 104 aprint_naive("\n"); 105 aprint_normal(": XUSB PADCTL\n"); 106 107 #ifdef TEGRA_XUSBPAD_DEBUG 108 padregdump(); 109 #endif 110 111 tegra_xusbpad_setup(sc); 112 113 #ifdef TEGRA_XUSBPAD_DEBUG 114 padregdump(); 115 #endif 116 } 117 118 static void 119 tegra_xusbpad_get_bs(bus_space_tag_t *pbst, bus_space_handle_t *pbsh) 120 { 121 if (xusbpad_softc) { 122 *pbst = xusbpad_softc->sc_bst; 123 *pbsh = xusbpad_softc->sc_bsh; 124 } else { 125 *pbst = &armv7_generic_bs_tag; 126 bus_space_subregion(*pbst, tegra_apb_bsh, 127 TEGRA_XUSB_PADCTL_OFFSET, TEGRA_XUSB_PADCTL_SIZE, pbsh); 128 } 129 } 130 131 void 132 tegra_xusbpad_sata_enable(void) 133 { 134 bus_space_tag_t bst; 135 bus_space_handle_t bsh; 136 int retry; 137 138 tegra_xusbpad_get_bs(&bst, &bsh); 139 140 tegra_reg_set_clear(bst, bsh, XUSB_PADCTL_USB3_PAD_MUX_REG, 141 __SHIFTIN(XUSB_PADCTL_USB3_PAD_MUX_SATA_PAD_LANE0_SATA, 142 XUSB_PADCTL_USB3_PAD_MUX_SATA_PAD_LANE0) | 143 XUSB_PADCTL_USB3_PAD_MUX_FORCE_SATA_PAD_IDDQ_DISABLE_MASK0, 144 XUSB_PADCTL_USB3_PAD_MUX_SATA_PAD_LANE0); 145 146 tegra_reg_set_clear(bst, bsh, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_REG, 147 0, 148 XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ | 149 XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ_OVRD); 150 tegra_reg_set_clear(bst, bsh, XUSB_PADCTL_IOPHY_PLL_S0_CTL1_REG, 151 0, 152 XUSB_PADCTL_IOPHY_PLL_S0_CTL1_IDDQ | 153 XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PWR_OVRD); 154 tegra_reg_set_clear(bst, bsh, XUSB_PADCTL_IOPHY_PLL_S0_CTL1_REG, 155 XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_MODE, 0); 156 tegra_reg_set_clear(bst, bsh, XUSB_PADCTL_IOPHY_PLL_S0_CTL1_REG, 157 XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_RST, 0); 158 159 for (retry = 1000; retry > 0; retry--) { 160 const uint32_t v = bus_space_read_4(bst, bsh, 161 XUSB_PADCTL_IOPHY_PLL_S0_CTL1_REG); 162 if (v & XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_LOCKDET) 163 break; 164 delay(100); 165 } 166 if (retry == 0) { 167 printf("WARNING: SATA PHY power-on failed\n"); 168 } 169 } 170 171 #ifdef TEGRA_XUSBPAD_DEBUG 172 static void 173 padregdump(void) 174 { 175 bus_space_tag_t bst; 176 bus_space_handle_t bsh; 177 bus_size_t i; 178 u_int j; 179 180 tegra_xusbpad_get_bs(&bst, &bsh); 181 182 for (i = 0x000; i < 0x160; ) { 183 printf("0x%03jx:", (uintmax_t)i); 184 for (j = 0; i < 0x160 && j < 0x10; j += 4, i += 4) { 185 printf(" %08x", bus_space_read_4(bst, bsh, i)); 186 } 187 printf("\n"); 188 } 189 } 190 #endif 191 192 static void 193 tegra_xusbpad_setup(struct tegra_xusbpad_softc * const sc) 194 { 195 const uint32_t skucalib = tegra_fuse_read(TEGRA_FUSE_SKU_CALIB_REG); 196 #ifdef TEGRA_XUSBPAD_DEBUG 197 uint32_t val; 198 #endif 199 200 #ifdef TEGRA_XUSBPAD_DEBUG 201 printf("SKU CALIB 0x%x\n", skucalib); 202 #endif 203 const uint32_t hcl[3] = { 204 (skucalib >> 0) & 0x3f, 205 (skucalib >> 15) & 0x3f, 206 (skucalib >> 15) & 0x3f, 207 }; 208 const uint32_t hic = (skucalib >> 13) & 3; 209 const uint32_t hsl = (skucalib >> 11) & 3; 210 const uint32_t htra = (skucalib >> 7) & 0xf; 211 212 213 #ifdef TEGRA_XUSBPAD_DEBUG 214 val = bus_space_read_4(sc->sc_bst, sc->sc_bsh, XUSB_PADCTL_USB2_PAD_MUX_REG); 215 device_printf(sc->sc_dev, "XUSB_PADCTL_USB2_PAD_MUX_REG is 0x%x\n", val); 216 val = bus_space_read_4(sc->sc_bst, sc->sc_bsh, XUSB_PADCTL_USB2_PORT_CAP_REG); 217 device_printf(sc->sc_dev, "XUSB_PADCTL_USB2_PORT_CAP_REG is 0x%x\n", val); 218 val = bus_space_read_4(sc->sc_bst, sc->sc_bsh, XUSB_PADCTL_SS_PORT_MAP_REG); 219 device_printf(sc->sc_dev, "XUSB_PADCTL_SS_PORT_MAP_REG is 0x%x\n", val); 220 #endif 221 222 bus_space_write_4(sc->sc_bst, sc->sc_bsh, XUSB_PADCTL_USB2_PAD_MUX_REG, (0<<0)|(0<<2)|(1<<4)); 223 bus_space_write_4(sc->sc_bst, sc->sc_bsh, XUSB_PADCTL_USB2_PORT_CAP_REG, (1<<0)|(1<<4)|(1<<8)); 224 bus_space_write_4(sc->sc_bst, sc->sc_bsh, XUSB_PADCTL_SS_PORT_MAP_REG, (2<<0)|(7<<4)); 225 226 tegra_reg_set_clear(sc->sc_bst, sc->sc_bsh, XUSB_PADCTL_USB2_BIAS_PAD_CTL0_REG, 227 __SHIFTIN(hsl, XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_SQUELCH_LEVEL) | 228 __SHIFTIN(XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_DISCON_LEVEL_VAL, 229 XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_DISCON_LEVEL), 230 XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_SQUELCH_LEVEL | 231 XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_DISCON_LEVEL); 232 233 tegra_reg_set_clear(sc->sc_bst, sc->sc_bsh, 234 XUSB_PADCTL_USB2_OTG_PAD0_CTL0_REG, 235 __SHIFTIN(hcl[0], 236 XUSB_PADCTL_USB2_OTG_PAD_CTL0_HS_CURR_LEVEL) | 237 __SHIFTIN(XUSB_PADCTL_USB2_OTG_PAD_CTL0_HS_SLEW_VAL, 238 XUSB_PADCTL_USB2_OTG_PAD_CTL0_HS_SLEW) | 239 __SHIFTIN(XUSB_PADCTL_USB2_OTG_PAD_CTL0_LS_RSLEW_VAL(0), 240 XUSB_PADCTL_USB2_OTG_PAD_CTL0_LS_RSLEW), 241 XUSB_PADCTL_USB2_OTG_PAD_CTL0_HS_CURR_LEVEL | 242 XUSB_PADCTL_USB2_OTG_PAD_CTL0_HS_SLEW | 243 XUSB_PADCTL_USB2_OTG_PAD_CTL0_LS_RSLEW | 244 XUSB_PADCTL_USB2_OTG_PAD_CTL0_PD | 245 XUSB_PADCTL_USB2_OTG_PAD_CTL0_PD2 | 246 XUSB_PADCTL_USB2_OTG_PAD_CTL0_PD_ZI); 247 tegra_reg_set_clear(sc->sc_bst, sc->sc_bsh, 248 XUSB_PADCTL_USB2_OTG_PAD1_CTL0_REG, 249 __SHIFTIN(hcl[1], 250 XUSB_PADCTL_USB2_OTG_PAD_CTL0_HS_CURR_LEVEL) | 251 __SHIFTIN(XUSB_PADCTL_USB2_OTG_PAD_CTL0_HS_SLEW_VAL, 252 XUSB_PADCTL_USB2_OTG_PAD_CTL0_HS_SLEW) | 253 __SHIFTIN(XUSB_PADCTL_USB2_OTG_PAD_CTL0_LS_RSLEW_VAL(1), 254 XUSB_PADCTL_USB2_OTG_PAD_CTL0_LS_RSLEW), 255 XUSB_PADCTL_USB2_OTG_PAD_CTL0_HS_CURR_LEVEL | 256 XUSB_PADCTL_USB2_OTG_PAD_CTL0_HS_SLEW | 257 XUSB_PADCTL_USB2_OTG_PAD_CTL0_LS_RSLEW | 258 XUSB_PADCTL_USB2_OTG_PAD_CTL0_PD | 259 XUSB_PADCTL_USB2_OTG_PAD_CTL0_PD2 | 260 XUSB_PADCTL_USB2_OTG_PAD_CTL0_PD_ZI); 261 tegra_reg_set_clear(sc->sc_bst, sc->sc_bsh, 262 XUSB_PADCTL_USB2_OTG_PAD2_CTL0_REG, 263 __SHIFTIN(hcl[2], 264 XUSB_PADCTL_USB2_OTG_PAD_CTL0_HS_CURR_LEVEL) | 265 __SHIFTIN(XUSB_PADCTL_USB2_OTG_PAD_CTL0_HS_SLEW_VAL, 266 XUSB_PADCTL_USB2_OTG_PAD_CTL0_HS_SLEW) | 267 __SHIFTIN(XUSB_PADCTL_USB2_OTG_PAD_CTL0_LS_RSLEW_VAL(2), 268 XUSB_PADCTL_USB2_OTG_PAD_CTL0_LS_RSLEW), 269 XUSB_PADCTL_USB2_OTG_PAD_CTL0_HS_CURR_LEVEL | 270 XUSB_PADCTL_USB2_OTG_PAD_CTL0_HS_SLEW | 271 XUSB_PADCTL_USB2_OTG_PAD_CTL0_LS_RSLEW | 272 XUSB_PADCTL_USB2_OTG_PAD_CTL0_PD | 273 XUSB_PADCTL_USB2_OTG_PAD_CTL0_PD2 | 274 XUSB_PADCTL_USB2_OTG_PAD_CTL0_PD_ZI); 275 276 tegra_reg_set_clear(sc->sc_bst, sc->sc_bsh, 277 XUSB_PADCTL_USB2_OTG_PAD0_CTL1_REG, 278 __SHIFTIN(htra, 279 XUSB_PADCTL_USB2_OTG_PAD_CTL1_TERM_RANGE_ADJ) | 280 __SHIFTIN(hic, 281 XUSB_PADCTL_USB2_OTG_PAD_CTL1_HS_IREF_CAP), 282 XUSB_PADCTL_USB2_OTG_PAD_CTL1_TERM_RANGE_ADJ | 283 XUSB_PADCTL_USB2_OTG_PAD_CTL1_HS_IREF_CAP | 284 XUSB_PADCTL_USB2_OTG_PAD_CTL1_PD_DR | 285 XUSB_PADCTL_USB2_OTG_PAD_CTL1_PD_CHRP_FORCE_POWERUP | 286 XUSB_PADCTL_USB2_OTG_PAD_CTL1_PD_DISC_FORCE_POWERUP); 287 tegra_reg_set_clear(sc->sc_bst, sc->sc_bsh, 288 XUSB_PADCTL_USB2_OTG_PAD1_CTL1_REG, 289 __SHIFTIN(htra, 290 XUSB_PADCTL_USB2_OTG_PAD_CTL1_TERM_RANGE_ADJ) | 291 __SHIFTIN(hic, 292 XUSB_PADCTL_USB2_OTG_PAD_CTL1_HS_IREF_CAP), 293 XUSB_PADCTL_USB2_OTG_PAD_CTL1_TERM_RANGE_ADJ | 294 XUSB_PADCTL_USB2_OTG_PAD_CTL1_HS_IREF_CAP | 295 XUSB_PADCTL_USB2_OTG_PAD_CTL1_PD_DR | 296 XUSB_PADCTL_USB2_OTG_PAD_CTL1_PD_CHRP_FORCE_POWERUP | 297 XUSB_PADCTL_USB2_OTG_PAD_CTL1_PD_DISC_FORCE_POWERUP); 298 tegra_reg_set_clear(sc->sc_bst, sc->sc_bsh, 299 XUSB_PADCTL_USB2_OTG_PAD2_CTL1_REG, 300 __SHIFTIN(htra, 301 XUSB_PADCTL_USB2_OTG_PAD_CTL1_TERM_RANGE_ADJ) | 302 __SHIFTIN(hic, 303 XUSB_PADCTL_USB2_OTG_PAD_CTL1_HS_IREF_CAP), 304 XUSB_PADCTL_USB2_OTG_PAD_CTL1_TERM_RANGE_ADJ | 305 XUSB_PADCTL_USB2_OTG_PAD_CTL1_HS_IREF_CAP | 306 XUSB_PADCTL_USB2_OTG_PAD_CTL1_PD_DR | 307 XUSB_PADCTL_USB2_OTG_PAD_CTL1_PD_CHRP_FORCE_POWERUP | 308 XUSB_PADCTL_USB2_OTG_PAD_CTL1_PD_DISC_FORCE_POWERUP); 309 310 //tegra_reg_set_clear(sc->sc_bst, sc->sc_bsh, XUSB_PADCTL_USB2_BATTERY_CHRG_BIASPAD_REG, 0, 1); /* PD_OTG */ 311 tegra_reg_set_clear(sc->sc_bst, sc->sc_bsh, XUSB_PADCTL_USB2_OTG_PAD0_CTL0_REG, 0, XUSB_PADCTL_USB2_OTG_PAD_CTL0_PD); 312 tegra_reg_set_clear(sc->sc_bst, sc->sc_bsh, XUSB_PADCTL_USB2_OTG_PAD1_CTL0_REG, 0, XUSB_PADCTL_USB2_OTG_PAD_CTL0_PD); 313 tegra_reg_set_clear(sc->sc_bst, sc->sc_bsh, XUSB_PADCTL_USB2_OTG_PAD2_CTL0_REG, 0, XUSB_PADCTL_USB2_OTG_PAD_CTL0_PD); 314 tegra_reg_set_clear(sc->sc_bst, sc->sc_bsh, XUSB_PADCTL_USB2_OTG_PAD0_CTL0_REG, 0, XUSB_PADCTL_USB2_OTG_PAD_CTL0_PD2); 315 tegra_reg_set_clear(sc->sc_bst, sc->sc_bsh, XUSB_PADCTL_USB2_OTG_PAD1_CTL0_REG, 0, XUSB_PADCTL_USB2_OTG_PAD_CTL0_PD2); 316 tegra_reg_set_clear(sc->sc_bst, sc->sc_bsh, XUSB_PADCTL_USB2_OTG_PAD2_CTL0_REG, 0, XUSB_PADCTL_USB2_OTG_PAD_CTL0_PD2); 317 tegra_reg_set_clear(sc->sc_bst, sc->sc_bsh, XUSB_PADCTL_USB2_OTG_PAD0_CTL0_REG, 0, XUSB_PADCTL_USB2_OTG_PAD_CTL0_PD_ZI); 318 tegra_reg_set_clear(sc->sc_bst, sc->sc_bsh, XUSB_PADCTL_USB2_OTG_PAD1_CTL0_REG, 0, XUSB_PADCTL_USB2_OTG_PAD_CTL0_PD_ZI); 319 tegra_reg_set_clear(sc->sc_bst, sc->sc_bsh, XUSB_PADCTL_USB2_OTG_PAD2_CTL0_REG, 0, XUSB_PADCTL_USB2_OTG_PAD_CTL0_PD_ZI); 320 tegra_reg_set_clear(sc->sc_bst, sc->sc_bsh, XUSB_PADCTL_USB2_OTG_PAD0_CTL1_REG, 0, XUSB_PADCTL_USB2_OTG_PAD_CTL1_PD_DR); 321 tegra_reg_set_clear(sc->sc_bst, sc->sc_bsh, XUSB_PADCTL_USB2_OTG_PAD1_CTL1_REG, 0, XUSB_PADCTL_USB2_OTG_PAD_CTL1_PD_DR); 322 tegra_reg_set_clear(sc->sc_bst, sc->sc_bsh, XUSB_PADCTL_USB2_OTG_PAD2_CTL1_REG, 0, XUSB_PADCTL_USB2_OTG_PAD_CTL1_PD_DR); 323 tegra_reg_set_clear(sc->sc_bst, sc->sc_bsh, XUSB_PADCTL_USB2_BIAS_PAD_CTL0_REG, 0, XUSB_PADCTL_USB2_BIAS_PAD_CTL0_PD); 324 tegra_reg_set_clear(sc->sc_bst, sc->sc_bsh, XUSB_PADCTL_USB2_BIAS_PAD_CTL0_REG, 0, XUSB_PADCTL_USB2_BIAS_PAD_CTL0_PD_TRK); 325 326 tegra_reg_set_clear(sc->sc_bst, sc->sc_bsh, XUSB_PADCTL_ELPG_PROGRAM_REG, 327 0, XUSB_PADCTL_ELPG_PROGRAM_SSP0_ELPG_CLAMP_EN); 328 tegra_reg_set_clear(sc->sc_bst, sc->sc_bsh, XUSB_PADCTL_ELPG_PROGRAM_REG, 329 0, XUSB_PADCTL_ELPG_PROGRAM_SSP0_ELPG_CLAMP_EN_EARLY); 330 tegra_reg_set_clear(sc->sc_bst, sc->sc_bsh, XUSB_PADCTL_ELPG_PROGRAM_REG, 331 0, XUSB_PADCTL_ELPG_PROGRAM_SSP0_ELPG_VCORE_DOWN); 332 333 DELAY(200); 334 tegra_reg_set_clear(sc->sc_bst, sc->sc_bsh, XUSB_PADCTL_ELPG_PROGRAM_REG, 0, __BIT(26)); 335 DELAY(200); 336 tegra_reg_set_clear(sc->sc_bst, sc->sc_bsh, XUSB_PADCTL_ELPG_PROGRAM_REG, 0, __BIT(25)); 337 DELAY(200); 338 tegra_reg_set_clear(sc->sc_bst, sc->sc_bsh, XUSB_PADCTL_ELPG_PROGRAM_REG, 0, __BIT(24)); 339 DELAY(200); 340 341 tegra_reg_set_clear(sc->sc_bst, sc->sc_bsh, XUSB_PADCTL_OC_DET_REG, 0, __BITS(22,16)); 342 tegra_reg_set_clear(sc->sc_bst, sc->sc_bsh, XUSB_PADCTL_OC_DET_REG, __BIT(4), 0); 343 tegra_reg_set_clear(sc->sc_bst, sc->sc_bsh, XUSB_PADCTL_OC_DET_REG, __BIT(8), 0); 344 tegra_reg_set_clear(sc->sc_bst, sc->sc_bsh, XUSB_PADCTL_OC_DET_REG, __BIT(9), 0); 345 346 #ifdef TEGRA_XUSBPAD_DEBUG 347 val = bus_space_read_4(sc->sc_bst, sc->sc_bsh, XUSB_PADCTL_USB2_PAD_MUX_REG); 348 device_printf(sc->sc_dev, "XUSB_PADCTL_USB2_PAD_MUX_REG is 0x%x\n", val); 349 val = bus_space_read_4(sc->sc_bst, sc->sc_bsh, XUSB_PADCTL_USB2_PORT_CAP_REG); 350 device_printf(sc->sc_dev, "XUSB_PADCTL_USB2_PORT_CAP_REG is 0x%x\n", val); 351 val = bus_space_read_4(sc->sc_bst, sc->sc_bsh, XUSB_PADCTL_SS_PORT_MAP_REG); 352 device_printf(sc->sc_dev, "XUSB_PADCTL_SS_PORT_MAP_REG is 0x%x\n", val); 353 #endif 354 } 355
Indexes created Wed Oct 15 16:09:53 GMT 2025