tegra_xusbpad.c revision 1.5
1 /* $NetBSD: tegra_xusbpad.c,v 1.5 2017/04/14 00:19:34 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2015 Jared D. McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include "opt_tegra.h" 30 31 #include <sys/cdefs.h> 32 __KERNEL_RCSID(0, "$NetBSD: tegra_xusbpad.c,v 1.5 2017/04/14 00:19:34 jmcneill Exp $"); 33 34 #include <sys/param.h> 35 #include <sys/bus.h> 36 #include <sys/device.h> 37 #include <sys/intr.h> 38 #include <sys/systm.h> 39 #include <sys/kernel.h> 40 41 #include <arm/nvidia/tegra_reg.h> 42 #include <arm/nvidia/tegra_xusbpadreg.h> 43 #include <arm/nvidia/tegra_var.h> 44 45 #include <dev/fdt/fdtvar.h> 46 47 #define TEGRA_FUSE_SKU_CALIB_REG 0xf0 48 49 static int tegra_xusbpad_match(device_t, cfdata_t, void *); 50 static void tegra_xusbpad_attach(device_t, device_t, void *); 51 52 struct tegra_xusbpad_softc { 53 device_t sc_dev; 54 bus_space_tag_t sc_bst; 55 bus_space_handle_t sc_bsh; 56 }; 57 58 #ifdef TEGRA_XUSBPAD_DEBUG 59 static void padregdump(void); 60 #endif 61 62 static struct tegra_xusbpad_softc *xusbpad_softc = NULL; 63 64 CFATTACH_DECL_NEW(tegra_xusbpad, sizeof(struct tegra_xusbpad_softc), 65 tegra_xusbpad_match, tegra_xusbpad_attach, NULL, NULL); 66 67 static int 68 tegra_xusbpad_match(device_t parent, cfdata_t cf, void *aux) 69 { 70 const char * const compatible[] = 71 { "nvidia,tegra124-xusb-padctl", NULL }; 72 struct fdt_attach_args * const faa = aux; 73 74 return of_match_compatible(faa->faa_phandle, compatible); 75 } 76 77 static void 78 tegra_xusbpad_attach(device_t parent, device_t self, void *aux) 79 { 80 struct tegra_xusbpad_softc * const sc = device_private(self); 81 struct fdt_attach_args * const faa = aux; 82 bus_addr_t addr; 83 bus_size_t size; 84 int error; 85 86 if (fdtbus_get_reg(faa->faa_phandle, 0, &addr, &size) != 0) { 87 aprint_error(": couldn't get registers\n"); 88 return; 89 } 90 91 sc->sc_dev = self; 92 sc->sc_bst = faa->faa_bst; 93 error = bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh); 94 if (error) { 95 aprint_error(": couldn't map %#llx: %d", (uint64_t)addr, error); 96 return; 97 } 98 99 KASSERT(xusbpad_softc == NULL); 100 xusbpad_softc = sc; 101 102 aprint_naive("\n"); 103 aprint_normal(": XUSB PADCTL\n"); 104 } 105 106 static void 107 tegra_xusbpad_get_bs(bus_space_tag_t *pbst, bus_space_handle_t *pbsh) 108 { 109 if (xusbpad_softc) { 110 *pbst = xusbpad_softc->sc_bst; 111 *pbsh = xusbpad_softc->sc_bsh; 112 } else { 113 *pbst = &armv7_generic_bs_tag; 114 bus_space_subregion(*pbst, tegra_apb_bsh, 115 TEGRA_XUSB_PADCTL_OFFSET, TEGRA_XUSB_PADCTL_SIZE, pbsh); 116 } 117 } 118 119 void 120 tegra_xusbpad_sata_enable(void) 121 { 122 bus_space_tag_t bst; 123 bus_space_handle_t bsh; 124 int retry; 125 126 tegra_xusbpad_get_bs(&bst, &bsh); 127 128 tegra_reg_set_clear(bst, bsh, XUSB_PADCTL_USB3_PAD_MUX_REG, 129 __SHIFTIN(XUSB_PADCTL_USB3_PAD_MUX_SATA_PAD_LANE0_SATA, 130 XUSB_PADCTL_USB3_PAD_MUX_SATA_PAD_LANE0) | 131 XUSB_PADCTL_USB3_PAD_MUX_FORCE_SATA_PAD_IDDQ_DISABLE_MASK0, 132 XUSB_PADCTL_USB3_PAD_MUX_SATA_PAD_LANE0); 133 134 tegra_reg_set_clear(bst, bsh, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_REG, 135 0, 136 XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ | 137 XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ_OVRD); 138 tegra_reg_set_clear(bst, bsh, XUSB_PADCTL_IOPHY_PLL_S0_CTL1_REG, 139 0, 140 XUSB_PADCTL_IOPHY_PLL_S0_CTL1_IDDQ | 141 XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PWR_OVRD); 142 tegra_reg_set_clear(bst, bsh, XUSB_PADCTL_IOPHY_PLL_S0_CTL1_REG, 143 XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_MODE, 0); 144 tegra_reg_set_clear(bst, bsh, XUSB_PADCTL_IOPHY_PLL_S0_CTL1_REG, 145 XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_RST, 0); 146 147 for (retry = 1000; retry > 0; retry--) { 148 const uint32_t v = bus_space_read_4(bst, bsh, 149 XUSB_PADCTL_IOPHY_PLL_S0_CTL1_REG); 150 if (v & XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_LOCKDET) 151 break; 152 delay(100); 153 } 154 if (retry == 0) { 155 printf("WARNING: SATA PHY power-on failed\n"); 156 } 157 } 158 159 #ifdef TEGRA_XUSBPAD_DEBUG 160 static void 161 padregdump(void) 162 { 163 bus_space_tag_t bst; 164 bus_space_handle_t bsh; 165 bus_size_t i; 166 u_int j; 167 168 tegra_xusbpad_get_bs(&bst, &bsh); 169 170 for (i = 0x000; i < 0x160; ) { 171 printf("0x%03jx:", (uintmax_t)i); 172 for (j = 0; i < 0x160 && j < 0x10; j += 4, i += 4) { 173 printf(" %08x", bus_space_read_4(bst, bsh, i)); 174 } 175 printf("\n"); 176 } 177 } 178 #endif 179 180 void 181 tegra_xusbpad_xhci_enable(void) 182 { 183 struct tegra_xusbpad_softc * const sc = xusbpad_softc; 184 const uint32_t skucalib = tegra_fuse_read(TEGRA_FUSE_SKU_CALIB_REG); 185 #ifdef TEGRA_XUSBPAD_DEBUG 186 uint32_t val; 187 #endif 188 189 if (sc == NULL) { 190 aprint_error("%s: xusbpad driver not loaded\n", __func__); 191 return; 192 } 193 194 195 #ifdef TEGRA_XUSBPAD_DEBUG 196 padregdump(void); 197 printf("SKU CALIB 0x%x\n", skucalib); 198 #endif 199 const uint32_t hcl[3] = { 200 (skucalib >> 0) & 0x3f, 201 (skucalib >> 15) & 0x3f, 202 (skucalib >> 15) & 0x3f, 203 }; 204 const uint32_t hic = (skucalib >> 13) & 3; 205 const uint32_t hsl = (skucalib >> 11) & 3; 206 const uint32_t htra = (skucalib >> 7) & 0xf; 207 208 209 #ifdef TEGRA_XUSBPAD_DEBUG 210 val = bus_space_read_4(sc->sc_bst, sc->sc_bsh, XUSB_PADCTL_USB2_PAD_MUX_REG); 211 device_printf(sc->sc_dev, "XUSB_PADCTL_USB2_PAD_MUX_REG is 0x%x\n", val); 212 val = bus_space_read_4(sc->sc_bst, sc->sc_bsh, XUSB_PADCTL_USB2_PORT_CAP_REG); 213 device_printf(sc->sc_dev, "XUSB_PADCTL_USB2_PORT_CAP_REG is 0x%x\n", val); 214 val = bus_space_read_4(sc->sc_bst, sc->sc_bsh, XUSB_PADCTL_SS_PORT_MAP_REG); 215 device_printf(sc->sc_dev, "XUSB_PADCTL_SS_PORT_MAP_REG is 0x%x\n", val); 216 #endif 217 218 bus_space_write_4(sc->sc_bst, sc->sc_bsh, XUSB_PADCTL_USB2_PAD_MUX_REG, (0<<0)|(0<<2)|(1<<4)); 219 bus_space_write_4(sc->sc_bst, sc->sc_bsh, XUSB_PADCTL_USB2_PORT_CAP_REG, (1<<0)|(1<<4)|(1<<8)); 220 bus_space_write_4(sc->sc_bst, sc->sc_bsh, XUSB_PADCTL_SS_PORT_MAP_REG, (2<<0)|(7<<4)); 221 222 tegra_reg_set_clear(sc->sc_bst, sc->sc_bsh, XUSB_PADCTL_USB2_BIAS_PAD_CTL0_REG, 223 __SHIFTIN(hsl, XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_SQUELCH_LEVEL) | 224 __SHIFTIN(XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_DISCON_LEVEL_VAL, 225 XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_DISCON_LEVEL), 226 XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_SQUELCH_LEVEL | 227 XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_DISCON_LEVEL); 228 229 tegra_reg_set_clear(sc->sc_bst, sc->sc_bsh, 230 XUSB_PADCTL_USB2_OTG_PAD0_CTL0_REG, 231 __SHIFTIN(hcl[0], 232 XUSB_PADCTL_USB2_OTG_PAD_CTL0_HS_CURR_LEVEL) | 233 __SHIFTIN(XUSB_PADCTL_USB2_OTG_PAD_CTL0_HS_SLEW_VAL, 234 XUSB_PADCTL_USB2_OTG_PAD_CTL0_HS_SLEW) | 235 __SHIFTIN(XUSB_PADCTL_USB2_OTG_PAD_CTL0_LS_RSLEW_VAL(0), 236 XUSB_PADCTL_USB2_OTG_PAD_CTL0_LS_RSLEW), 237 XUSB_PADCTL_USB2_OTG_PAD_CTL0_HS_CURR_LEVEL | 238 XUSB_PADCTL_USB2_OTG_PAD_CTL0_HS_SLEW | 239 XUSB_PADCTL_USB2_OTG_PAD_CTL0_LS_RSLEW | 240 XUSB_PADCTL_USB2_OTG_PAD_CTL0_PD | 241 XUSB_PADCTL_USB2_OTG_PAD_CTL0_PD2 | 242 XUSB_PADCTL_USB2_OTG_PAD_CTL0_PD_ZI); 243 tegra_reg_set_clear(sc->sc_bst, sc->sc_bsh, 244 XUSB_PADCTL_USB2_OTG_PAD1_CTL0_REG, 245 __SHIFTIN(hcl[1], 246 XUSB_PADCTL_USB2_OTG_PAD_CTL0_HS_CURR_LEVEL) | 247 __SHIFTIN(XUSB_PADCTL_USB2_OTG_PAD_CTL0_HS_SLEW_VAL, 248 XUSB_PADCTL_USB2_OTG_PAD_CTL0_HS_SLEW) | 249 __SHIFTIN(XUSB_PADCTL_USB2_OTG_PAD_CTL0_LS_RSLEW_VAL(1), 250 XUSB_PADCTL_USB2_OTG_PAD_CTL0_LS_RSLEW), 251 XUSB_PADCTL_USB2_OTG_PAD_CTL0_HS_CURR_LEVEL | 252 XUSB_PADCTL_USB2_OTG_PAD_CTL0_HS_SLEW | 253 XUSB_PADCTL_USB2_OTG_PAD_CTL0_LS_RSLEW | 254 XUSB_PADCTL_USB2_OTG_PAD_CTL0_PD | 255 XUSB_PADCTL_USB2_OTG_PAD_CTL0_PD2 | 256 XUSB_PADCTL_USB2_OTG_PAD_CTL0_PD_ZI); 257 tegra_reg_set_clear(sc->sc_bst, sc->sc_bsh, 258 XUSB_PADCTL_USB2_OTG_PAD2_CTL0_REG, 259 __SHIFTIN(hcl[2], 260 XUSB_PADCTL_USB2_OTG_PAD_CTL0_HS_CURR_LEVEL) | 261 __SHIFTIN(XUSB_PADCTL_USB2_OTG_PAD_CTL0_HS_SLEW_VAL, 262 XUSB_PADCTL_USB2_OTG_PAD_CTL0_HS_SLEW) | 263 __SHIFTIN(XUSB_PADCTL_USB2_OTG_PAD_CTL0_LS_RSLEW_VAL(2), 264 XUSB_PADCTL_USB2_OTG_PAD_CTL0_LS_RSLEW), 265 XUSB_PADCTL_USB2_OTG_PAD_CTL0_HS_CURR_LEVEL | 266 XUSB_PADCTL_USB2_OTG_PAD_CTL0_HS_SLEW | 267 XUSB_PADCTL_USB2_OTG_PAD_CTL0_LS_RSLEW | 268 XUSB_PADCTL_USB2_OTG_PAD_CTL0_PD | 269 XUSB_PADCTL_USB2_OTG_PAD_CTL0_PD2 | 270 XUSB_PADCTL_USB2_OTG_PAD_CTL0_PD_ZI); 271 272 tegra_reg_set_clear(sc->sc_bst, sc->sc_bsh, 273 XUSB_PADCTL_USB2_OTG_PAD0_CTL1_REG, 274 __SHIFTIN(htra, 275 XUSB_PADCTL_USB2_OTG_PAD_CTL1_TERM_RANGE_ADJ) | 276 __SHIFTIN(hic, 277 XUSB_PADCTL_USB2_OTG_PAD_CTL1_HS_IREF_CAP), 278 XUSB_PADCTL_USB2_OTG_PAD_CTL1_TERM_RANGE_ADJ | 279 XUSB_PADCTL_USB2_OTG_PAD_CTL1_HS_IREF_CAP | 280 XUSB_PADCTL_USB2_OTG_PAD_CTL1_PD_DR | 281 XUSB_PADCTL_USB2_OTG_PAD_CTL1_PD_CHRP_FORCE_POWERUP | 282 XUSB_PADCTL_USB2_OTG_PAD_CTL1_PD_DISC_FORCE_POWERUP); 283 tegra_reg_set_clear(sc->sc_bst, sc->sc_bsh, 284 XUSB_PADCTL_USB2_OTG_PAD1_CTL1_REG, 285 __SHIFTIN(htra, 286 XUSB_PADCTL_USB2_OTG_PAD_CTL1_TERM_RANGE_ADJ) | 287 __SHIFTIN(hic, 288 XUSB_PADCTL_USB2_OTG_PAD_CTL1_HS_IREF_CAP), 289 XUSB_PADCTL_USB2_OTG_PAD_CTL1_TERM_RANGE_ADJ | 290 XUSB_PADCTL_USB2_OTG_PAD_CTL1_HS_IREF_CAP | 291 XUSB_PADCTL_USB2_OTG_PAD_CTL1_PD_DR | 292 XUSB_PADCTL_USB2_OTG_PAD_CTL1_PD_CHRP_FORCE_POWERUP | 293 XUSB_PADCTL_USB2_OTG_PAD_CTL1_PD_DISC_FORCE_POWERUP); 294 tegra_reg_set_clear(sc->sc_bst, sc->sc_bsh, 295 XUSB_PADCTL_USB2_OTG_PAD2_CTL1_REG, 296 __SHIFTIN(htra, 297 XUSB_PADCTL_USB2_OTG_PAD_CTL1_TERM_RANGE_ADJ) | 298 __SHIFTIN(hic, 299 XUSB_PADCTL_USB2_OTG_PAD_CTL1_HS_IREF_CAP), 300 XUSB_PADCTL_USB2_OTG_PAD_CTL1_TERM_RANGE_ADJ | 301 XUSB_PADCTL_USB2_OTG_PAD_CTL1_HS_IREF_CAP | 302 XUSB_PADCTL_USB2_OTG_PAD_CTL1_PD_DR | 303 XUSB_PADCTL_USB2_OTG_PAD_CTL1_PD_CHRP_FORCE_POWERUP | 304 XUSB_PADCTL_USB2_OTG_PAD_CTL1_PD_DISC_FORCE_POWERUP); 305 306 //tegra_reg_set_clear(sc->sc_bst, sc->sc_bsh, XUSB_PADCTL_USB2_BATTERY_CHRG_BIASPAD_REG, 0, 1); /* PD_OTG */ 307 tegra_reg_set_clear(sc->sc_bst, sc->sc_bsh, XUSB_PADCTL_USB2_OTG_PAD0_CTL0_REG, 0, XUSB_PADCTL_USB2_OTG_PAD_CTL0_PD); 308 tegra_reg_set_clear(sc->sc_bst, sc->sc_bsh, XUSB_PADCTL_USB2_OTG_PAD1_CTL0_REG, 0, XUSB_PADCTL_USB2_OTG_PAD_CTL0_PD); 309 tegra_reg_set_clear(sc->sc_bst, sc->sc_bsh, XUSB_PADCTL_USB2_OTG_PAD2_CTL0_REG, 0, XUSB_PADCTL_USB2_OTG_PAD_CTL0_PD); 310 tegra_reg_set_clear(sc->sc_bst, sc->sc_bsh, XUSB_PADCTL_USB2_OTG_PAD0_CTL0_REG, 0, XUSB_PADCTL_USB2_OTG_PAD_CTL0_PD2); 311 tegra_reg_set_clear(sc->sc_bst, sc->sc_bsh, XUSB_PADCTL_USB2_OTG_PAD1_CTL0_REG, 0, XUSB_PADCTL_USB2_OTG_PAD_CTL0_PD2); 312 tegra_reg_set_clear(sc->sc_bst, sc->sc_bsh, XUSB_PADCTL_USB2_OTG_PAD2_CTL0_REG, 0, XUSB_PADCTL_USB2_OTG_PAD_CTL0_PD2); 313 tegra_reg_set_clear(sc->sc_bst, sc->sc_bsh, XUSB_PADCTL_USB2_OTG_PAD0_CTL0_REG, 0, XUSB_PADCTL_USB2_OTG_PAD_CTL0_PD_ZI); 314 tegra_reg_set_clear(sc->sc_bst, sc->sc_bsh, XUSB_PADCTL_USB2_OTG_PAD1_CTL0_REG, 0, XUSB_PADCTL_USB2_OTG_PAD_CTL0_PD_ZI); 315 tegra_reg_set_clear(sc->sc_bst, sc->sc_bsh, XUSB_PADCTL_USB2_OTG_PAD2_CTL0_REG, 0, XUSB_PADCTL_USB2_OTG_PAD_CTL0_PD_ZI); 316 tegra_reg_set_clear(sc->sc_bst, sc->sc_bsh, XUSB_PADCTL_USB2_OTG_PAD0_CTL1_REG, 0, XUSB_PADCTL_USB2_OTG_PAD_CTL1_PD_DR); 317 tegra_reg_set_clear(sc->sc_bst, sc->sc_bsh, XUSB_PADCTL_USB2_OTG_PAD1_CTL1_REG, 0, XUSB_PADCTL_USB2_OTG_PAD_CTL1_PD_DR); 318 tegra_reg_set_clear(sc->sc_bst, sc->sc_bsh, XUSB_PADCTL_USB2_OTG_PAD2_CTL1_REG, 0, XUSB_PADCTL_USB2_OTG_PAD_CTL1_PD_DR); 319 tegra_reg_set_clear(sc->sc_bst, sc->sc_bsh, XUSB_PADCTL_USB2_BIAS_PAD_CTL0_REG, 0, XUSB_PADCTL_USB2_BIAS_PAD_CTL0_PD); 320 tegra_reg_set_clear(sc->sc_bst, sc->sc_bsh, XUSB_PADCTL_USB2_BIAS_PAD_CTL0_REG, 0, XUSB_PADCTL_USB2_BIAS_PAD_CTL0_PD_TRK); 321 322 tegra_reg_set_clear(sc->sc_bst, sc->sc_bsh, XUSB_PADCTL_ELPG_PROGRAM_REG, 323 0, XUSB_PADCTL_ELPG_PROGRAM_SSP0_ELPG_CLAMP_EN); 324 tegra_reg_set_clear(sc->sc_bst, sc->sc_bsh, XUSB_PADCTL_ELPG_PROGRAM_REG, 325 0, XUSB_PADCTL_ELPG_PROGRAM_SSP0_ELPG_CLAMP_EN_EARLY); 326 tegra_reg_set_clear(sc->sc_bst, sc->sc_bsh, XUSB_PADCTL_ELPG_PROGRAM_REG, 327 0, XUSB_PADCTL_ELPG_PROGRAM_SSP0_ELPG_VCORE_DOWN); 328 329 DELAY(200); 330 tegra_reg_set_clear(sc->sc_bst, sc->sc_bsh, XUSB_PADCTL_ELPG_PROGRAM_REG, 0, __BIT(26)); 331 DELAY(200); 332 tegra_reg_set_clear(sc->sc_bst, sc->sc_bsh, XUSB_PADCTL_ELPG_PROGRAM_REG, 0, __BIT(25)); 333 DELAY(200); 334 tegra_reg_set_clear(sc->sc_bst, sc->sc_bsh, XUSB_PADCTL_ELPG_PROGRAM_REG, 0, __BIT(24)); 335 DELAY(200); 336 337 tegra_reg_set_clear(sc->sc_bst, sc->sc_bsh, XUSB_PADCTL_OC_DET_REG, 0, __BITS(22,16)); 338 tegra_reg_set_clear(sc->sc_bst, sc->sc_bsh, XUSB_PADCTL_OC_DET_REG, __BIT(4), 0); 339 tegra_reg_set_clear(sc->sc_bst, sc->sc_bsh, XUSB_PADCTL_OC_DET_REG, __BIT(8), 0); 340 tegra_reg_set_clear(sc->sc_bst, sc->sc_bsh, XUSB_PADCTL_OC_DET_REG, __BIT(9), 0); 341 342 #ifdef TEGRA_XUSBPAD_DEBUG 343 val = bus_space_read_4(sc->sc_bst, sc->sc_bsh, XUSB_PADCTL_USB2_PAD_MUX_REG); 344 device_printf(sc->sc_dev, "XUSB_PADCTL_USB2_PAD_MUX_REG is 0x%x\n", val); 345 val = bus_space_read_4(sc->sc_bst, sc->sc_bsh, XUSB_PADCTL_USB2_PORT_CAP_REG); 346 device_printf(sc->sc_dev, "XUSB_PADCTL_USB2_PORT_CAP_REG is 0x%x\n", val); 347 val = bus_space_read_4(sc->sc_bst, sc->sc_bsh, XUSB_PADCTL_SS_PORT_MAP_REG); 348 device_printf(sc->sc_dev, "XUSB_PADCTL_SS_PORT_MAP_REG is 0x%x\n", val); 349 350 padregdump(); 351 #endif 352 } 353
Indexes created Wed Oct 15 16:09:53 GMT 2025