imx6_ccmreg.h revision 1.1 1 1.1 skrll /* $NetBSD: imx6_ccmreg.h,v 1.1 2020/12/23 14:42:38 skrll Exp $ */
2 1.1 skrll
3 1.1 skrll /*
4 1.1 skrll * Copyright (c) 2014 Ryo Shimizu <ryo (at) nerv.org>
5 1.1 skrll * All rights reserved.
6 1.1 skrll *
7 1.1 skrll * Redistribution and use in source and binary forms, with or without
8 1.1 skrll * modification, are permitted provided that the following conditions
9 1.1 skrll * are met:
10 1.1 skrll * 1. Redistributions of source code must retain the above copyright
11 1.1 skrll * notice, this list of conditions and the following disclaimer.
12 1.1 skrll * 2. Redistributions in binary form must reproduce the above copyright
13 1.1 skrll * notice, this list of conditions and the following disclaimer in the
14 1.1 skrll * documentation and/or other materials provided with the distribution.
15 1.1 skrll *
16 1.1 skrll * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17 1.1 skrll * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
18 1.1 skrll * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
19 1.1 skrll * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
20 1.1 skrll * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
21 1.1 skrll * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
22 1.1 skrll * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 1.1 skrll * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
24 1.1 skrll * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
25 1.1 skrll * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
26 1.1 skrll * POSSIBILITY OF SUCH DAMAGE.
27 1.1 skrll */
28 1.1 skrll
29 1.1 skrll #ifndef _ARM_NXP_IMX6_CCMREG_H
30 1.1 skrll #define _ARM_NXP_IMX6_CCMREG_H
31 1.1 skrll
32 1.1 skrll #include <sys/cdefs.h>
33 1.1 skrll
34 1.1 skrll /*
35 1.1 skrll * PERIPHCLK_N is an arm root clock divider for MPcore interrupt controller.
36 1.1 skrll * PERIPHCLK_N is equal to, or greater than two.
37 1.1 skrll * see "Cortex-A9 MPCore Technical Reference Manual" -
38 1.1 skrll * Chapter 5: Clocks, Resets, and Power Management, 5.1: Clocks.
39 1.1 skrll */
40 1.1 skrll #ifndef IMX6_PERIPHCLK_N
41 1.1 skrll #define IMX6_PERIPHCLK_N 2
42 1.1 skrll #endif
43 1.1 skrll
44 1.1 skrll #ifndef IMX6_CKIL_FREQ
45 1.1 skrll #define IMX6_CKIL_FREQ 32768
46 1.1 skrll #endif
47 1.1 skrll #ifndef IMX6_CKIH_FREQ
48 1.1 skrll #define IMX6_CKIH_FREQ 0
49 1.1 skrll #endif
50 1.1 skrll #ifndef IMX6_OSC_FREQ
51 1.1 skrll #define IMX6_OSC_FREQ (24 * 1000 * 1000) /* 24MHz */
52 1.1 skrll #endif
53 1.1 skrll #ifndef IMX6_ANACLK1_FREQ
54 1.1 skrll #define IMX6_ANACLK1_FREQ 0
55 1.1 skrll #endif
56 1.1 skrll #ifndef IMX6_ANACLK2_FREQ
57 1.1 skrll #define IMX6_ANACLK2_FREQ 0
58 1.1 skrll #endif
59 1.1 skrll
60 1.1 skrll #define CCM_CCR 0x00000000
61 1.1 skrll #define CCM_CCR_RBC_EN __BIT(27)
62 1.1 skrll #define CCM_CCR_REG_BYPASS_COUNT __BITS(26, 21)
63 1.1 skrll #define CCM_CCR_WB_COUNT __BITS(18, 16)
64 1.1 skrll #define CCM_CCR_COSC_EN __BIT(12)
65 1.1 skrll #define CCM_CCR_OSCNT __BITS(7, 0)
66 1.1 skrll
67 1.1 skrll #define CCM_CCDR 0x00000004
68 1.1 skrll #define CCM_CSR 0x00000008
69 1.1 skrll #define CCM_CCSR 0x0000000c
70 1.1 skrll #define CCM_CCSR_PLL3_PFD1_DIS_MASK __BIT(15)
71 1.1 skrll #define CCM_CCSR_PLL3_PFD0_DIS_MASK __BIT(14)
72 1.1 skrll #define CCM_CCSR_PLL3_PFD3_DIS_MASK __BIT(13)
73 1.1 skrll #define CCM_CCSR_PLL3_PFD2_DIS_MASK __BIT(12)
74 1.1 skrll #define CCM_CCSR_PLL2_PFD1_594M_DIS_MASK __BIT(11)
75 1.1 skrll #define CCM_CCSR_PLL2_PFD0_DIS_MASK __BIT(10)
76 1.1 skrll #define CCM_CCSR_PLL2_PFD2_DIS_MASK __BIT(9)
77 1.1 skrll #define CCM_CCSR_STEP_SEL __BIT(8)
78 1.1 skrll #define CCM_CCSR_PLL1_SW_CLK_SEL __BIT(2)
79 1.1 skrll #define CCM_CCSR_PLL3_SW_CLK_SEL __BIT(0)
80 1.1 skrll #define CCM_CACRR 0x00000010
81 1.1 skrll #define CCM_CACRR_ARM_PODF __BITS(2, 0)
82 1.1 skrll
83 1.1 skrll #define CCM_CBCDR 0x00000014
84 1.1 skrll #define CCM_CBCDR_PERIPH_CLK2_PODF __BITS(29, 27)
85 1.1 skrll /* source of mmdc_ch1_axi_clk_root */
86 1.1 skrll #define CCM_CBCDR_PERIPH2_CLK_SEL __BIT(26)
87 1.1 skrll /* source of mmdc_ch0_axi_clk_root */
88 1.1 skrll #define CCM_CBCDR_PERIPH_CLK_SEL __BIT(25)
89 1.1 skrll #define CCM_CBCDR_MMDC_CH0_AXI_PODF __BITS(21, 19)
90 1.1 skrll #define CCM_CBCDR_AXI_PODF __BITS(18, 16)
91 1.1 skrll #define CCM_CBCDR_AHB_PODF __BITS(12, 10)
92 1.1 skrll #define CCM_CBCDR_IPG_PODF __BITS(9, 8)
93 1.1 skrll #define CCM_CBCDR_AXI_ALT_SEL __BIT(7)
94 1.1 skrll #define CCM_CBCDR_AXI_SEL __BITS(7, 6)
95 1.1 skrll #define CCM_CBCDR_MMDC_CH1_AXI_PODF __BITS(5, 3)
96 1.1 skrll #define CCM_CBCDR_PERIPH2_CLK2_PODF __BITS(2, 0)
97 1.1 skrll
98 1.1 skrll #define CCM_CBCMR 0x00000018
99 1.1 skrll #define CCM_CBCMR_GPU3D_SHADER_PODF __BITS(31, 29)
100 1.1 skrll #define CCM_CBCMR_GPU3D_CORE_PODF __BITS(28, 26)
101 1.1 skrll #define CCM_CBCMR_GPU2D_CORE_CLK_PODF __BITS(25, 23)
102 1.1 skrll #define CCM_CBCMR_PRE_PERIPH2_CLK_SEL __BITS(22, 21)
103 1.1 skrll #define CCM_CBCMR_PERIPH2_CLK2_SEL __BIT(20)
104 1.1 skrll #define CCM_CBCMR_PRE_PERIPH_CLK_SEL __BITS(19, 18)
105 1.1 skrll #define CCM_CBCMR_GPU2D_CLK_SEL __BITS(17, 16)
106 1.1 skrll #define CCM_CBCMR_VPU_AXI_CLK_SEL __BITS(15, 14)
107 1.1 skrll #define CCM_CBCMR_PERIPH_CLK2_SEL __BITS(13, 12)
108 1.1 skrll #define CCM_CBCMR_VDOAXI_CLK_SEL __BIT(11)
109 1.1 skrll #define CCM_CBCMR_PCIE_AXI_CLK_SEL __BIT(10)
110 1.1 skrll #define CCM_CBCMR_GPU3D_SHADER_CLK_SEL __BITS(9, 8)
111 1.1 skrll #define CCM_CBCMR_GPU3D_CORE_CLK_SEL __BITS(5, 4)
112 1.1 skrll #define CCM_CBCMR_GPU3D_AXI_CLK_SEL __BIT(1)
113 1.1 skrll #define CCM_CBCMR_GPU2D_AXI_CLK_SEL __BIT(0)
114 1.1 skrll
115 1.1 skrll #define CCM_CSCMR1 0x0000001c
116 1.1 skrll #define CCM_CSCMR1_ACLK_EIM_SLOW_SEL __BITS(30, 29)
117 1.1 skrll #define CCM_CSCMR1_ACLK_SEL __BITS(28, 27)
118 1.1 skrll #define CCM_CSCMR1_ACLK_EIM_SLOW_PODF __BITS(25, 23)
119 1.1 skrll #define CCM_CSCMR1_ACLK_PODF __BITS(22, 20)
120 1.1 skrll #define CCM_CSCMR1_USDHC4_CLK_SEL __BIT(19)
121 1.1 skrll #define CCM_CSCMR1_USDHC3_CLK_SEL __BIT(18)
122 1.1 skrll #define CCM_CSCMR1_USDHC2_CLK_SEL __BIT(17)
123 1.1 skrll #define CCM_CSCMR1_USDHC1_CLK_SEL __BIT(16)
124 1.1 skrll #define CCM_CSCMR1_SSI3_CLK_SEL __BITS(15, 14)
125 1.1 skrll #define CCM_CSCMR1_SSI2_CLK_SEL __BITS(13, 12)
126 1.1 skrll #define CCM_CSCMR1_SSI1_CLK_SEL __BITS(11, 10)
127 1.1 skrll #define CCM_CSCMR1_PERCLK_PODF __BITS(5, 0)
128 1.1 skrll
129 1.1 skrll #define CCM_CSCMR2 0x00000020
130 1.1 skrll #define CCM_CSCMR2_ESAI_CLK_SEL __BITS(20, 19)
131 1.1 skrll #define CCM_CSCMR2_LDB_DI1_IPU_DIV __BIT(11)
132 1.1 skrll #define CCM_CSCMR2_LDB_DI0_IPU_DIV __BIT(10)
133 1.1 skrll #define CCM_CSCMR2_CAN_CLK_PODF __BITS(7, 2)
134 1.1 skrll
135 1.1 skrll #define CCM_CSCDR1 0x00000024
136 1.1 skrll #define CCM_CSCDR1_VPU_AXI_PODF __BITS(27, 25)
137 1.1 skrll #define CCM_CSCDR1_USDHC4_PODF __BITS(24, 22)
138 1.1 skrll #define CCM_CSCDR1_USDHC3_PODF __BITS(21, 19)
139 1.1 skrll #define CCM_CSCDR1_USDHC2_PODF __BITS(18, 16)
140 1.1 skrll #define CCM_CSCDR1_USDHC1_PODF __BITS(13, 11)
141 1.1 skrll #define CCM_CSCDR1_UART_CLK_PODF __BITS(5, 0)
142 1.1 skrll
143 1.1 skrll #define CCM_CS1CDR 0x00000028
144 1.1 skrll #define CCM_CS1CDR_ESAI_CLK_PODF __BITS(27, 25)
145 1.1 skrll #define CCM_CS1CDR_SSI3_CLK_PRED __BITS(24, 22)
146 1.1 skrll #define CCM_CS1CDR_SSI3_CLK_PODF __BITS(21, 16)
147 1.1 skrll #define CCM_CS1CDR_ESAI_CLK_PRED __BITS(11, 9)
148 1.1 skrll #define CCM_CS1CDR_SSI1_CLK_PRED __BITS(8, 6)
149 1.1 skrll #define CCM_CS1CDR_SSI1_CLK_PODF __BITS(5, 0)
150 1.1 skrll
151 1.1 skrll #define CCM_CS2CDR 0x0000002c
152 1.1 skrll #define CCM_CS2CDR_ENFC_CLK_PODF __BITS(26, 21)
153 1.1 skrll #define CCM_CS2CDR_ENFC_CLK_PRED __BITS(20, 18)
154 1.1 skrll #define CCM_CS2CDR_ENFC_CLK_SEL __BITS(17, 16)
155 1.1 skrll #define CCM_CS2CDR_LDB_DI1_CLK_SEL __BITS(14, 12)
156 1.1 skrll #define CCM_CS2CDR_LDB_DI0_CLK_SEL __BITS(11, 9)
157 1.1 skrll #define CCM_CS2CDR_SSI2_CLK_PRED __BITS(8, 6)
158 1.1 skrll #define CCM_CS2CDR_SSI2_CLK_PODF __BITS(5, 0)
159 1.1 skrll
160 1.1 skrll #define CCM_CDCDR 0x00000030
161 1.1 skrll #define CCM_CDCDR_HSI_TX_PODF __BITS(31, 29)
162 1.1 skrll #define CCM_CDCDR_HSI_TX_CLK_SEL __BIT(28)
163 1.1 skrll #define CCM_CDCDR_SPDIF0_CLK_PRED __BITS(27, 25)
164 1.1 skrll #define CCM_CDCDR_SPDIF0_CLK_PODF __BITS(24, 22)
165 1.1 skrll #define CCM_CDCDR_SPDIF0_CLK_SEL __BITS(21, 20)
166 1.1 skrll #define CCM_CDCDR_SPDIF1_CLK_PRED __BITS(14, 12)
167 1.1 skrll #define CCM_CDCDR_SPDIF1_CLK_PODF __BITS(11, 9)
168 1.1 skrll #define CCM_CDCDR_SPDIF1_CLK_SEL __BITS(8, 7)
169 1.1 skrll
170 1.1 skrll #define CCM_CHSCCDR 0x00000034
171 1.1 skrll #define CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL __BITS(17, 15)
172 1.1 skrll #define CCM_CHSCCDR_IPU1_DI1_PODF __BITS(14, 12)
173 1.1 skrll #define CCM_CHSCCDR_IPU1_DI1_CLK_SEL __BITS(11, 9)
174 1.1 skrll #define CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL __BITS(8, 6)
175 1.1 skrll #define CCM_CHSCCDR_IPU1_DI0_PODF __BITS(5, 3)
176 1.1 skrll #define CCM_CHSCCDR_IPU1_DI0_CLK_SEL __BITS(2, 0)
177 1.1 skrll
178 1.1 skrll #define CCM_CSCDR2 0x00000038
179 1.1 skrll #define CCM_CSCDR2_ECSPI_CLK_PODF __BITS(24, 19)
180 1.1 skrll #define CCM_CSCDR2_IPU2_DI1_PRE_CLK_SEL __BITS(17, 15)
181 1.1 skrll #define CCM_CSCDR2_IPU2_DI1_PODF __BITS(14, 12)
182 1.1 skrll #define CCM_CSCDR2_IPU2_DI1_CLK_SEL __BITS(11, 9)
183 1.1 skrll #define CCM_CSCDR2_IPU2_DI0_PRE_CLK_SEL __BITS(8, 6)
184 1.1 skrll #define CCM_CSCDR2_IPU2_DI0_PODF __BITS(5, 3)
185 1.1 skrll #define CCM_CSCDR2_IPU2_DI0_CLK_SEL __BITS(2, 0)
186 1.1 skrll
187 1.1 skrll #define CCM_CDHIPR 0x00000048
188 1.1 skrll #define CCM_CDHIPR_ARM_PODF_BUSY __BIT(16)
189 1.1 skrll #define CCM_CDHIPR_PERIPH_CLK_SEL_BUSY __BIT(5)
190 1.1 skrll #define CCM_CDHIPR_MMDC_CH0_PODF_BUSY __BIT(4)
191 1.1 skrll #define CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY __BIT(3)
192 1.1 skrll #define CCM_CDHIPR_MMDC_CH1_PODF_BUSY __BIT(2)
193 1.1 skrll #define CCM_CDHIPR_AHB_PODF_BUSY __BIT(1)
194 1.1 skrll #define CCM_CDHIPR_AXI_PODF_BUSY __BIT(0)
195 1.1 skrll
196 1.1 skrll #define CCM_CSCDR3 0x0000003c
197 1.1 skrll #define CCM_CSCDR3_IPU2_HSP_PODF __BITS(18, 16)
198 1.1 skrll #define CCM_CSCDR3_IPU2_HSP_CLK_SEL __BITS(15, 14)
199 1.1 skrll #define CCM_CSCDR3_IPU1_HSP_PODF __BITS(13, 11)
200 1.1 skrll #define CCM_CSCDR3_IPU1_HSP_CLK_SEL __BITS(10, 9)
201 1.1 skrll
202 1.1 skrll #define CCM_CCOSR 0x00000060
203 1.1 skrll #define CCM_CCOSR_CLKO2_EN __BIT(24)
204 1.1 skrll #define CCM_CCOSR_CLKO2_DIV __BITS(23, 21)
205 1.1 skrll #define CCM_CCOSR_CLKO2_SEL __BITS(20, 16)
206 1.1 skrll #define CCM_CCOSR_CLK_OUT_SEL __BIT(8)
207 1.1 skrll #define CCM_CCOSR_CLKO1_EN __BIT(7)
208 1.1 skrll #define CCM_CCOSR_CLKO1_DIV __BITS(6, 4)
209 1.1 skrll #define CCM_CCOSR_CLKO1_SEL __BITS(3, 0)
210 1.1 skrll
211 1.1 skrll #define CCM_CCGR0 0x00000068
212 1.1 skrll #define CCM_CCGR0_DTCP_CLK_ENABLE __BITS(29, 28)
213 1.1 skrll #define CCM_CCGR0_DCIC2_CLK_ENABLE __BITS(27, 26)
214 1.1 skrll #define CCM_CCGR0_DCIC1_CLK_ENABLE __BITS(25, 24)
215 1.1 skrll #define CCM_CCGR0_ARM_DBG_CLK_ENABLE __BITS(23, 22)
216 1.1 skrll #define CCM_CCGR0_CAN2_SERIAL_CLK_ENABLE __BITS(21, 20)
217 1.1 skrll #define CCM_CCGR0_CAN2_CLK_ENABLE __BITS(19, 18)
218 1.1 skrll #define CCM_CCGR0_CAN1_SERIAL_CLK_ENABLE __BITS(17, 16)
219 1.1 skrll #define CCM_CCGR0_CAN1_CLK_ENABLE __BITS(15, 14)
220 1.1 skrll #define CCM_CCGR0_CAAM_WRAPPER_IPG_ENABLE __BITS(13, 12)
221 1.1 skrll #define CCM_CCGR0_CAAM_WRAPPER_ACLK_ENABLE __BITS(11, 10)
222 1.1 skrll #define CCM_CCGR0_CAAM_SECURE_MEM_CLK_ENABLE __BITS(9, 8)
223 1.1 skrll #define CCM_CCGR0_ASRC_CLK_ENABLE __BITS(7, 6)
224 1.1 skrll #define CCM_CCGR0_APBHDMA_HCLK_ENABLE __BITS(5, 4)
225 1.1 skrll #define CCM_CCGR0_AIPS_TZ2_CLK_ENABLE __BITS(3, 2)
226 1.1 skrll #define CCM_CCGR0_AIPS_TZ1_CLK_ENABLE __BITS(1, 0)
227 1.1 skrll #define CCM_CCGR1 0x0000006C
228 1.1 skrll #define CCM_CCGR1_GPU3D_CLK_ENABLE __BITS(27, 26)
229 1.1 skrll #define CCM_CCGR1_GPU2D_CLK_ENABLE __BITS(25, 24)
230 1.1 skrll #define CCM_CCGR1_GPT_SERIAL_CLK_ENABLE __BITS(23, 22)
231 1.1 skrll #define CCM_CCGR1_GPT_CLK_ENABLE __BITS(21, 20)
232 1.1 skrll #define CCM_CCGR1_ESAI_CLK_ENABLE __BITS(17, 16)
233 1.1 skrll #define CCM_CCGR1_EPIT2_CLK_ENABLE __BITS(15, 14)
234 1.1 skrll #define CCM_CCGR1_EPIT1_CLK_ENABLE __BITS(13, 12)
235 1.1 skrll #define CCM_CCGR1_ENET_CLK_ENABLE __BITS(11, 10)
236 1.1 skrll #define CCM_CCGR1_I2C4_CLK_ENABLE __BITS(9, 8) /* i.MX6DL */
237 1.1 skrll #define CCM_CCGR1_ECSPI5_CLK_ENABLE __BITS(9, 8) /* i.MX6Q */
238 1.1 skrll #define CCM_CCGR1_ECSPI4_CLK_ENABLE __BITS(7, 6)
239 1.1 skrll #define CCM_CCGR1_ECSPI3_CLK_ENABLE __BITS(5, 4)
240 1.1 skrll #define CCM_CCGR1_ECSPI2_CLK_ENABLE __BITS(3, 2)
241 1.1 skrll #define CCM_CCGR1_ECSPI1_CLK_ENABLE __BITS(1, 0)
242 1.1 skrll #define CCM_CCGR2 0x00000070
243 1.1 skrll #define CCM_CCGR2_IPSYNC_VDOA_IPG_CLK_ENABLE __BITS(27, 26)
244 1.1 skrll #define CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_CLK_ENABLE __BITS(25, 24)
245 1.1 skrll #define CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPG_CLK_ENABLE __BITS(23, 22)
246 1.1 skrll #define CCM_CCGR2_IPMUX3_CLK_ENABLE __BITS(21, 20)
247 1.1 skrll #define CCM_CCGR2_IPMUX2_CLK_ENABLE __BITS(19, 18)
248 1.1 skrll #define CCM_CCGR2_IPMUX1_CLK_ENABLE __BITS(17, 16)
249 1.1 skrll #define CCM_CCGR2_IOMUX_IPT_CLK_IO_CLK_ENABLE __BITS(15, 14)
250 1.1 skrll #define CCM_CCGR2_IIM_CLK_ENABLE __BITS(13, 12)
251 1.1 skrll #define CCM_CCGR2_I2C3_SERIAL_CLK_ENABLE __BITS(11, 10)
252 1.1 skrll #define CCM_CCGR2_I2C2_SERIAL_CLK_ENABLE __BITS(9, 8)
253 1.1 skrll #define CCM_CCGR2_I2C1_SERIAL_CLK_ENABLE __BITS(7, 6)
254 1.1 skrll #define CCM_CCGR2_HDMI_TX_ISFRCLK_ENABLE __BITS(5, 4)
255 1.1 skrll #define CCM_CCGR2_HDMI_TX_IAHBCLK_ENABLE __BITS(1, 0)
256 1.1 skrll #define CCM_CCGR3 0x00000074
257 1.1 skrll #define CCM_CCGR3_OPENVGAXICLK_CLK_ROOT_ENABLE __BITS(31, 30)
258 1.1 skrll #define CCM_CCGR3_OCRAM_CLK_ENABLE __BITS(29, 28)
259 1.1 skrll #define CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_ENABLE __BITS(25, 24)
260 1.1 skrll #define CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1_ENABLE __BITS(23, 22)
261 1.1 skrll #define CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_ENABLE __BITS(21, 20)
262 1.1 skrll #define CCM_CCGR3_MLB_CLK_ENABLE __BITS(19, 18)
263 1.1 skrll #define CCM_CCGR3_MIPI_CORE_CFG_CLK_ENABLE __BITS(17, 16)
264 1.1 skrll #define CCM_CCGR3_LDB_DI1_CLK_ENABLE __BITS(15, 14)
265 1.1 skrll #define CCM_CCGR3_LDB_DI0_CLK_ENABLE __BITS(13, 12)
266 1.1 skrll #define CCM_CCGR3_IPU2_IPU_DI1_CLK_ENABLE __BITS(11, 10)
267 1.1 skrll #define CCM_CCGR3_IPU2_IPU_DI0_CLK_ENABLE __BITS(9, 8)
268 1.1 skrll #define CCM_CCGR3_IPU2_IPU_CLK_ENABLE __BITS(7, 6)
269 1.1 skrll #define CCM_CCGR3_IPU1_IPU_DI1_CLK_ENABLE __BITS(5, 4)
270 1.1 skrll #define CCM_CCGR3_IPU1_IPU_DI0_CLK_ENABLE __BITS(3, 2)
271 1.1 skrll #define CCM_CCGR3_IPU1_IPU_CLK_ENABLE __BITS(1, 0)
272 1.1 skrll #define CCM_CCGR4 0x00000078
273 1.1 skrll #define CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_CLK_ENABLE __BITS(31, 30)
274 1.1 skrll #define CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_CLK_ENABLE __BITS(29, 28)
275 1.1 skrll #define CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_CLK_ENABLE __BITS(27, 26)
276 1.1 skrll #define CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_CLK_ENABLE __BITS(25, 24)
277 1.1 skrll #define CCM_CCGR4_PWM4_CLK_ENABLE __BITS(23, 22)
278 1.1 skrll #define CCM_CCGR4_PWM3_CLK_ENABLE __BITS(21, 20)
279 1.1 skrll #define CCM_CCGR4_PWM2_CLK_ENABLE __BITS(19, 18)
280 1.1 skrll #define CCM_CCGR4_PWM1_CLK_ENABLE __BITS(17, 16)
281 1.1 skrll #define CCM_CCGR4_PL301_MX6QPER2_MAINCLK_ENABLE __BITS(15, 14)
282 1.1 skrll #define CCM_CCGR4_PL301_MX6QPER1_BCHCLK_ENABLE __BITS(13, 12)
283 1.1 skrll #define CCM_CCGR4_PL301_MX6QFAST1_S133CLK_ENABLE __BITS(9, 8)
284 1.1 skrll #define CCM_CCGR4_PCIE_ROOT_ENABLE __BITS(1, 0)
285 1.1 skrll #define CCM_CCGR5 0x0000007c
286 1.1 skrll #define CCM_CCGR5_UART_SERIAL_CLK_ENABLE __BITS(27, 26)
287 1.1 skrll #define CCM_CCGR5_UART_CLK_ENABLE __BITS(25, 24)
288 1.1 skrll #define CCM_CCGR5_SSI3_CLK_ENABLE __BITS(23, 22)
289 1.1 skrll #define CCM_CCGR5_SSI2_CLK_ENABLE __BITS(21, 20)
290 1.1 skrll #define CCM_CCGR5_SSI1_CLK_ENABLE __BITS(19, 18)
291 1.1 skrll #define CCM_CCGR5_SPDIF_CLK_ENABLE __BITS(15, 14)
292 1.1 skrll #define CCM_CCGR5_SPBA_CLK_ENABLE __BITS(13, 12)
293 1.1 skrll #define CCM_CCGR5_SDMA_CLK_ENABLE __BITS(7, 6)
294 1.1 skrll #define CCM_CCGR5_SATA_CLK_ENABLE __BITS(5, 4)
295 1.1 skrll #define CCM_CCGR5_ROM_CLK_ENABLE __BITS(1, 0)
296 1.1 skrll #define CCM_CCGR6 0x00000080
297 1.1 skrll #define CCM_CCGR6_VPU_CLK_ENABLE __BITS(15, 14)
298 1.1 skrll #define CCM_CCGR6_VDOAXICLK_CLK_ENABLE __BITS(13, 12)
299 1.1 skrll #define CCM_CCGR6_EIM_SLOW_CLK_ENABLE __BITS(11, 10)
300 1.1 skrll #define CCM_CCGR6_USDHC4_CLK_ENABLE __BITS(9, 8)
301 1.1 skrll #define CCM_CCGR6_USDHC3_CLK_ENABLE __BITS(7, 6)
302 1.1 skrll #define CCM_CCGR6_USDHC2_CLK_ENABLE __BITS(5, 4)
303 1.1 skrll #define CCM_CCGR6_USDHC1_CLK_ENABLE __BITS(3, 2)
304 1.1 skrll #define CCM_CCGR6_USBOH3_CLK_ENABLE __BITS(1, 0)
305 1.1 skrll
306 1.1 skrll #define CCM_ANALOG_BASE 0x00004000
307 1.1 skrll #define CCM_ANALOG_SIZE 0x00001000
308 1.1 skrll
309 1.1 skrll #define CCM_ANALOG_PLL_ARM 0x00000000 /* = 020c8000 */
310 1.1 skrll #define CCM_ANALOG_PLL_ARM_SET 0x00000004
311 1.1 skrll #define CCM_ANALOG_PLL_ARM_CLR 0x00000008
312 1.1 skrll #define CCM_ANALOG_PLL_ARM_TOG 0x0000000c
313 1.1 skrll #define CCM_ANALOG_PLL_ARM_LOCK __BIT(31)
314 1.1 skrll #define CCM_ANALOG_PLL_ARM_PLL_SEL __BIT(19)
315 1.1 skrll #define CCM_ANALOG_PLL_ARM_LVDS_24MHZ_SEL __BIT(18)
316 1.1 skrll #define CCM_ANALOG_PLL_ARM_LVDS_SEL __BIT(17)
317 1.1 skrll #define CCM_ANALOG_PLL_ARM_BYPASS __BIT(16)
318 1.1 skrll #define CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC __BITS(15, 14)
319 1.1 skrll #define CCM_ANALOG_PLL_ARM_ENABLE __BIT(13)
320 1.1 skrll #define CCM_ANALOG_PLL_ARM_POWERDOWN __BIT(12)
321 1.1 skrll #define CCM_ANALOG_PLL_ARM_DIV_SELECT __BITS(6, 0)
322 1.1 skrll
323 1.1 skrll #define CCM_ANALOG_PLL_LOCK __BIT(31)
324 1.1 skrll #define CCM_ANALOG_PLL_BYPASS __BIT(16)
325 1.1 skrll #define CCM_ANALOG_PLL_BYPASS_CLK_SRC __BITS(15, 14)
326 1.1 skrll #define CCM_ANALOG_PLL_ENABLE __BIT(13)
327 1.1 skrll #define CCM_ANALOG_PLL_POWER __BIT(12)
328 1.1 skrll #define CCM_ANALOG_PLL_EN_USB_CLK __BIT(6)
329 1.1 skrll #define CCM_ANALOG_PLL_DIV_SELECT __BITS(1, 0)
330 1.1 skrll
331 1.1 skrll #define CCM_ANALOG_PLL_USB1 0x00000010
332 1.1 skrll #define CCM_ANALOG_PLL_USB1_SET 0x00000014
333 1.1 skrll #define CCM_ANALOG_PLL_USB1_CLR 0x00000018
334 1.1 skrll #define CCM_ANALOG_PLL_USB1_TOG 0x0000001c
335 1.1 skrll #define CCM_ANALOG_PLL_USB1_LOCK __BIT(31)
336 1.1 skrll #define CCM_ANALOG_PLL_USB1_RESERVED __BIT(20)
337 1.1 skrll #define CCM_ANALOG_PLL_USB1_BYPASS __BIT(16)
338 1.1 skrll #define CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC __BITS(15, 14)
339 1.1 skrll #define CCM_ANALOG_PLL_USB1_ENABLE __BIT(13)
340 1.1 skrll #define CCM_ANALOG_PLL_USB1_POWER __BIT(12)
341 1.1 skrll #define CCM_ANALOG_PLL_USB1_EN_USB_CLK __BIT(6)
342 1.1 skrll #define CCM_ANALOG_PLL_USB1_DIV_SELECT __BITS(1, 0)
343 1.1 skrll
344 1.1 skrll #define CCM_ANALOG_PLL_USB2 0x00000020
345 1.1 skrll #define CCM_ANALOG_PLL_USB2_SET 0x00000024
346 1.1 skrll #define CCM_ANALOG_PLL_USB2_CLR 0x00000028
347 1.1 skrll #define CCM_ANALOG_PLL_USB2_TOG 0x0000002c
348 1.1 skrll #define CCM_ANALOG_PLL_USB2_LOCK __BIT(31)
349 1.1 skrll #define CCM_ANALOG_PLL_USB2_RESERVED __BIT(20)
350 1.1 skrll #define CCM_ANALOG_PLL_USB2_BYPASS __BIT(16)
351 1.1 skrll #define CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC __BITS(15, 14)
352 1.1 skrll #define CCM_ANALOG_PLL_USB2_ENABLE __BIT(13)
353 1.1 skrll #define CCM_ANALOG_PLL_USB2_POWER __BIT(12)
354 1.1 skrll #define CCM_ANALOG_PLL_USB2_EN_USB_CLK __BIT(6)
355 1.1 skrll #define CCM_ANALOG_PLL_USB2_DIV_SELECT __BITS(1, 0)
356 1.1 skrll
357 1.1 skrll #define CCM_ANALOG_PLL_SYS 0x00000030
358 1.1 skrll #define CCM_ANALOG_PLL_SYS_SET 0x00000034
359 1.1 skrll #define CCM_ANALOG_PLL_SYS_CLR 0x00000038
360 1.1 skrll #define CCM_ANALOG_PLL_SYS_TOG 0x0000003c
361 1.1 skrll #define CCM_ANALOG_PLL_SYS_BYPASS __BIT(16)
362 1.1 skrll #define CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC __BITS(15, 14)
363 1.1 skrll #define CCM_ANALOG_PLL_SYS_ENABLE __BIT(13)
364 1.1 skrll #define CCM_ANALOG_PLL_SYS_POWERDOWN __BIT(12)
365 1.1 skrll #define CCM_ANALOG_PLL_SYS_DIV_SELECT __BIT(0)
366 1.1 skrll #define CCM_ANALOG_PLL_SYS_SS 0x00000040
367 1.1 skrll #define CCM_ANALOG_PLL_SYS_NUM 0x00000050
368 1.1 skrll #define CCM_ANALOG_PLL_SYS_DENOM 0x00000060
369 1.1 skrll #define CCM_ANALOG_PLL_AUDIO 0x00000070
370 1.1 skrll #define CCM_ANALOG_PLL_AUDIO_SET 0x00000074
371 1.1 skrll #define CCM_ANALOG_PLL_AUDIO_CLR 0x00000078
372 1.1 skrll #define CCM_ANALOG_PLL_AUDIO_TOG 0x0000007c
373 1.1 skrll #define CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT __BITS(20, 19)
374 1.1 skrll #define CCM_ANALOG_PLL_AUDIO_BYPASS __BIT(16)
375 1.1 skrll #define CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC __BITS(15, 14)
376 1.1 skrll #define CCM_ANALOG_PLL_AUDIO_ENABLE __BIT(13)
377 1.1 skrll #define CCM_ANALOG_PLL_AUDIO_POWERDOWN __BIT(12)
378 1.1 skrll #define CCM_ANALOG_PLL_AUDIO_DIV_SELECT __BITS(6, 0)
379 1.1 skrll #define CCM_ANALOG_PLL_AUDIO_NUM 0x00000080
380 1.1 skrll #define CCM_ANALOG_PLL_AUDIO_DENOM 0x00000090
381 1.1 skrll #define CCM_ANALOG_PLL_VIDEO 0x000000a0
382 1.1 skrll #define CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT __BITS(20, 19)
383 1.1 skrll #define CCM_ANALOG_PLL_VIDEO_BYPASS __BIT(16)
384 1.1 skrll #define CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC __BITS(15, 14)
385 1.1 skrll #define CCM_ANALOG_PLL_VIDEO_ENABLE __BIT(13)
386 1.1 skrll #define CCM_ANALOG_PLL_VIDEO_POWERDOWN __BIT(12)
387 1.1 skrll #define CCM_ANALOG_PLL_VIDEO_DIV_SELECT __BITS(6, 0)
388 1.1 skrll #define CCM_ANALOG_PLL_VIDEO_SET 0x000000a4
389 1.1 skrll #define CCM_ANALOG_PLL_VIDEO_CLR 0x000000a8
390 1.1 skrll #define CCM_ANALOG_PLL_VIDEO_TOG 0x000000ac
391 1.1 skrll #define CCM_ANALOG_PLL_VIDEO_NUM 0x000000b0
392 1.1 skrll #define CCM_ANALOG_PLL_VIDEO_DENOM 0x000000c0
393 1.1 skrll #define CCM_ANALOG_PLL_MLB 0x000000d0
394 1.1 skrll #define CCM_ANALOG_PLL_MLB_SET 0x000000d4
395 1.1 skrll #define CCM_ANALOG_PLL_MLB_CLR 0x000000d8
396 1.1 skrll #define CCM_ANALOG_PLL_MLB_TOG 0x000000dc
397 1.1 skrll #define CCM_ANALOG_PLL_ENET 0x000000e0
398 1.1 skrll #define CCM_ANALOG_PLL_ENET_SET 0x000000e4
399 1.1 skrll #define CCM_ANALOG_PLL_ENET_CLR 0x000000e8
400 1.1 skrll #define CCM_ANALOG_PLL_ENET_TOG 0x000000ec
401 1.1 skrll #define CCM_ANALOG_PLL_ENET_LOCK __BIT(31)
402 1.1 skrll #define CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN __BIT(21) /* iMX6UL */
403 1.1 skrll #define CCM_ANALOG_PLL_ENET_ENET2_125M_EN __BIT(20) /* iMX6UL */
404 1.1 skrll #define CCM_ANALOG_PLL_ENET_ENABLE_100M __BIT(20) /* SATA */
405 1.1 skrll #define CCM_ANALOG_PLL_ENET_ENABLE_125M __BIT(19) /* PCIe */
406 1.1 skrll #define CCM_ANALOG_PLL_ENET_PFD_OFFSET_EN __BIT(18)
407 1.1 skrll #define CCM_ANALOG_PLL_ENET_BYPASS __BIT(16)
408 1.1 skrll #define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC __BITS(15, 14)
409 1.1 skrll #define CCM_ANALOG_PLL_ENET_ENET1_125M_EN __BIT(13) /* iMX6UL */
410 1.1 skrll #define CCM_ANALOG_PLL_ENET_ENABLE __BIT(13) /* Ether */
411 1.1 skrll #define CCM_ANALOG_PLL_ENET_POWERDOWN __BIT(12)
412 1.1 skrll #define CCM_ANALOG_PLL_ENET_DIV_SELECT __BITS(1, 0)
413 1.1 skrll #define CCM_ANALOG_PFD_480 0x000000f0
414 1.1 skrll #define CCM_ANALOG_PFD_480_SET 0x000000f4
415 1.1 skrll #define CCM_ANALOG_PFD_480_CLR 0x000000f8
416 1.1 skrll #define CCM_ANALOG_PFD_480_TOG 0x000000fc
417 1.1 skrll #define CCM_ANALOG_PFD_480_PFD3_CLKGATE __BIT(31)
418 1.1 skrll #define CCM_ANALOG_PFD_480_PFD3_STABLE __BIT(30)
419 1.1 skrll #define CCM_ANALOG_PFD_480_PFD3_FRAC __BITS(29, 24)
420 1.1 skrll #define CCM_ANALOG_PFD_480_PFD2_CLKGATE __BIT(23)
421 1.1 skrll #define CCM_ANALOG_PFD_480_PFD2_STABLE __BIT(22)
422 1.1 skrll #define CCM_ANALOG_PFD_480_PFD2_FRAC __BITS(21, 16)
423 1.1 skrll #define CCM_ANALOG_PFD_480_PFD1_CLKGATE __BIT(15)
424 1.1 skrll #define CCM_ANALOG_PFD_480_PFD1_STABLE __BIT(14)
425 1.1 skrll #define CCM_ANALOG_PFD_480_PFD1_FRAC __BITS(13, 8)
426 1.1 skrll #define CCM_ANALOG_PFD_480_PFD0_CLKGATE __BIT(7)
427 1.1 skrll #define CCM_ANALOG_PFD_480_PFD0_STABLE __BIT(6)
428 1.1 skrll #define CCM_ANALOG_PFD_480_PFD0_FRAC __BITS(5, 0)
429 1.1 skrll #define CCM_ANALOG_PFD_528 0x00000100
430 1.1 skrll #define CCM_ANALOG_PFD_528_SET 0x00000104
431 1.1 skrll #define CCM_ANALOG_PFD_528_CLR 0x00000108
432 1.1 skrll #define CCM_ANALOG_PFD_528_TOG 0x0000010c
433 1.1 skrll #define CCM_ANALOG_PFD_528_PFD2_CLKGATE __BIT(23)
434 1.1 skrll #define CCM_ANALOG_PFD_528_PFD2_STABLE __BIT(22)
435 1.1 skrll #define CCM_ANALOG_PFD_528_PFD2_FRAC __BITS(21, 16)
436 1.1 skrll #define CCM_ANALOG_PFD_528_PFD1_CLKGATE __BIT(15)
437 1.1 skrll #define CCM_ANALOG_PFD_528_PFD1_STABLE __BIT(14)
438 1.1 skrll #define CCM_ANALOG_PFD_528_PFD1_FRAC __BITS(13, 8)
439 1.1 skrll #define CCM_ANALOG_PFD_528_PFD0_CLKGATE __BIT(7)
440 1.1 skrll #define CCM_ANALOG_PFD_528_PFD0_STABLE __BIT(6)
441 1.1 skrll #define CCM_ANALOG_PFD_528_PFD0_FRAC __BITS(5, 0)
442 1.1 skrll #define CCM_ANALOG_MISC0 0x00000150
443 1.1 skrll #define CCM_ANALOG_MISC0_SET 0x00000154
444 1.1 skrll #define CCM_ANALOG_MISC0_CLR 0x00000158
445 1.1 skrll #define CCM_ANALOG_MISC0_TOG 0x0000015c
446 1.1 skrll #define CCM_ANALOG_MISC1 0x00000160
447 1.1 skrll #define CCM_ANALOG_MISC1_SET 0x00000164
448 1.1 skrll #define CCM_ANALOG_MISC1_CLR 0x00000168
449 1.1 skrll #define CCM_ANALOG_MISC1_TOG 0x0000016c
450 1.1 skrll #define CCM_ANALOG_MISC1_LVDS_CLK1_SRC __BITS(4, 0)
451 1.1 skrll #define CCM_ANALOG_MISC1_LVDS_CLK1_SRC_PCIE __SHIFTIN(0xa, CCM_ANALOG_MISC1_LVDS_CLK1_SRC)
452 1.1 skrll #define CCM_ANALOG_MISC1_LVDS_CLK1_SRC_SATA __SHIFTIN(0xb, CCM_ANALOG_MISC1_LVDS_CLK1_SRC)
453 1.1 skrll #define CCM_ANALOG_MISC1_LVDS_CLK2_SRC __BITS(9, 5)
454 1.1 skrll #define CCM_ANALOG_MISC1_LVDS_CLK1_OBEN __BIT(10)
455 1.1 skrll #define CCM_ANALOG_MISC1_LVDS_CLK2_OBEN __BIT(11)
456 1.1 skrll #define CCM_ANALOG_MISC1_LVDS_CLK1_IBEN __BIT(12)
457 1.1 skrll #define CCM_ANALOG_MISC1_LVDS_CLK2_IBEN __BIT(13)
458 1.1 skrll #define CCM_ANALOG_MISC2 0x00000170
459 1.1 skrll #define CCM_ANALOG_MISC2_SET 0x00000174
460 1.1 skrll #define CCM_ANALOG_MISC2_CLR 0x00000178
461 1.1 skrll #define CCM_ANALOG_MISC2_TOG 0x0000017C
462 1.1 skrll #define CCM_ANALOG_MISC2_VIDEO_DIV __BITS(31, 30)
463 1.1 skrll #define CCM_ANALOG_MISC2_REG2_STEP_TIME __BITS(29, 28)
464 1.1 skrll #define CCM_ANALOG_MISC2_REG1_STEP_TIME __BITS(27, 26)
465 1.1 skrll #define CCM_ANALOG_MISC2_REG0_STEP_TIME __BITS(25, 24)
466 1.1 skrll #define CCM_ANALOG_MISC2_AUDIO_DIV_MSB __BIT(23)
467 1.1 skrll #define CCM_ANALOG_MISC2_REG2_OK __BIT(22)
468 1.1 skrll #define CCM_ANALOG_MISC2_REG2_ENABLE_BO __BIT(21)
469 1.1 skrll #define CCM_ANALOG_MISC2_REG2_BO_STATUS __BIT(19)
470 1.1 skrll #define CCM_ANALOG_MISC2_REG2_BO_OFFSET __BITS(18, 16)
471 1.1 skrll #define CCM_ANALOG_MISC2_AUDIO_DIV_LSB __BIT(15)
472 1.1 skrll #define CCM_ANALOG_MISC2_REG1_ENABLE_BO __BIT(13)
473 1.1 skrll #define CCM_ANALOG_MISC2_REG1_BO_STATUS __BIT(11)
474 1.1 skrll #define CCM_ANALOG_MISC2_REG1_BO_OFFSET __BITS(10, 8)
475 1.1 skrll #define CCM_ANALOG_MISC2_PLL3_DISABLE __BIT(7)
476 1.1 skrll #define CCM_ANALOG_MISC2_REG0_ENABLE_BO __BIT(5)
477 1.1 skrll #define CCM_ANALOG_MISC2_REG0_BO_STATUS __BIT(3)
478 1.1 skrll #define CCM_ANALOG_MISC2_REG0_BO_OFFSET __BITS(2, 0)
479 1.1 skrll
480 1.1 skrll #define CCM_TEMPMON_TEMPSENSE0 0x00000180
481 1.1 skrll #define CCM_TEMPMON_TEMPSENSE0_ALARM_VALUE __BIT(31, 30)
482 1.1 skrll #define CCM_TEMPMON_TEMPSENSE0_TEMP_CNT __BITS(19, 8)
483 1.1 skrll #define CCM_TEMPMON_TEMPSENSE0_FINISHED __BIT(2)
484 1.1 skrll #define CCM_TEMPMON_TEMPSENSE0_MEASURE_TEMP __BIT(1)
485 1.1 skrll #define CCM_TEMPMON_TEMPSENSE0_POWER_DOWN __BIT(0)
486 1.1 skrll #define CCM_TEMPMON_TEMPSENSE1 0x00000180
487 1.1 skrll #define CCM_TEMPMON_TEMPSENSE1_MEASURE_FREQ __BITS(15, 0)
488 1.1 skrll
489 1.1 skrll #define USB_ANALOG_USB1_VBUS_DETECT 0x000001a0
490 1.1 skrll #define USB_ANALOG_USB1_CHRG_DETECT 0x000001b0
491 1.1 skrll #define USB_ANALOG_USB_CHRG_DETECT_EN_B __BIT(20)
492 1.1 skrll #define USB_ANALOG_USB_CHRG_DETECT_CHK_CHRG_B __BIT(19)
493 1.1 skrll #define USB_ANALOG_USB_CHRG_DETECT_CHK_CHK_CONTACT __BIT(18)
494 1.1 skrll #define USB_ANALOG_USB1_VBUS_DETECT_STAT 0x000001c0
495 1.1 skrll #define USB_ANALOG_USB1_CHRG_DETECT_STAT 0x000001d0
496 1.1 skrll #define USB_ANALOG_USB1_MISC 0x000001f0
497 1.1 skrll #define USB_ANALOG_USB2_VBUS_DETECT 0x00000200
498 1.1 skrll #define USB_ANALOG_USB2_CHRG_DETECT 0x00000210
499 1.1 skrll #define USB_ANALOG_USB2_VBUS_DETECT_STAT 0x00000220
500 1.1 skrll #define USB_ANALOG_USB2_CHRG_DETECT_STAT 0x00000230
501 1.1 skrll #define USB_ANALOG_USB2_MISC 0x00000250
502 1.1 skrll
503 1.1 skrll #define USB_ANALOG_DIGPROG 0x00000260
504 1.1 skrll #define USB_ANALOG_DIGPROG_SOLOLITE 0x00000280
505 1.1 skrll #define USB_ANALOG_DIGPROG_MAJOR __BITS(23, 8)
506 1.1 skrll #define USB_ANALOG_DIGPROG_MINOR __BITS(7, 0)
507 1.1 skrll
508 1.1 skrll #endif /* _ARM_NXP_IMX6_CCMREG_H */
509