imx6_ccmvar.h revision 1.1
1 /* $NetBSD: imx6_ccmvar.h,v 1.1 2020/12/23 14:42:38 skrll Exp $ */ 2 /* 3 * Copyright (c) 2012,2019 Genetec Corporation. All rights reserved. 4 * Written by Hashimoto Kenichi for Genetec Corporation. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 17 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 18 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORPORATION 19 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #ifndef _ARM_NXP_IMX6_CCMVAR_H_ 29 #define _ARM_NXP_IMX6_CCMVAR_H_ 30 31 #include <dev/clk/clk.h> 32 #include <dev/clk/clk_backend.h> 33 34 struct imx6ccm_softc { 35 device_t sc_dev; 36 bus_space_tag_t sc_iot; 37 bus_space_handle_t sc_ioh; 38 bus_space_handle_t sc_ioh_analog; 39 40 struct clk_domain sc_clkdom; 41 }; 42 43 void imx6ccm_attach_common(device_t); 44 45 struct clk *imx6_get_clock(const char *); 46 struct clk *imx6_get_clock_by_id(u_int); 47 48 /* Clock IDs */ 49 #define IMX6CLK_DUMMY 0 50 #define IMX6CLK_CKIL 1 51 #define IMX6CLK_CKIH 2 52 #define IMX6CLK_OSC 3 53 #define IMX6CLK_PLL2_PFD0_352M 4 54 #define IMX6CLK_PLL2_PFD1_594M 5 55 #define IMX6CLK_PLL2_PFD2_396M 6 56 #define IMX6CLK_PLL3_PFD0_720M 7 57 #define IMX6CLK_PLL3_PFD1_540M 8 58 #define IMX6CLK_PLL3_PFD2_508M 9 59 #define IMX6CLK_PLL3_PFD3_454M 10 60 #define IMX6CLK_PLL2_198M 11 61 #define IMX6CLK_PLL3_120M 12 62 #define IMX6CLK_PLL3_80M 13 63 #define IMX6CLK_PLL3_60M 14 64 #define IMX6CLK_TWD 15 65 #define IMX6CLK_STEP 16 66 #define IMX6CLK_PLL1_SW 17 67 #define IMX6CLK_PERIPH_PRE 18 68 #define IMX6CLK_PERIPH2_PRE 19 69 #define IMX6CLK_PERIPH_CLK2_SEL 20 70 #define IMX6CLK_PERIPH2_CLK2_SEL 21 71 #define IMX6CLK_AXI_SEL 22 72 #define IMX6CLK_ESAI_SEL 23 73 #define IMX6CLK_ASRC_SEL 24 74 #define IMX6CLK_SPDIF_SEL 25 75 #define IMX6CLK_GPU2D_AXI 26 76 #define IMX6CLK_GPU3D_AXI 27 77 #define IMX6CLK_GPU2D_CORE_SEL 28 78 #define IMX6CLK_GPU3D_CORE_SEL 29 79 #define IMX6CLK_GPU3D_SHADER_SEL 30 80 #define IMX6CLK_IPU1_SEL 31 81 #define IMX6CLK_IPU2_SEL 32 82 #define IMX6CLK_LDB_DI0_SEL 33 83 #define IMX6CLK_LDB_DI1_SEL 34 84 #define IMX6CLK_IPU1_DI0_PRE_SEL 35 85 #define IMX6CLK_IPU1_DI1_PRE_SEL 36 86 #define IMX6CLK_IPU2_DI0_PRE_SEL 37 87 #define IMX6CLK_IPU2_DI1_PRE_SEL 38 88 #define IMX6CLK_IPU1_DI0_SEL 39 89 #define IMX6CLK_IPU1_DI1_SEL 40 90 #define IMX6CLK_IPU2_DI0_SEL 41 91 #define IMX6CLK_IPU2_DI1_SEL 42 92 #define IMX6CLK_HSI_TX_SEL 43 93 #define IMX6CLK_PCIE_AXI_SEL 44 94 #define IMX6CLK_SSI1_SEL 45 95 #define IMX6CLK_SSI2_SEL 46 96 #define IMX6CLK_SSI3_SEL 47 97 #define IMX6CLK_USDHC1_SEL 48 98 #define IMX6CLK_USDHC2_SEL 49 99 #define IMX6CLK_USDHC3_SEL 50 100 #define IMX6CLK_USDHC4_SEL 51 101 #define IMX6CLK_ENFC_SEL 52 102 #define IMX6CLK_EIM_SEL 53 103 #define IMX6CLK_EIM_SLOW_SEL 54 104 #define IMX6CLK_VDO_AXI_SEL 55 105 #define IMX6CLK_VPU_AXI_SEL 56 106 #define IMX6CLK_CKO1_SEL 57 107 #define IMX6CLK_PERIPH 58 108 #define IMX6CLK_PERIPH2 59 109 #define IMX6CLK_PERIPH_CLK2 60 110 #define IMX6CLK_PERIPH2_CLK2 61 111 #define IMX6CLK_IPG 62 112 #define IMX6CLK_IPG_PER 63 113 #define IMX6CLK_ESAI_PRED 64 114 #define IMX6CLK_ESAI_PODF 65 115 #define IMX6CLK_ASRC_PRED 66 116 #define IMX6CLK_ASRC_PODF 67 117 #define IMX6CLK_SPDIF_PRED 68 118 #define IMX6CLK_SPDIF_PODF 69 119 #define IMX6CLK_CAN_ROOT 70 120 #define IMX6CLK_ECSPI_ROOT 71 121 #define IMX6CLK_GPU2D_CORE_PODF 72 122 #define IMX6CLK_GPU3D_CORE_PODF 73 123 #define IMX6CLK_GPU3D_SHADER 74 124 #define IMX6CLK_IPU1_PODF 75 125 #define IMX6CLK_IPU2_PODF 76 126 #define IMX6CLK_LDB_DI0_PODF 77 127 #define IMX6CLK_LDB_DI1_PODF 78 128 #define IMX6CLK_IPU1_DI0_PRE 79 129 #define IMX6CLK_IPU1_DI1_PRE 80 130 #define IMX6CLK_IPU2_DI0_PRE 81 131 #define IMX6CLK_IPU2_DI1_PRE 82 132 #define IMX6CLK_HSI_TX_PODF 83 133 #define IMX6CLK_SSI1_PRED 84 134 #define IMX6CLK_SSI1_PODF 85 135 #define IMX6CLK_SSI2_PRED 86 136 #define IMX6CLK_SSI2_PODF 87 137 #define IMX6CLK_SSI3_PRED 88 138 #define IMX6CLK_SSI3_PODF 89 139 #define IMX6CLK_UART_SERIAL_PODF 90 140 #define IMX6CLK_USDHC1_PODF 91 141 #define IMX6CLK_USDHC2_PODF 92 142 #define IMX6CLK_USDHC3_PODF 93 143 #define IMX6CLK_USDHC4_PODF 94 144 #define IMX6CLK_ENFC_PRED 95 145 #define IMX6CLK_ENFC_PODF 96 146 #define IMX6CLK_EIM_PODF 97 147 #define IMX6CLK_EIM_SLOW_PODF 98 148 #define IMX6CLK_VPU_AXI_PODF 99 149 #define IMX6CLK_CKO1_PODF 100 150 #define IMX6CLK_AXI 101 151 #define IMX6CLK_MMDC_CH0_AXI_PODF 102 152 #define IMX6CLK_MMDC_CH1_AXI_PODF 103 153 #define IMX6CLK_ARM 104 154 #define IMX6CLK_AHB 105 155 #define IMX6CLK_APBH_DMA 106 156 #define IMX6CLK_ASRC 107 157 #define IMX6CLK_CAN1_IPG 108 158 #define IMX6CLK_CAN1_SERIAL 109 159 #define IMX6CLK_CAN2_IPG 110 160 #define IMX6CLK_CAN2_SERIAL 111 161 #define IMX6CLK_ECSPI1 112 162 #define IMX6CLK_ECSPI2 113 163 #define IMX6CLK_ECSPI3 114 164 #define IMX6CLK_ECSPI4 115 165 #define IMX6CLK_ECSPI5 116 /* i.MX6Q */ 166 #define IMX6CLK_I2C4 116 /* i.MX6DL */ 167 #define IMX6CLK_ENET 117 168 #define IMX6CLK_ESAI_EXTAL 118 169 #define IMX6CLK_GPT_IPG 119 170 #define IMX6CLK_GPT_IPG_PER 120 171 #define IMX6CLK_GPU2D_CORE 121 172 #define IMX6CLK_GPU3D_CORE 122 173 #define IMX6CLK_HDMI_IAHB 123 174 #define IMX6CLK_HDMI_ISFR 124 175 #define IMX6CLK_I2C1 125 176 #define IMX6CLK_I2C2 126 177 #define IMX6CLK_I2C3 127 178 #define IMX6CLK_IIM 128 179 #define IMX6CLK_ENFC 129 180 #define IMX6CLK_IPU1 130 181 #define IMX6CLK_IPU1_DI0 131 182 #define IMX6CLK_IPU1_DI1 132 183 #define IMX6CLK_IPU2 133 184 #define IMX6CLK_IPU2_DI0 134 185 #define IMX6CLK_LDB_DI0 135 186 #define IMX6CLK_LDB_DI1 136 187 #define IMX6CLK_IPU2_DI1 137 188 #define IMX6CLK_HSI_TX 138 189 #define IMX6CLK_MLB 139 190 #define IMX6CLK_MMDC_CH0_AXI 140 191 #define IMX6CLK_MMDC_CH1_AXI 141 192 #define IMX6CLK_OCRAM 142 193 #define IMX6CLK_OPENVG_AXI 143 194 #define IMX6CLK_PCIE_AXI 144 195 #define IMX6CLK_PWM1 145 196 #define IMX6CLK_PWM2 146 197 #define IMX6CLK_PWM3 147 198 #define IMX6CLK_PWM4 148 199 #define IMX6CLK_PER1_BCH 149 200 #define IMX6CLK_GPMI_BCH_APB 150 201 #define IMX6CLK_GPMI_BCH 151 202 #define IMX6CLK_GPMI_IO 152 203 #define IMX6CLK_GPMI_APB 153 204 #define IMX6CLK_SATA 154 205 #define IMX6CLK_SDMA 155 206 #define IMX6CLK_SPBA 156 207 #define IMX6CLK_SSI1 157 208 #define IMX6CLK_SSI2 158 209 #define IMX6CLK_SSI3 159 210 #define IMX6CLK_UART_IPG 160 211 #define IMX6CLK_UART_SERIAL 161 212 #define IMX6CLK_USBOH3 162 213 #define IMX6CLK_USDHC1 163 214 #define IMX6CLK_USDHC2 164 215 #define IMX6CLK_USDHC3 165 216 #define IMX6CLK_USDHC4 166 217 #define IMX6CLK_VDO_AXI 167 218 #define IMX6CLK_VPU_AXI 168 219 #define IMX6CLK_CKO1 169 220 #define IMX6CLK_PLL1_SYS 170 221 #define IMX6CLK_PLL2_BUS 171 222 #define IMX6CLK_PLL3_USB_OTG 172 223 #define IMX6CLK_PLL4_AUDIO 173 224 #define IMX6CLK_PLL5_VIDEO 174 225 #define IMX6CLK_PLL8_MLB 175 226 #define IMX6CLK_PLL7_USB_HOST 176 227 #define IMX6CLK_PLL6_ENET 177 228 #define IMX6CLK_SSI1_IPG 178 229 #define IMX6CLK_SSI2_IPG 179 230 #define IMX6CLK_SSI3_IPG 180 231 #define IMX6CLK_ROM 181 232 #define IMX6CLK_USBPHY1 182 233 #define IMX6CLK_USBPHY2 183 234 #define IMX6CLK_LDB_DI0_DIV_3_5 184 235 #define IMX6CLK_LDB_DI1_DIV_3_5 185 236 #define IMX6CLK_SATA_REF 186 237 #define IMX6CLK_SATA_REF_100M 187 238 #define IMX6CLK_PCIE_REF 188 239 #define IMX6CLK_PCIE_REF_125M 189 240 #define IMX6CLK_ENET_REF 190 241 #define IMX6CLK_USBPHY1_GATE 191 242 #define IMX6CLK_USBPHY2_GATE 192 243 #define IMX6CLK_PLL4_POST_DIV 193 244 #define IMX6CLK_PLL5_POST_DIV 194 245 #define IMX6CLK_PLL5_VIDEO_DIV 195 246 #define IMX6CLK_EIM_SLOW 196 247 #define IMX6CLK_SPDIF 197 248 #define IMX6CLK_CKO2_SEL 198 249 #define IMX6CLK_CKO2_PODF 199 250 #define IMX6CLK_CKO2 200 251 #define IMX6CLK_CKO 201 252 #define IMX6CLK_VDOA 202 253 #define IMX6CLK_PLL4_AUDIO_DIV 203 254 #define IMX6CLK_LVDS1_SEL 204 255 #define IMX6CLK_LVDS2_SEL 205 256 #define IMX6CLK_LVDS1_GATE 206 257 #define IMX6CLK_LVDS2_GATE 207 258 #define IMX6CLK_ESAI_IPG 208 259 #define IMX6CLK_ESAI_MEM 209 260 #define IMX6CLK_ASRC_IPG 210 261 #define IMX6CLK_ASRC_MEM 211 262 #define IMX6CLK_LVDS1_IN 212 263 #define IMX6CLK_LVDS2_IN 213 264 #define IMX6CLK_ANACLK1 214 265 #define IMX6CLK_ANACLK2 215 266 #define IMX6CLK_PLL1_BYPASS_SRC 216 267 #define IMX6CLK_PLL2_BYPASS_SRC 217 268 #define IMX6CLK_PLL3_BYPASS_SRC 218 269 #define IMX6CLK_PLL4_BYPASS_SRC 219 270 #define IMX6CLK_PLL5_BYPASS_SRC 220 271 #define IMX6CLK_PLL6_BYPASS_SRC 221 272 #define IMX6CLK_PLL7_BYPASS_SRC 222 273 #define IMX6CLK_PLL1 223 274 #define IMX6CLK_PLL2 224 275 #define IMX6CLK_PLL3 225 276 #define IMX6CLK_PLL4 226 277 #define IMX6CLK_PLL5 227 278 #define IMX6CLK_PLL6 228 279 #define IMX6CLK_PLL7 229 280 #define IMX6CLK_PLL1_BYPASS 230 281 #define IMX6CLK_PLL2_BYPASS 231 282 #define IMX6CLK_PLL3_BYPASS 232 283 #define IMX6CLK_PLL4_BYPASS 233 284 #define IMX6CLK_PLL5_BYPASS 234 285 #define IMX6CLK_PLL6_BYPASS 235 286 #define IMX6CLK_PLL7_BYPASS 236 287 #define IMX6CLK_GPT_3M 237 288 #define IMX6CLK_VIDEO_27M 238 289 #define IMX6CLK_MIPI_CORE_CFG 239 290 #define IMX6CLK_MIPI_IPG 240 291 #define IMX6CLK_CAAM_MEM 241 292 #define IMX6CLK_CAAM_ACLK 242 293 #define IMX6CLK_CAAM_IPG 243 294 #define IMX6CLK_SPDIF_GCLK 244 295 #define IMX6CLK_UART_SEL 245 296 #define IMX6CLK_IPG_PER_SEL 246 297 #define IMX6CLK_ECSPI_SEL 247 298 #define IMX6CLK_CAN_SEL 248 299 #define IMX6CLK_MMDC_CH1_AXI_CG 249 300 #define IMX6CLK_PRE0 250 301 #define IMX6CLK_PRE1 251 302 #define IMX6CLK_PRE2 252 303 #define IMX6CLK_PRE3 253 304 #define IMX6CLK_PRG0_AXI 254 305 #define IMX6CLK_PRG1_AXI 255 306 #define IMX6CLK_PRG0_APB 256 307 #define IMX6CLK_PRG1_APB 257 308 #define IMX6CLK_PRE_AXI 258 309 #define IMX6CLK_MLB_SEL 259 310 #define IMX6CLK_MLB_PODF 260 311 #define IMX6CLK_END 261 312 313 enum imx6_clk_type { 314 IMX6_CLK_FIXED, 315 IMX6_CLK_FIXED_FACTOR, 316 IMX6_CLK_PLL, 317 IMX6_CLK_MUX, 318 IMX6_CLK_GATE, 319 IMX6_CLK_PFD, 320 IMX6_CLK_DIV, 321 }; 322 323 enum imx6_clk_reg { 324 IMX6_CLK_REG_CCM, 325 IMX6_CLK_REG_CCM_ANALOG, 326 }; 327 328 enum imx6_clk_pll_type { 329 IMX6_CLK_PLL_GENERIC, 330 IMX6_CLK_PLL_SYS, 331 IMX6_CLK_PLL_USB, 332 IMX6_CLK_PLL_AUDIO_VIDEO, 333 IMX6_CLK_PLL_ENET, 334 }; 335 336 enum imx6_clk_div_type { 337 IMX6_CLK_DIV_NORMAL, 338 IMX6_CLK_DIV_BUSY, 339 IMX6_CLK_DIV_TABLE, 340 }; 341 342 enum imx6_clk_mux_type { 343 IMX6_CLK_MUX_NORMAL, 344 IMX6_CLK_MUX_BUSY, 345 }; 346 347 struct imx6_clk_fixed { 348 u_int rate; 349 }; 350 351 struct imx6_clk_fixed_factor { 352 u_int div; 353 u_int mult; 354 }; 355 356 struct imx6_clk_pfd { 357 uint32_t reg; 358 int index; 359 }; 360 361 struct imx6_clk_pll { 362 enum imx6_clk_pll_type type; 363 uint32_t reg; 364 uint32_t mask; 365 uint32_t powerdown; 366 unsigned long ref; 367 }; 368 369 struct imx6_clk_div { 370 enum imx6_clk_div_type type; 371 enum imx6_clk_reg base; 372 uint32_t reg; 373 uint32_t mask; 374 uint32_t busy_reg; 375 uint32_t busy_mask; 376 const int *tbl; 377 }; 378 379 struct imx6_clk_mux { 380 enum imx6_clk_mux_type type; 381 enum imx6_clk_reg base; 382 uint32_t reg; 383 uint32_t mask; 384 const char **parents; 385 u_int nparents; 386 uint32_t busy_reg; 387 uint32_t busy_mask; 388 }; 389 390 struct imx6_clk_gate { 391 enum imx6_clk_reg base; 392 uint32_t reg; 393 uint32_t mask; 394 uint32_t exclusive_mask; 395 }; 396 397 struct imx6_clk { 398 struct clk base; /* must be first */ 399 400 const char *parent; 401 u_int refcnt; 402 403 enum imx6_clk_type type; 404 union { 405 struct imx6_clk_fixed fixed; 406 struct imx6_clk_fixed_factor fixed_factor; 407 struct imx6_clk_pfd pfd; 408 struct imx6_clk_pll pll; 409 struct imx6_clk_div div; 410 struct imx6_clk_mux mux; 411 struct imx6_clk_gate gate; 412 } clk; 413 }; 414 415 #define CLK_FIXED(_name, _rate) { \ 416 .base = { .name = (_name) }, \ 417 .type = IMX6_CLK_FIXED, \ 418 .clk = { \ 419 .fixed = { \ 420 .rate = (_rate), \ 421 } \ 422 } \ 423 } 424 425 #define CLK_FIXED_FACTOR(_name, _parent, _div, _mult) { \ 426 .base = { .name = (_name) }, \ 427 .type = IMX6_CLK_FIXED_FACTOR, \ 428 .parent = (_parent), \ 429 .clk = { \ 430 .fixed_factor = { \ 431 .div = (_div), \ 432 .mult = (_mult), \ 433 } \ 434 } \ 435 } 436 437 #define CLK_PFD(_name, _parent, _reg, _index) { \ 438 .base = { .name = (_name) }, \ 439 .type = IMX6_CLK_PFD, \ 440 .parent = (_parent), \ 441 .clk = { \ 442 .pfd = { \ 443 .reg = (CCM_ANALOG_##_reg), \ 444 .index = (_index), \ 445 } \ 446 } \ 447 } 448 449 #define CLK_PLL(_name, _parent, _type, _reg, _mask, _powerdown, _ref) { \ 450 .base = { .name = (_name) }, \ 451 .type = IMX6_CLK_PLL, \ 452 .parent = (_parent), \ 453 .clk = { \ 454 .pll = { \ 455 .type = (IMX6_CLK_PLL_##_type), \ 456 .reg = (CCM_ANALOG_##_reg), \ 457 .mask = (CCM_ANALOG_##_reg##_##_mask), \ 458 .powerdown = (CCM_ANALOG_##_reg##_##_powerdown), \ 459 .ref = (_ref), \ 460 } \ 461 } \ 462 } 463 464 #define CLK_DIV(_name, _parent, _reg, _mask) { \ 465 .base = { .name = (_name) }, \ 466 .type = IMX6_CLK_DIV, \ 467 .parent = (_parent), \ 468 .clk = { \ 469 .div = { \ 470 .type = (IMX6_CLK_DIV_NORMAL), \ 471 .base = (IMX6_CLK_REG_CCM), \ 472 .reg = (CCM_##_reg), \ 473 .mask = (CCM_##_reg##_##_mask), \ 474 } \ 475 } \ 476 } 477 478 #define CLK_DIV_BUSY(_name, _parent, _reg, _mask, _busy_reg, _busy_mask) { \ 479 .base = { .name = (_name) }, \ 480 .type = IMX6_CLK_DIV, \ 481 .parent = (_parent), \ 482 .clk = { \ 483 .div = { \ 484 .type = (IMX6_CLK_DIV_BUSY), \ 485 .base = (IMX6_CLK_REG_CCM), \ 486 .reg = (CCM_##_reg), \ 487 .mask = (CCM_##_reg##_##_mask), \ 488 .busy_reg = (CCM_##_busy_reg), \ 489 .busy_mask = (CCM_##_busy_reg##_##_busy_mask) \ 490 } \ 491 } \ 492 } 493 494 #define CLK_DIV_TABLE(_name, _parent, _reg, _mask, _tbl) { \ 495 .base = { .name = (_name) }, \ 496 .type = IMX6_CLK_DIV, \ 497 .parent = (_parent), \ 498 .clk = { \ 499 .div = { \ 500 .type = (IMX6_CLK_DIV_TABLE), \ 501 .base = (IMX6_CLK_REG_CCM_ANALOG), \ 502 .reg = (CCM_ANALOG_##_reg), \ 503 .mask = (CCM_ANALOG_##_reg##_##_mask), \ 504 .tbl = (_tbl) \ 505 } \ 506 } \ 507 } 508 509 #define CLK_MUX(_name, _parents, _base, _reg, _mask) { \ 510 .base = { .name = (_name), .flags = CLK_SET_RATE_PARENT }, \ 511 .type = IMX6_CLK_MUX, \ 512 .clk = { \ 513 .mux = { \ 514 .type = (IMX6_CLK_MUX_NORMAL), \ 515 .base = (IMX6_CLK_REG_##_base), \ 516 .reg = (_base##_##_reg), \ 517 .mask = (_base##_##_reg##_##_mask), \ 518 .parents = (_parents), \ 519 .nparents = __arraycount(_parents) \ 520 } \ 521 } \ 522 } 523 524 #define CLK_MUX_BUSY(_name, _parents, _reg, _mask, _busy_reg, _busy_mask) { \ 525 .base = { .name = (_name), .flags = CLK_SET_RATE_PARENT }, \ 526 .type = IMX6_CLK_MUX, \ 527 .clk = { \ 528 .mux = { \ 529 .type = (IMX6_CLK_MUX_BUSY), \ 530 .base = (IMX6_CLK_REG_CCM), \ 531 .reg = (CCM_##_reg), \ 532 .mask = (CCM_##_reg##_##_mask), \ 533 .parents = (_parents), \ 534 .nparents = __arraycount(_parents), \ 535 .busy_reg = (CCM_##_busy_reg), \ 536 .busy_mask = (CCM_##_busy_reg##_##_busy_mask) \ 537 } \ 538 } \ 539 } 540 541 #define CLK_GATE(_name, _parent, _base, _reg, _mask) { \ 542 .base = { .name = (_name), .flags = CLK_SET_RATE_PARENT }, \ 543 .type = IMX6_CLK_GATE, \ 544 .parent = (_parent), \ 545 .clk = { \ 546 .gate = { \ 547 .base = (IMX6_CLK_REG_##_base), \ 548 .reg = (_base##_##_reg), \ 549 .mask = (_base##_##_reg##_##_mask), \ 550 .exclusive_mask = 0 \ 551 } \ 552 } \ 553 } 554 555 #define CLK_GATE_EXCLUSIVE(_name, _parent, _base, _reg, _mask, _exclusive_mask) { \ 556 .base = { .name = (_name), .flags = CLK_SET_RATE_PARENT }, \ 557 .type = IMX6_CLK_GATE, \ 558 .parent = (_parent), \ 559 .clk = { \ 560 .gate = { \ 561 .base = (IMX6_CLK_REG_##_base), \ 562 .reg = (_base##_##_reg), \ 563 .mask = (_base##_##_reg##_##_mask), \ 564 .exclusive_mask = (_base##_##_reg##_##_exclusive_mask) \ 565 } \ 566 } \ 567 } 568 569 #endif /* _ARM_NXP_IMX6_CCMVAR_H_ */ 570
Indexes created Sat Oct 04 05:10:05 GMT 2025