imx6_iomuxreg.h revision 1.1
1 /* $NetBSD: imx6_iomuxreg.h,v 1.1 2020/12/23 14:42:38 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 2014 Ryo Shimizu <ryo (at) nerv.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 18 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 19 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 20 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 22 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 24 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 25 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #ifndef _ARM_NXP_IMX6_IOMUXREG_H_ 30 #define _ARM_NXP_IMX6_IOMUXREG_H_ 31 32 #define IOMUX_GPR0 0x00000000 33 #define IOMUX_GPR1 0x00000004 34 #define IOMUX_GPR1_CFG_L1_CLK_REMOVAL_EN __BIT(31) 35 #define IOMUX_GPR1_APP_CLK_REQ_N __BIT(30) 36 #define IOMUX_GPR1_PCIE_SW_RST __BIT(29) 37 #define IOMUX_GPR1_APP_REQ_EXIT_L1 __BIT(28) 38 #define IOMUX_GPR1_APP_READY_ENTR_L23 __BIT(27) 39 #define IOMUX_GPR1_APP_REQ_ENTR_L1 __BIT(26) 40 #define IOMUX_GPR1_MIPI_COLOR_SW __BIT(25) 41 #define IOMUX_GPR1_MIPI_DPI_OFF __BIT(24) 42 #define IOMUX_GPR1_EXC_MON __BIT(22) 43 #define IOMUX_GPR1_ENET_CLK_SEL __BIT(21) 44 #define IOMUX_GPR1_MIPI_IPU2_MUX __BIT(20) 45 #define IOMUX_GPR1_MIPI_IPU1_MUX __BIT(19) 46 #define IOMUX_GPR1_TEST_POWERDOWN __BIT(18) 47 #define IOMUX_GPR1_IPU_VPU_MUX __BIT(17) 48 #define IOMUX_GPR1_REF_SSP_EN __BIT(16) 49 #define IOMUX_GPR1_USB_EXP_MODE __BIT(15) 50 #define IOMUX_GPR1_SYS_INT __BIT(14) 51 #define IOMUX_GPR1_USB_OTG_ID_SEL __BIT(13) 52 #define IOMUX_GPR1_GINT __BIT(12) 53 #define IOMUX_GPR1_ADDRS3 __BITS(11, 10) 54 #define IOMUX_GPR1_ACT_CS3 __BIT(9) 55 #define IOMUX_GPR1_ADDRS2 __BITS(8, 7) 56 #define IOMUX_GPR1_ACT_CS2 __BIT(6) 57 #define IOMUX_GPR1_ADDRS1 __BITS(5, 4) 58 #define IOMUX_GPR1_ACT_CS1 __BIT(3) 59 #define IOMUX_GPR1_ADDRS0 __BITS(2, 1) 60 #define IOMUX_GPR1_ACT_CS0 __BIT(0) 61 #define IOMUX_GPR2 0x00000008 62 #define IOMUX_GPR3 0x0000000c 63 #define IOMUX_GPR4 0x00000010 64 #define IOMUX_GPR5 0x00000014 65 #define IOMUX_GPR6 0x00000018 66 #define IOMUX_GPR7 0x0000001c 67 #define IOMUX_GPR8 0x00000020 68 #define IOMUX_GPR8_PCS_TX_SWING_LOW __BITS(31, 25) 69 #define IOMUX_GPR8_PCS_TX_SWING_FULL __BITS(24, 18) 70 #define IOMUX_GPR8_PCS_TX_DEEMPH_GEN2_6DB __BITS(17, 12) 71 #define IOMUX_GPR8_PCS_TX_DEEMPH_GEN2_3P5DB __BITS(11, 6) 72 #define IOMUX_GPR8_PCS_TX_DEEMPH_GEN1 __BITS(5, 0) 73 #define IOMUX_GPR9 0x00000024 74 #define IOMUX_GPR10 0x00000028 75 #define IOMUX_GPR11 0x0000002c 76 #define IOMUX_GPR12 0x00000030 77 #define IOMUX_GPR12_ARMP_IPG_CLK_EN __BIT(27) 78 #define IOMUX_GPR12_ARMP_AHB_CLK_EN __BIT(26) 79 #define IOMUX_GPR12_ARMP_ATB_CLK_EN __BIT(25) 80 #define IOMUX_GPR12_ARMP_APB_CLK_EN __BIT(24) 81 #define IOMUX_GPR12_PCIE_CTL_7 __BITS(23, 21) 82 #define IOMUX_GPR12_DIA_STATUS_BUS_SELECT __BITS(20, 17) 83 #define IOMUX_GPR12_APPS_PM_XMT_TURNOFF __BIT(16) 84 #define IOMUX_GPR12_DEVICE_TYPE __BITS(15, 12) 85 #define IOMUX_GPR12_DEVICE_TYPE_PCIE_EP (0 << 12) 86 #define IOMUX_GPR12_DEVICE_TYPE_PCIE_RC (2 << 12) 87 #define IOMUX_GPR12_APP_INIT_RST __BIT(11) 88 #define IOMUX_GPR12_APP_LTSSM_ENABLE __BIT(10) 89 #define IOMUX_GPR12_APPS_PM_XMT_PME __BIT(9) 90 #define IOMUX_GPR12_LOS_LEVEL __BITS(8, 4) 91 #define IOMUX_GPR12_USDHC_DBG_MUX __BITS(3, 2) 92 #define IOMUX_GPR13 0x00000034 93 #define IOMUX_GPR13_SDMA_STOP_REQ __BIT(30) 94 #define IOMUX_GPR13_CAN2_STOP_REQ __BIT(29) 95 #define IOMUX_GPR13_CAN1_STOP_REQ __BIT(28) 96 #define IOMUX_GPR13_ENET_STOP_REQ __BIT(27) 97 #define IOMUX_GPR13_SATA_PHY_8 __BITS(26, 24) 98 #define IOMUX_GPR13_SATA_PHY_7 __BITS(23, 19) 99 #define IOMUX_GPR13_SATA_PHY_6 __BITS(18, 16) 100 #define IOMUX_GPR13_SATA_SPEED __BIT(15) 101 #define IOMUX_GPR13_SATA_PHY_5 __BIT(14) 102 #define IOMUX_GPR13_SATA_PHY_4 __BITS(13, 11) 103 #define IOMUX_GPR13_SATA_PHY_3 __BITS(10, 7) 104 #define IOMUX_GPR13_SATA_PHY_2 __BITS(6, 2) 105 #define IOMUX_GPR13_SATA_PHY_1 __BIT(1) 106 #define IOMUX_GPR13_SATA_PHY_0 __BIT(0) 107 108 /* for iMX6Dual/Quad */ 109 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA1 0x0000004c 110 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA2 0x00000050 111 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA0 0x00000054 112 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_RGMII_TXC 0x00000058 113 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD0 0x0000005c 114 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD1 0x00000060 115 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD2 0x00000064 116 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD3 0x00000068 117 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_RGMII_RX_CTL 0x0000006c 118 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD0 0x00000070 119 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_RGMII_TX_CTL 0x00000074 120 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD1 0x00000078 121 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD2 0x0000007c 122 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD3 0x00000080 123 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_RGMII_RXC 0x00000084 124 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR25 0x00000088 125 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_EIM_EB2_B 0x0000008c 126 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA16 0x00000090 127 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA17 0x00000094 128 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA18 0x00000098 129 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA19 0x0000009c 130 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA20 0x000000a0 131 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA21 0x000000a4 132 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA22 0x000000a8 133 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA23 0x000000ac 134 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_EIM_EB3_B 0x000000b0 135 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA24 0x000000b4 136 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA25 0x000000b8 137 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA26 0x000000bc 138 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA27 0x000000c0 139 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA28 0x000000c4 140 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA29 0x000000c8 141 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA30 0x000000cc 142 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA31 0x000000d0 143 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR24 0x000000d4 144 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR23 0x000000d8 145 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR22 0x000000dc 146 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR21 0x000000e0 147 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR20 0x000000e4 148 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR19 0x000000e8 149 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR18 0x000000ec 150 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR17 0x000000f0 151 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR16 0x000000f4 152 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_EIM_CS0_B 0x000000f8 153 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_EIM_CS1_B 0x000000fc 154 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_EIM_OE_B 0x00000100 155 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_EIM_RW 0x00000104 156 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_EIM_LBA_B 0x00000108 157 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_EIM_EB0_B 0x0000010c 158 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_EIM_EB1_B 0x00000110 159 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_EIM_AD00 0x00000114 160 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_EIM_AD01 0x00000118 161 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_EIM_AD02 0x0000011c 162 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_EIM_AD03 0x00000120 163 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_EIM_AD04 0x00000124 164 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_EIM_AD05 0x00000128 165 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_EIM_AD06 0x0000012c 166 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_EIM_AD07 0x00000130 167 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_EIM_AD08 0x00000134 168 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_EIM_AD09 0x00000138 169 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_EIM_AD10 0x0000013c 170 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_EIM_AD11 0x00000140 171 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_EIM_AD12 0x00000144 172 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_EIM_AD13 0x00000148 173 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_EIM_AD14 0x0000014c 174 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_EIM_AD15 0x00000150 175 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_EIM_WAIT_B 0x00000154 176 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_EIM_BCLK 0x00000158 177 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_DI0_DISP_CLK 0x0000015c 178 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN15 0x00000160 179 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN02 0x00000164 180 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN03 0x00000168 181 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN04 0x0000016c 182 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA00 0x00000170 183 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA01 0x00000174 184 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA02 0x00000178 185 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA03 0x0000017c 186 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA04 0x00000180 187 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA05 0x00000184 188 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA06 0x00000188 189 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA07 0x0000018c 190 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA08 0x00000190 191 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA09 0x00000194 192 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA10 0x00000198 193 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA11 0x0000019c 194 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA12 0x000001a0 195 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA13 0x000001a4 196 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA14 0x000001a8 197 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA15 0x000001ac 198 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA16 0x000001b0 199 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA17 0x000001b4 200 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA18 0x000001b8 201 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA19 0x000001bc 202 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA20 0x000001c0 203 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA21 0x000001c4 204 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA22 0x000001c8 205 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA23 0x000001cc 206 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_ENET_MDIO 0x000001d0 207 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_ENET_REF_CLK 0x000001d4 208 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_ER 0x000001d8 209 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_ENET_CRS_DV 0x000001dc 210 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA1 0x000001e0 211 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA0 0x000001e4 212 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_EN 0x000001e8 213 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA1 0x000001ec 214 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA0 0x000001f0 215 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_ENET_MDC 0x000001f4 216 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_KEY_COL0 0x000001f8 217 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW0 0x000001fc 218 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_KEY_COL1 0x00000200 219 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW1 0x00000204 220 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_KEY_COL2 0x00000208 221 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW2 0x0000020c 222 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_KEY_COL3 0x00000210 223 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW3 0x00000214 224 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_KEY_COL4 0x00000218 225 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW4 0x0000021c 226 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_GPIO00 0x00000220 227 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_GPIO01 0x00000224 228 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_GPIO09 0x00000228 229 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_GPIO03 0x0000022c 230 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_GPIO06 0x00000230 231 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_GPIO02 0x00000234 232 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_GPIO04 0x00000238 233 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_GPIO05 0x0000023c 234 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_GPIO07 0x00000240 235 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_GPIO08 0x00000244 236 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_GPIO16 0x00000248 237 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_GPIO17 0x0000024c 238 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_GPIO18 0x00000250 239 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_GPIO19 0x00000254 240 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_CSI0_PIXCLK 0x00000258 241 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_CSI0_HSYNC 0x0000025c 242 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA_EN 0x00000260 243 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_CSI0_VSYNC 0x00000264 244 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA04 0x00000268 245 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA05 0x0000026c 246 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA06 0x00000270 247 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA07 0x00000274 248 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA08 0x00000278 249 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA09 0x0000027c 250 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA10 0x00000280 251 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA11 0x00000284 252 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA12 0x00000288 253 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA13 0x0000028c 254 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA14 0x00000290 255 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA15 0x00000294 256 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA16 0x00000298 257 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA17 0x0000029c 258 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA18 0x000002a0 259 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA19 0x000002a4 260 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7 0x000002a8 261 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6 0x000002ac 262 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA5 0x000002b0 263 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA4 0x000002b4 264 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_SD3_CMD 0x000002b8 265 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_SD3_CLK 0x000002bc 266 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0 0x000002c0 267 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1 0x000002c4 268 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA2 0x000002c8 269 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA3 0x000002cc 270 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_SD3_RESET 0x000002d0 271 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_NAND_CLE 0x000002d4 272 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_NAND_ALE 0x000002d8 273 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B 0x000002dc 274 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_NAND_READY_B 0x000002e0 275 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_NAND_CS0_B 0x000002e4 276 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_NAND_CS1_B 0x000002e8 277 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_NAND_CS2_B 0x000002ec 278 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_NAND_CS3_B 0x000002f0 279 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_SD4_CMD 0x000002f4 280 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_SD4_CLK 0x000002f8 281 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00 0x000002fc 282 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01 0x00000300 283 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02 0x00000304 284 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03 0x00000308 285 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA04 0x0000030c 286 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05 0x00000310 287 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06 0x00000314 288 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07 0x00000318 289 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA0 0x0000031c 290 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA1 0x00000320 291 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA2 0x00000324 292 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA3 0x00000328 293 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA4 0x0000032c 294 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA5 0x00000330 295 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA6 0x00000334 296 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA7 0x00000338 297 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1 0x0000033c 298 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA0 0x00000340 299 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA3 0x00000344 300 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_SD1_CMD 0x00000348 301 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA2 0x0000034c 302 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_SD1_CLK 0x00000350 303 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_SD2_CLK 0x00000354 304 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_SD2_CMD 0x00000358 305 #define IMX6DQ_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA3 0x0000035c 306 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1 0x00000360 307 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2 0x00000364 308 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0 0x00000368 309 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC 0x0000036c 310 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD0 0x00000370 311 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD1 0x00000374 312 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD2 0x00000378 313 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD3 0x0000037c 314 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL 0x00000380 315 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD0 0x00000384 316 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL 0x00000388 317 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD1 0x0000038c 318 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD2 0x00000390 319 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD3 0x00000394 320 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC 0x00000398 321 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25 0x0000039c 322 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_B 0x000003a0 323 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16 0x000003a4 324 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17 0x000003a8 325 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18 0x000003ac 326 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19 0x000003b0 327 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20 0x000003b4 328 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21 0x000003b8 329 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22 0x000003bc 330 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23 0x000003c0 331 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_B 0x000003c4 332 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24 0x000003c8 333 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25 0x000003cc 334 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26 0x000003d0 335 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27 0x000003d4 336 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28 0x000003d8 337 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29 0x000003dc 338 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30 0x000003e0 339 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31 0x000003e4 340 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24 0x000003e8 341 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23 0x000003ec 342 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22 0x000003f0 343 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21 0x000003f4 344 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20 0x000003f8 345 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19 0x000003fc 346 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18 0x00000400 347 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17 0x00000404 348 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16 0x00000408 349 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_B 0x0000040c 350 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_B 0x00000410 351 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_B 0x00000414 352 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_EIM_RW 0x00000418 353 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_B 0x0000041c 354 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_B 0x00000420 355 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_B 0x00000424 356 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00 0x00000428 357 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01 0x0000042c 358 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02 0x00000430 359 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03 0x00000434 360 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04 0x00000438 361 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05 0x0000043c 362 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06 0x00000440 363 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07 0x00000444 364 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08 0x00000448 365 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09 0x0000044c 366 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10 0x00000450 367 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11 0x00000454 368 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12 0x00000458 369 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13 0x0000045c 370 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14 0x00000460 371 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15 0x00000464 372 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_B 0x00000468 373 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK 0x0000046c 374 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK 0x00000470 375 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15 0x00000474 376 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02 0x00000478 377 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03 0x0000047c 378 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04 0x00000480 379 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00 0x00000484 380 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01 0x00000488 381 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02 0x0000048c 382 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03 0x00000490 383 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04 0x00000494 384 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05 0x00000498 385 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06 0x0000049c 386 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07 0x000004a0 387 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08 0x000004a4 388 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09 0x000004a8 389 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10 0x000004ac 390 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11 0x000004b0 391 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12 0x000004b4 392 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13 0x000004b8 393 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14 0x000004bc 394 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15 0x000004c0 395 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16 0x000004c4 396 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17 0x000004c8 397 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18 0x000004cc 398 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19 0x000004d0 399 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20 0x000004d4 400 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21 0x000004d8 401 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22 0x000004dc 402 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23 0x000004e0 403 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO 0x000004e4 404 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK 0x000004e8 405 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER 0x000004ec 406 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV 0x000004f0 407 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1 0x000004f4 408 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0 0x000004f8 409 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN 0x000004fc 410 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1 0x00000500 411 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0 0x00000504 412 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC 0x00000508 413 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P 0x0000050c 414 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5 0x00000510 415 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4 0x00000514 416 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P 0x00000518 417 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P 0x0000051c 418 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3 0x00000520 419 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P 0x00000524 420 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2 0x00000528 421 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00 0x0000052c 422 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01 0x00000530 423 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02 0x00000534 424 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03 0x00000538 425 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04 0x0000053c 426 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05 0x00000540 427 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06 0x00000544 428 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07 0x00000548 429 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08 0x0000054c 430 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09 0x00000550 431 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10 0x00000554 432 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11 0x00000558 433 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12 0x0000055c 434 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13 0x00000560 435 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14 0x00000564 436 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15 0x00000568 437 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_B 0x0000056c 438 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_B 0x00000570 439 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_B 0x00000574 440 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_B 0x00000578 441 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET 0x0000057c 442 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0 0x00000580 443 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1 0x00000584 444 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P 0x00000588 445 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2 0x0000058c 446 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0 0x00000590 447 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P 0x00000594 448 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1 0x00000598 449 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0 0x0000059c 450 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1 0x000005a0 451 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_B 0x000005a4 452 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P 0x000005a8 453 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0 0x000005ac 454 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P 0x000005b0 455 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1 0x000005b4 456 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P 0x000005b8 457 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6 0x000005bc 458 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P 0x000005c0 459 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7 0x000005c4 460 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0 0x000005c8 461 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0 0x000005cc 462 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_KEY_COL1 0x000005d0 463 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1 0x000005d4 464 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2 0x000005d8 465 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2 0x000005dc 466 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3 0x000005e0 467 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3 0x000005e4 468 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4 0x000005e8 469 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4 0x000005ec 470 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_GPIO00 0x000005f0 471 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_GPIO01 0x000005f4 472 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_GPIO09 0x000005f8 473 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_GPIO03 0x000005fc 474 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_GPIO06 0x00000600 475 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_GPIO02 0x00000604 476 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_GPIO04 0x00000608 477 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_GPIO05 0x0000060c 478 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_GPIO07 0x00000610 479 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_GPIO08 0x00000614 480 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_GPIO16 0x00000618 481 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_GPIO17 0x0000061c 482 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_GPIO18 0x00000620 483 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_GPIO19 0x00000624 484 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK 0x00000628 485 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC 0x0000062c 486 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN 0x00000630 487 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC 0x00000634 488 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04 0x00000638 489 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05 0x0000063c 490 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06 0x00000640 491 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07 0x00000644 492 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08 0x00000648 493 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09 0x0000064c 494 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10 0x00000650 495 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11 0x00000654 496 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12 0x00000658 497 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13 0x0000065c 498 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14 0x00000660 499 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15 0x00000664 500 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16 0x00000668 501 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17 0x0000066c 502 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18 0x00000670 503 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19 0x00000674 504 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS 0x00000678 505 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD 0x0000067c 506 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB 0x00000680 507 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI 0x00000684 508 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK 0x00000688 509 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO 0x0000068c 510 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7 0x00000690 511 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6 0x00000694 512 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5 0x00000698 513 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4 0x0000069c 514 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_SD3_CMD 0x000006a0 515 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_SD3_CLK 0x000006a4 516 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0 0x000006a8 517 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1 0x000006ac 518 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2 0x000006b0 519 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3 0x000006b4 520 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_SD3_RESET 0x000006b8 521 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE 0x000006bc 522 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE 0x000006c0 523 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B 0x000006c4 524 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_B 0x000006c8 525 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B 0x000006cc 526 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B 0x000006d0 527 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B 0x000006d4 528 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B 0x000006d8 529 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD 0x000006dc 530 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK 0x000006e0 531 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00 0x000006e4 532 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01 0x000006e8 533 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02 0x000006ec 534 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03 0x000006f0 535 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04 0x000006f4 536 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05 0x000006f8 537 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06 0x000006fc 538 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07 0x00000700 539 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0 0x00000704 540 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1 0x00000708 541 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2 0x0000070c 542 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3 0x00000710 543 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4 0x00000714 544 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5 0x00000718 545 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6 0x0000071c 546 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7 0x00000720 547 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1 0x00000724 548 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0 0x00000728 549 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3 0x0000072c 550 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD 0x00000730 551 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2 0x00000734 552 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK 0x00000738 553 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_SD2_CLK 0x0000073c 554 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD 0x00000740 555 #define IMX6DQ_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3 0x00000744 556 #define IMX6DQ_IOMUXC_SW_PAD_CTL_GRP_B7DS 0x00000748 557 #define IMX6DQ_IOMUXC_SW_PAD_CTL_GRP_ADDDS 0x0000074c 558 #define IMX6DQ_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL 0x00000750 559 #define IMX6DQ_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL0 0x00000754 560 #define IMX6DQ_IOMUXC_SW_PAD_CTL_GRP_DDRPKE 0x00000758 561 #define IMX6DQ_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL1 0x0000075c 562 #define IMX6DQ_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL2 0x00000760 563 #define IMX6DQ_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL3 0x00000764 564 #define IMX6DQ_IOMUXC_SW_PAD_CTL_GRP_DDRPK 0x00000768 565 #define IMX6DQ_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL4 0x0000076c 566 #define IMX6DQ_IOMUXC_SW_PAD_CTL_GRP_DDRHYS 0x00000770 567 #define IMX6DQ_IOMUXC_SW_PAD_CTL_GRP_DDRMODE 0x00000774 568 #define IMX6DQ_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL5 0x00000778 569 #define IMX6DQ_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL6 0x0000077c 570 #define IMX6DQ_IOMUXC_SW_PAD_CTL_GRP_TERM_CTL7 0x00000780 571 #define IMX6DQ_IOMUXC_SW_PAD_CTL_GRP_B0DS 0x00000784 572 #define IMX6DQ_IOMUXC_SW_PAD_CTL_GRP_B1DS 0x00000788 573 #define IMX6DQ_IOMUXC_SW_PAD_CTL_GRP_CTLDS 0x0000078c 574 #define IMX6DQ_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RGMII 0x00000790 575 #define IMX6DQ_IOMUXC_SW_PAD_CTL_GRP_B2DS 0x00000794 576 #define IMX6DQ_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE 0x00000798 577 #define IMX6DQ_IOMUXC_SW_PAD_CTL_GRP_B3DS 0x0000079c 578 #define IMX6DQ_IOMUXC_SW_PAD_CTL_GRP_B4DS 0x000007a0 579 #define IMX6DQ_IOMUXC_SW_PAD_CTL_GRP_B5DS 0x000007a4 580 #define IMX6DQ_IOMUXC_SW_PAD_CTL_GRP_B6DS 0x000007a8 581 #define IMX6DQ_IOMUXC_SW_PAD_CTL_GRP_RGMII_TERM 0x000007ac 582 #define IMX6DQ_IOMUXC_ASRC_ASRCK_CLOCK_6_SELECT_INPUT 0x000007b0 583 #define IMX6DQ_IOMUXC_AUD4_INPUT_DA_AMX_SELECT_INPUT 0x000007b4 584 #define IMX6DQ_IOMUXC_AUD4_INPUT_DB_AMX_SELECT_INPUT 0x000007b8 585 #define IMX6DQ_IOMUXC_AUD4_INPUT_RXCLK_AMX_SELECT_INPUT 0x000007bc 586 #define IMX6DQ_IOMUXC_AUD4_INPUT_RXFS_AMX_SELECT_INPUT 0x000007c0 587 #define IMX6DQ_IOMUXC_AUD4_INPUT_TXCLK_AMX_SELECT_INPUT 0x000007c4 588 #define IMX6DQ_IOMUXC_AUD4_INPUT_TXFS_AMX_SELECT_INPUT 0x000007c8 589 #define IMX6DQ_IOMUXC_AUD5_INPUT_DA_AMX_SELECT_INPUT 0x000007cc 590 #define IMX6DQ_IOMUXC_AUD5_INPUT_DB_AMX_SELECT_INPUT 0x000007d0 591 #define IMX6DQ_IOMUXC_AUD5_INPUT_RXCLK_AMX_SELECT_INPUT 0x000007d4 592 #define IMX6DQ_IOMUXC_AUD5_INPUT_RXFS_AMX_SELECT_INPUT 0x000007d8 593 #define IMX6DQ_IOMUXC_AUD5_INPUT_TXCLK_AMX_SELECT_INPUT 0x000007dc 594 #define IMX6DQ_IOMUXC_AUD5_INPUT_TXFS_AMX_SELECT_INPUT 0x000007e0 595 #define IMX6DQ_IOMUXC_FLEXCAN1_RX_SELECT_INPUT 0x000007e4 596 #define IMX6DQ_IOMUXC_FLEXCAN2_RX_SELECT_INPUT 0x000007e8 597 #define IMX6DQ_IOMUXC_CCM_PMIC_READY_SELECT_INPUT 0x000007f0 598 #define IMX6DQ_IOMUXC_ECSPI1_CSPI_CLK_IN_SELECT_INPUT 0x000007f4 599 #define IMX6DQ_IOMUXC_ECSPI1_MISO_SELECT_INPUT 0x000007f8 600 #define IMX6DQ_IOMUXC_ECSPI1_MOSI_SELECT_INPUT 0x000007fc 601 #define IMX6DQ_IOMUXC_ECSPI1_SS0_SELECT_INPUT 0x00000800 602 #define IMX6DQ_IOMUXC_ECSPI1_SS1_SELECT_INPUT 0x00000804 603 #define IMX6DQ_IOMUXC_ECSPI1_SS2_SELECT_INPUT 0x00000808 604 #define IMX6DQ_IOMUXC_ECSPI1_SS3_SELECT_INPUT 0x0000080c 605 #define IMX6DQ_IOMUXC_ECSPI2_CSPI_CLK_IN_SELECT_INPUT 0x00000810 606 #define IMX6DQ_IOMUXC_ECSPI2_MISO_SELECT_INPUT 0x00000814 607 #define IMX6DQ_IOMUXC_ECSPI2_MOSI_SELECT_INPUT 0x00000818 608 #define IMX6DQ_IOMUXC_ECSPI2_SS0_SELECT_INPUT 0x0000081c 609 #define IMX6DQ_IOMUXC_ECSPI2_SS1_SELECT_INPUT 0x00000820 610 #define IMX6DQ_IOMUXC_ECSPI4_SS0_SELECT_INPUT 0x00000824 611 #define IMX6DQ_IOMUXC_ECSPI5_CSPI_CLK_IN_SELECT_INPUT 0x00000828 612 #define IMX6DQ_IOMUXC_ECSPI5_MISO_SELECT_INPUT 0x0000082c 613 #define IMX6DQ_IOMUXC_ECSPI5_MOSI_SELECT_INPUT 0x00000830 614 #define IMX6DQ_IOMUXC_ECSPI5_SS0_SELECT_INPUT 0x00000834 615 #define IMX6DQ_IOMUXC_ECSPI5_SS1_SELECT_INPUT 0x00000838 616 #define IMX6DQ_IOMUXC_ENET_REF_CLK_SELECT_INPUT 0x0000083c 617 #define IMX6DQ_IOMUXC_ENET_MAC0_MDIO_SELECT_INPUT 0x00000840 618 #define IMX6DQ_IOMUXC_ENET_MAC0_RX_CLK_SELECT_INPUT 0x00000844 619 #define IMX6DQ_IOMUXC_ENET_MAC0_RX_DATA0_SELECT_INPUT 0x00000848 620 #define IMX6DQ_IOMUXC_ENET_MAC0_RX_DATA1_SELECT_INPUT 0x0000084c 621 #define IMX6DQ_IOMUXC_ENET_MAC0_RX_DATA2_SELECT_INPUT 0x00000850 622 #define IMX6DQ_IOMUXC_ENET_MAC0_RX_DATA3_SELECT_INPUT 0x00000854 623 #define IMX6DQ_IOMUXC_ENET_MAC0_RX_EN_SELECT_INPUT 0x00000858 624 #define IMX6DQ_IOMUXC_ESAI_RX_FS_SELECT_INPUT 0x0000085c 625 #define IMX6DQ_IOMUXC_ESAI_TX_FS_SELECT_INPUT 0x00000860 626 #define IMX6DQ_IOMUXC_ESAI_RX_HF_CLK_SELECT_INPUT 0x00000864 627 #define IMX6DQ_IOMUXC_ESAI_TX_HF_CLK_SELECT_INPUT 0x00000868 628 #define IMX6DQ_IOMUXC_ESAI_RX_CLK_SELECT_INPUT 0x0000086c 629 #define IMX6DQ_IOMUXC_ESAI_TX_CLK_SELECT_INPUT 0x00000870 630 #define IMX6DQ_IOMUXC_ESAI_SDO0_SELECT_INPUT 0x00000874 631 #define IMX6DQ_IOMUXC_ESAI_SDO1_SELECT_INPUT 0x00000878 632 #define IMX6DQ_IOMUXC_ESAI_SDO2_SDI3_SELECT_INPUT 0x0000087c 633 #define IMX6DQ_IOMUXC_ESAI_SDO3_SDI2_SELECT_INPUT 0x00000880 634 #define IMX6DQ_IOMUXC_ESAI_SDO4_SDI1_SELECT_INPUT 0x00000884 635 #define IMX6DQ_IOMUXC_ESAI_SDO5_SDI0_SELECT_INPUT 0x00000888 636 #define IMX6DQ_IOMUXC_HDMI_ICECIN_SELECT_INPUT 0x0000088c 637 #define IMX6DQ_IOMUXC_HDMI_II2C_CLKIN_SELECT_INPUT 0x00000890 638 #define IMX6DQ_IOMUXC_HDMI_II2C_DATAIN_SELECT_INPUT 0x00000894 639 #define IMX6DQ_IOMUXC_I2C1_SCL_IN_SELECT_INPUT 0x00000898 640 #define IMX6DQ_IOMUXC_I2C1_SDA_IN_SELECT_INPUT 0x0000089c 641 #define IMX6DQ_IOMUXC_I2C2_SCL_IN_SELECT_INPUT 0x000008a0 642 #define IMX6DQ_IOMUXC_I2C2_SDA_IN_SELECT_INPUT 0x000008a4 643 #define IMX6DQ_IOMUXC_I2C3_SCL_IN_SELECT_INPUT 0x000008a8 644 #define IMX6DQ_IOMUXC_I2C3_SDA_IN_SELECT_INPUT 0x000008ac 645 #define IMX6DQ_IOMUXC_IPU2_SENS1_DATA10_SELECT_INPUT 0x000008b0 646 #define IMX6DQ_IOMUXC_IPU2_SENS1_DATA11_SELECT_INPUT 0x000008b4 647 #define IMX6DQ_IOMUXC_IPU2_SENS1_DATA12_SELECT_INPUT 0x000008b8 648 #define IMX6DQ_IOMUXC_IPU2_SENS1_DATA13_SELECT_INPUT 0x000008bc 649 #define IMX6DQ_IOMUXC_IPU2_SENS1_DATA14_SELECT_INPUT 0x000008c0 650 #define IMX6DQ_IOMUXC_IPU2_SENS1_DATA15_SELECT_INPUT 0x000008c4 651 #define IMX6DQ_IOMUXC_IPU2_SENS1_DATA16_SELECT_INPUT 0x000008c8 652 #define IMX6DQ_IOMUXC_IPU2_SENS1_DATA17_SELECT_INPUT 0x000008cc 653 #define IMX6DQ_IOMUXC_IPU2_SENS1_DATA18_SELECT_INPUT 0x000008d0 654 #define IMX6DQ_IOMUXC_IPU2_SENS1_DATA19_SELECT_INPUT 0x000008d4 655 #define IMX6DQ_IOMUXC_IPU2_SENS1_DATA_EN_SELECT_INPUT 0x000008d8 656 #define IMX6DQ_IOMUXC_IPU2_SENS1_HSYNC_SELECT_INPUT 0x000008dc 657 #define IMX6DQ_IOMUXC_IPU2_SENS1_PIX_CLK_SELECT_INPUT 0x000008e0 658 #define IMX6DQ_IOMUXC_IPU2_SENS1_VSYNC_SELECT_INPUT 0x000008e4 659 #define IMX6DQ_IOMUXC_KEY_COL5_SELECT_INPUT 0x000008e8 660 #define IMX6DQ_IOMUXC_KEY_COL6_SELECT_INPUT 0x000008ec 661 #define IMX6DQ_IOMUXC_KEY_COL7_SELECT_INPUT 0x000008f0 662 #define IMX6DQ_IOMUXC_KEY_ROW5_SELECT_INPUT 0x000008f4 663 #define IMX6DQ_IOMUXC_KEY_ROW6_SELECT_INPUT 0x000008f8 664 #define IMX6DQ_IOMUXC_KEY_ROW7_SELECT_INPUT 0x000008fc 665 #define IMX6DQ_IOMUXC_MLB_MLB_CLK_IN_SELECT_INPUT 0x00000900 666 #define IMX6DQ_IOMUXC_MLB_MLB_DATA_IN_SELECT_INPUT 0x00000904 667 #define IMX6DQ_IOMUXC_MLB_MLB_SIG_IN_SELECT_INPUT 0x00000908 668 #define IMX6DQ_IOMUXC_SDMA_EVENTS14_SELECT_INPUT 0x0000090c 669 #define IMX6DQ_IOMUXC_SDMA_EVENTS15_SELECT_INPUT 0x00000910 670 #define IMX6DQ_IOMUXC_SPDIF_SPDIF_IN1_SELECT_INPUT 0x00000914 671 #define IMX6DQ_IOMUXC_SPDIF_TX_CLK2_SELECT_INPUT 0x00000918 672 #define IMX6DQ_IOMUXC_UART1_UART_RTS_B_SELECT_INPUT 0x0000091c 673 #define IMX6DQ_IOMUXC_UART1_UART_RX_DATA_SELECT_INPUT 0x00000920 674 #define IMX6DQ_IOMUXC_UART2_UART_RTS_B_SELECT_INPUT 0x00000924 675 #define IMX6DQ_IOMUXC_UART2_UART_RX_DATA_SELECT_INPUT 0x00000928 676 #define IMX6DQ_IOMUXC_UART3_UART_RTS_B_SELECT_INPUT 0x0000092c 677 #define IMX6DQ_IOMUXC_UART3_UART_RX_DATA_SELECT_INPUT 0x00000930 678 #define IMX6DQ_IOMUXC_UART4_UART_RTS_B_SELECT_INPUT 0x00000934 679 #define IMX6DQ_IOMUXC_UART4_UART_RX_DATA_SELECT_INPUT 0x00000938 680 #define IMX6DQ_IOMUXC_UART5_UART_RTS_B_SELECT_INPUT 0x0000093c 681 #define IMX6DQ_IOMUXC_UART5_UART_RX_DATA_SELECT_INPUT 0x00000940 682 #define IMX6DQ_IOMUXC_USB_OTG_OC_SELECT_INPUT 0x00000944 683 #define IMX6DQ_IOMUXC_USB_H1_OC_SELECT_INPUT 0x00000948 684 685 /* for iMX6Solo/DualLite */ 686 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA10 0x0000004c 687 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA11 0x00000050 688 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA12 0x00000054 689 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA13 0x00000058 690 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA14 0x0000005c 691 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA15 0x00000060 692 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA16 0x00000064 693 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA17 0x00000068 694 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA18 0x0000006c 695 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA19 0x00000070 696 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA04 0x00000074 697 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA05 0x00000078 698 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA06 0x0000007c 699 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA07 0x00000080 700 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA08 0x00000084 701 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA09 0x00000088 702 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA_EN 0x0000008c 703 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_CSI0_HSYNC 0x00000090 704 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_CSI0_PIXCLK 0x00000094 705 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_CSI0_VSYNC 0x00000098 706 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_DI0_DISP_CLK 0x0000009c 707 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN15 0x000000a0 708 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN02 0x000000a4 709 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN03 0x000000a8 710 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_DI0_PIN04 0x000000ac 711 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA00 0x000000b0 712 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA01 0x000000b4 713 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA10 0x000000b8 714 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA11 0x000000bc 715 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA12 0x000000c0 716 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA13 0x000000c4 717 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA14 0x000000c8 718 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA15 0x000000cc 719 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA16 0x000000d0 720 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA17 0x000000d4 721 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA18 0x000000d8 722 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA19 0x000000dc 723 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA02 0x000000e0 724 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA20 0x000000e4 725 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA21 0x000000e8 726 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA22 0x000000ec 727 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA23 0x000000f0 728 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA03 0x000000f4 729 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA04 0x000000f8 730 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA05 0x000000fc 731 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA06 0x00000100 732 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA07 0x00000104 733 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA08 0x00000108 734 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA09 0x0000010c 735 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR16 0x00000110 736 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR17 0x00000114 737 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR18 0x00000118 738 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR19 0x0000011c 739 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR20 0x00000120 740 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR21 0x00000124 741 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR22 0x00000128 742 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR23 0x0000012c 743 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR24 0x00000130 744 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR25 0x00000134 745 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_EIM_BCLK 0x00000138 746 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_EIM_CS0_B 0x0000013c 747 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_EIM_CS1_B 0x00000140 748 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA16 0x00000144 749 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA17 0x00000148 750 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA18 0x0000014c 751 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA19 0x00000150 752 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA20 0x00000154 753 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA21 0x00000158 754 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA22 0x0000015c 755 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA23 0x00000160 756 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA24 0x00000164 757 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA25 0x00000168 758 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA26 0x0000016c 759 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA27 0x00000170 760 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA28 0x00000174 761 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA29 0x00000178 762 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA30 0x0000017c 763 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_EIM_DATA31 0x00000180 764 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_EIM_AD00 0x00000184 765 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_EIM_AD01 0x00000188 766 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_EIM_AD10 0x0000018c 767 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_EIM_AD11 0x00000190 768 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_EIM_AD12 0x00000194 769 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_EIM_AD13 0x00000198 770 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_EIM_AD14 0x0000019c 771 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_EIM_AD15 0x000001a0 772 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_EIM_AD02 0x000001a4 773 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_EIM_AD03 0x000001a8 774 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_EIM_AD04 0x000001ac 775 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_EIM_AD05 0x000001b0 776 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_EIM_AD06 0x000001b4 777 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_EIM_AD07 0x000001b8 778 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_EIM_AD08 0x000001bc 779 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_EIM_AD09 0x000001c0 780 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_EIM_EB0_B 0x000001c4 781 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_EIM_EB1_B 0x000001c8 782 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_EIM_EB2_B 0x000001cc 783 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_EIM_EB3_B 0x000001d0 784 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_EIM_LBA_B 0x000001d4 785 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_EIM_OE_B 0x000001d8 786 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_EIM_RW 0x000001dc 787 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_EIM_WAIT_B 0x000001e0 788 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_ENET_CRS_DV 0x000001e4 789 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_ENET_MDC 0x000001e8 790 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_ENET_MDIO 0x000001ec 791 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_ENET_REF_CLK 0x000001f0 792 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_ER 0x000001f4 793 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA0 0x000001f8 794 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA1 0x000001fc 795 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_EN 0x00000200 796 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA0 0x00000204 797 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA1 0x00000208 798 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_GPIO00 0x0000020c 799 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_GPIO01 0x00000210 800 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_GPIO16 0x00000214 801 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_GPIO17 0x00000218 802 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_GPIO18 0x0000021c 803 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_GPIO19 0x00000220 804 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_GPIO02 0x00000224 805 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_GPIO03 0x00000228 806 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_GPIO04 0x0000022c 807 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_GPIO05 0x00000230 808 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_GPIO06 0x00000234 809 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_GPIO07 0x00000238 810 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_GPIO08 0x0000023c 811 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_GPIO09 0x00000240 812 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_KEY_COL0 0x00000244 813 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_KEY_COL1 0x00000248 814 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_KEY_COL2 0x0000024c 815 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_KEY_COL3 0x00000250 816 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_KEY_COL4 0x00000254 817 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW0 0x00000258 818 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW1 0x0000025c 819 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW2 0x00000260 820 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW3 0x00000264 821 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW4 0x00000268 822 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_NAND_ALE 0x0000026c 823 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_NAND_CLE 0x00000270 824 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_NAND_CS0_B 0x00000274 825 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_NAND_CS1_B 0x00000278 826 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_NAND_CS2_B 0x0000027c 827 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_NAND_CS3_B 0x00000280 828 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00 0x00000284 829 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01 0x00000288 830 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02 0x0000028c 831 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03 0x00000290 832 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA04 0x00000294 833 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05 0x00000298 834 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06 0x0000029c 835 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07 0x000002a0 836 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_NAND_READY_B 0x000002a4 837 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B 0x000002a8 838 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD0 0x000002ac 839 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD1 0x000002b0 840 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD2 0x000002b4 841 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_RGMII_RD3 0x000002b8 842 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_RGMII_RX_CTL 0x000002bc 843 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_RGMII_RXC 0x000002c0 844 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD0 0x000002c4 845 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD1 0x000002c8 846 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD2 0x000002cc 847 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_RGMII_TD3 0x000002d0 848 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_RGMII_TX_CTL 0x000002d4 849 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_RGMII_TXC 0x000002d8 850 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_SD1_CLK 0x000002dc 851 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_SD1_CMD 0x000002e0 852 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA0 0x000002e4 853 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1 0x000002e8 854 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA2 0x000002ec 855 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA3 0x000002f0 856 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_SD2_CLK 0x000002f4 857 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_SD2_CMD 0x000002f8 858 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA0 0x000002fc 859 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA1 0x00000300 860 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA2 0x00000304 861 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA3 0x00000308 862 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_SD3_CLK 0x0000030c 863 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_SD3_CMD 0x00000310 864 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0 0x00000314 865 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1 0x00000318 866 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA2 0x0000031c 867 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA3 0x00000320 868 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA4 0x00000324 869 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA5 0x00000328 870 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6 0x0000032c 871 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7 0x00000330 872 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_SD3_RESET 0x00000334 873 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_SD4_CLK 0x00000338 874 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_SD4_CMD 0x0000033c 875 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA0 0x00000340 876 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA1 0x00000344 877 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA2 0x00000348 878 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA3 0x0000034c 879 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA4 0x00000350 880 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA5 0x00000354 881 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA6 0x00000358 882 #define IMX6SDL_IOMUXC_SW_MUX_CTL_PAD_SD4_DATA7 0x0000035c 883 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10 0x00000360 884 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11 0x00000364 885 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12 0x00000368 886 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13 0x0000036c 887 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14 0x00000370 888 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15 0x00000374 889 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16 0x00000378 890 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17 0x0000037c 891 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18 0x00000380 892 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19 0x00000384 893 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04 0x00000388 894 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05 0x0000038c 895 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06 0x00000390 896 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07 0x00000394 897 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08 0x00000398 898 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09 0x0000039c 899 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN 0x000003a0 900 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC 0x000003a4 901 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK 0x000003a8 902 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC 0x000003ac 903 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK 0x000003b0 904 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15 0x000003b4 905 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02 0x000003b8 906 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03 0x000003bc 907 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04 0x000003c0 908 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00 0x000003c4 909 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01 0x000003c8 910 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10 0x000003cc 911 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11 0x000003d0 912 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12 0x000003d4 913 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13 0x000003d8 914 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14 0x000003dc 915 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15 0x000003e0 916 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16 0x000003e4 917 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17 0x000003e8 918 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18 0x000003ec 919 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19 0x000003f0 920 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02 0x000003f4 921 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20 0x000003f8 922 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21 0x000003fc 923 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22 0x00000400 924 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23 0x00000404 925 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03 0x00000408 926 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04 0x0000040c 927 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05 0x00000410 928 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06 0x00000414 929 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07 0x00000418 930 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08 0x0000041c 931 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09 0x00000420 932 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00 0x00000424 933 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01 0x00000428 934 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10 0x0000042c 935 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11 0x00000430 936 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12 0x00000434 937 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13 0x00000438 938 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14 0x0000043c 939 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15 0x00000440 940 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02 0x00000444 941 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03 0x00000448 942 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04 0x0000044c 943 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05 0x00000450 944 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06 0x00000454 945 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07 0x00000458 946 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08 0x0000045c 947 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09 0x00000460 948 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_B 0x00000464 949 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_B 0x00000468 950 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_B 0x0000046c 951 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0 0x00000470 952 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1 0x00000474 953 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2 0x00000478 954 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3 0x0000047c 955 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4 0x00000480 956 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5 0x00000484 957 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6 0x00000488 958 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7 0x0000048c 959 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_B 0x00000490 960 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET 0x00000494 961 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0 0x00000498 962 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1 0x0000049c 963 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2 0x000004a0 964 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0 0x000004a4 965 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1 0x000004a8 966 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P 0x000004ac 967 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P 0x000004b0 968 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0 0x000004b4 969 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1 0x000004b8 970 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P 0x000004bc 971 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P 0x000004c0 972 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P 0x000004c4 973 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P 0x000004c8 974 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P 0x000004cc 975 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P 0x000004d0 976 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P 0x000004d4 977 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P 0x000004d8 978 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_B 0x000004dc 979 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16 0x000004e0 980 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17 0x000004e4 981 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18 0x000004e8 982 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19 0x000004ec 983 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20 0x000004f0 984 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21 0x000004f4 985 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22 0x000004f8 986 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23 0x000004fc 987 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24 0x00000500 988 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25 0x00000504 989 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK 0x00000508 990 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_B 0x0000050c 991 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_B 0x00000510 992 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16 0x00000514 993 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17 0x00000518 994 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18 0x0000051c 995 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19 0x00000520 996 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20 0x00000524 997 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21 0x00000528 998 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22 0x0000052c 999 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23 0x00000530 1000 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24 0x00000534 1001 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25 0x00000538 1002 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26 0x0000053c 1003 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27 0x00000540 1004 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28 0x00000544 1005 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29 0x00000548 1006 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30 0x0000054c 1007 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31 0x00000550 1008 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_EIM_AD00 0x00000554 1009 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_EIM_AD01 0x00000558 1010 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_EIM_AD10 0x0000055c 1011 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_EIM_AD11 0x00000560 1012 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_EIM_AD12 0x00000564 1013 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_EIM_AD13 0x00000568 1014 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_EIM_AD14 0x0000056c 1015 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_EIM_AD15 0x00000570 1016 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_EIM_AD02 0x00000574 1017 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_EIM_AD03 0x00000578 1018 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_EIM_AD04 0x0000057c 1019 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_EIM_AD05 0x00000580 1020 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_EIM_AD06 0x00000584 1021 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_EIM_AD07 0x00000588 1022 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_EIM_AD08 0x0000058c 1023 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_EIM_AD09 0x00000590 1024 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_B 0x00000594 1025 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_B 0x00000598 1026 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_B 0x0000059c 1027 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_B 0x000005a0 1028 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_B 0x000005a4 1029 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_EIM_OE_B 0x000005a8 1030 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_EIM_RW 0x000005ac 1031 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_B 0x000005b0 1032 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV 0x000005b4 1033 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_ENET_MDC 0x000005b8 1034 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO 0x000005bc 1035 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK 0x000005c0 1036 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER 0x000005c4 1037 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0 0x000005c8 1038 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1 0x000005cc 1039 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN 0x000005d0 1040 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0 0x000005d4 1041 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1 0x000005d8 1042 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_GPIO00 0x000005dc 1043 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_GPIO01 0x000005e0 1044 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_GPIO16 0x000005e4 1045 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_GPIO17 0x000005e8 1046 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_GPIO18 0x000005ec 1047 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_GPIO19 0x000005f0 1048 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_GPIO02 0x000005f4 1049 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_GPIO03 0x000005f8 1050 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_GPIO04 0x000005fc 1051 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_GPIO05 0x00000600 1052 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_GPIO06 0x00000604 1053 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_GPIO07 0x00000608 1054 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_GPIO08 0x0000060c 1055 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_GPIO09 0x00000610 1056 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD 0x00000614 1057 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK 0x00000618 1058 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI 0x0000061c 1059 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO 0x00000620 1060 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS 0x00000624 1061 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB 0x00000628 1062 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0 0x0000062c 1063 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_KEY_COL1 0x00000630 1064 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2 0x00000634 1065 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3 0x00000638 1066 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4 0x0000063c 1067 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0 0x00000640 1068 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1 0x00000644 1069 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2 0x00000648 1070 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3 0x0000064c 1071 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4 0x00000650 1072 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE 0x00000654 1073 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE 0x00000658 1074 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B 0x0000065c 1075 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B 0x00000660 1076 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B 0x00000664 1077 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B 0x00000668 1078 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00 0x0000066c 1079 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01 0x00000670 1080 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02 0x00000674 1081 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03 0x00000678 1082 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04 0x0000067c 1083 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05 0x00000680 1084 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06 0x00000684 1085 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07 0x00000688 1086 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_B 0x0000068c 1087 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B 0x00000690 1088 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD0 0x00000694 1089 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD1 0x00000698 1090 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD2 0x0000069c 1091 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_RGMII_RD3 0x000006a0 1092 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL 0x000006a4 1093 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC 0x000006a8 1094 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD0 0x000006ac 1095 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD1 0x000006b0 1096 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD2 0x000006b4 1097 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_RGMII_TD3 0x000006b8 1098 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL 0x000006bc 1099 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC 0x000006c0 1100 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK 0x000006c4 1101 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD 0x000006c8 1102 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0 0x000006cc 1103 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1 0x000006d0 1104 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2 0x000006d4 1105 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3 0x000006d8 1106 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_SD2_CLK 0x000006dc 1107 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD 0x000006e0 1108 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0 0x000006e4 1109 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1 0x000006e8 1110 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2 0x000006ec 1111 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3 0x000006f0 1112 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_SD3_CLK 0x000006f4 1113 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_SD3_CMD 0x000006f8 1114 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0 0x000006fc 1115 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1 0x00000700 1116 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2 0x00000704 1117 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3 0x00000708 1118 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4 0x0000070c 1119 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5 0x00000710 1120 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6 0x00000714 1121 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7 0x00000718 1122 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_SD3_RESET 0x0000071c 1123 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_SD4_CLK 0x00000720 1124 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_SD4_CMD 0x00000724 1125 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0 0x00000728 1126 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1 0x0000072c 1127 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2 0x00000730 1128 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3 0x00000734 1129 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4 0x00000738 1130 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5 0x0000073c 1131 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6 0x00000740 1132 #define IMX6SDL_IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7 0x00000744 1133 #define IMX6SDL_IOMUXC_SW_PAD_CTL_GRP_B7DS 0x00000748 1134 #define IMX6SDL_IOMUXC_SW_PAD_CTL_GRP_ADDDS 0x0000074c 1135 #define IMX6SDL_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL 0x00000750 1136 #define IMX6SDL_IOMUXC_SW_PAD_CTL_GRP_DDRPKE 0x00000754 1137 #define IMX6SDL_IOMUXC_SW_PAD_CTL_GRP_DDRPK 0x00000758 1138 #define IMX6SDL_IOMUXC_SW_PAD_CTL_GRP_DDRHYS 0x0000075c 1139 #define IMX6SDL_IOMUXC_SW_PAD_CTL_GRP_DDRMODE 0x00000760 1140 #define IMX6SDL_IOMUXC_SW_PAD_CTL_GRP_B0DS 0x00000764 1141 #define IMX6SDL_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RGMII 0x00000768 1142 #define IMX6SDL_IOMUXC_SW_PAD_CTL_GRP_CTLDS 0x0000076c 1143 #define IMX6SDL_IOMUXC_SW_PAD_CTL_GRP_B1DS 0x00000770 1144 #define IMX6SDL_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE 0x00000774 1145 #define IMX6SDL_IOMUXC_SW_PAD_CTL_GRP_B2DS 0x00000778 1146 #define IMX6SDL_IOMUXC_SW_PAD_CTL_GRP_B3DS 0x0000077c 1147 #define IMX6SDL_IOMUXC_SW_PAD_CTL_GRP_B4DS 0x00000780 1148 #define IMX6SDL_IOMUXC_SW_PAD_CTL_GRP_B5DS 0x00000784 1149 #define IMX6SDL_IOMUXC_SW_PAD_CTL_GRP_RGMII_TERM 0x00000788 1150 #define IMX6SDL_IOMUXC_SW_PAD_CTL_GRP_B6DS 0x0000078c 1151 #define IMX6SDL_IOMUXC_ANALOG_USB_OTG_ID_SELECT_INPUT 0x00000790 1152 #define IMX6SDL_IOMUXC_ASRC_ASRCK_CLOCK_6_SELECT_INPUT 0x00000794 1153 #define IMX6SDL_IOMUXC_AUD4_INPUT_DA_AMX_SELECT_INPUT 0x00000798 1154 #define IMX6SDL_IOMUXC_AUD4_INPUT_DB_AMX_SELECT_INPUT 0x0000079c 1155 #define IMX6SDL_IOMUXC_AUD4_INPUT_RXCLK_AMX_SELECT_INPUT 0x000007a0 1156 #define IMX6SDL_IOMUXC_AUD4_INPUT_RXFS_AMX_SELECT_INPUT 0x000007a4 1157 #define IMX6SDL_IOMUXC_AUD4_INPUT_TXCLK_AMX_SELECT_INPUT 0x000007a8 1158 #define IMX6SDL_IOMUXC_AUD4_INPUT_TXFS_AMX_SELECT_INPUT 0x000007ac 1159 #define IMX6SDL_IOMUXC_AUD5_INPUT_DA_AMX_SELECT_INPUT 0x000007b0 1160 #define IMX6SDL_IOMUXC_AUD5_INPUT_DB_AMX_SELECT_INPUT 0x000007b4 1161 #define IMX6SDL_IOMUXC_AUD5_INPUT_RXCLK_AMX_SELECT_INPUT 0x000007b8 1162 #define IMX6SDL_IOMUXC_AUD5_INPUT_RXFS_AMX_SELECT_INPUT 0x000007bc 1163 #define IMX6SDL_IOMUXC_AUD5_INPUT_TXCLK_AMX_SELECT_INPUT 0x000007c0 1164 #define IMX6SDL_IOMUXC_AUD5_INPUT_TXFS_AMX_SELECT_INPUT 0x000007c4 1165 #define IMX6SDL_IOMUXC_FLEXCAN1_RX_SELECT_INPUT 0x000007c8 1166 #define IMX6SDL_IOMUXC_FLEXCAN2_RX_SELECT_INPUT 0x000007cc 1167 #define IMX6SDL_IOMUXC_CCM_PMIC_READY_SELECT_INPUT 0x000007d4 1168 #define IMX6SDL_IOMUXC_ECSPI1_CSPI_CLK_IN_SELECT_INPUT 0x000007d8 1169 #define IMX6SDL_IOMUXC_ECSPI1_MISO_SELECT_INPUT 0x000007dc 1170 #define IMX6SDL_IOMUXC_ECSPI1_MOSI_SELECT_INPUT 0x000007e0 1171 #define IMX6SDL_IOMUXC_ECSPI1_SS0_SELECT_INPUT 0x000007e4 1172 #define IMX6SDL_IOMUXC_ECSPI1_SS1_SELECT_INPUT 0x000007e8 1173 #define IMX6SDL_IOMUXC_ECSPI1_SS2_SELECT_INPUT 0x000007ec 1174 #define IMX6SDL_IOMUXC_ECSPI1_SS3_SELECT_INPUT 0x000007f0 1175 #define IMX6SDL_IOMUXC_ECSPI2_CSPI_CLK_IN_SELECT_INPUT 0x000007f4 1176 #define IMX6SDL_IOMUXC_ECSPI2_MISO_SELECT_INPUT 0x000007f8 1177 #define IMX6SDL_IOMUXC_ECSPI2_MOSI_SELECT_INPUT 0x000007fc 1178 #define IMX6SDL_IOMUXC_ECSPI2_SS0_SELECT_INPUT 0x00000800 1179 #define IMX6SDL_IOMUXC_ECSPI2_SS1_SELECT_INPUT 0x00000804 1180 #define IMX6SDL_IOMUXC_ECSPI4_SS0_SELECT_INPUT 0x00000808 1181 #define IMX6SDL_IOMUXC_ENET_REF_CLK_SELECT_INPUT 0x0000080c 1182 #define IMX6SDL_IOMUXC_ENET_MAC0_MDIO_SELECT_INPUT 0x00000810 1183 #define IMX6SDL_IOMUXC_ENET_MAC0_RX_CLK_SELECT_INPUT 0x00000814 1184 #define IMX6SDL_IOMUXC_ENET_MAC0_RX_DATA0_SELECT_INPUT 0x00000818 1185 #define IMX6SDL_IOMUXC_ENET_MAC0_RX_DATA1_SELECT_INPUT 0x0000081c 1186 #define IMX6SDL_IOMUXC_ENET_MAC0_RX_DATA2_SELECT_INPUT 0x00000820 1187 #define IMX6SDL_IOMUXC_ENET_MAC0_RX_DATA3_SELECT_INPUT 0x00000824 1188 #define IMX6SDL_IOMUXC_ENET_MAC0_RX_EN_SELECT_INPUT 0x00000828 1189 #define IMX6SDL_IOMUXC_ESAI_RX_FS_SELECT_INPUT 0x0000082c 1190 #define IMX6SDL_IOMUXC_ESAI_TX_FS_SELECT_INPUT 0x00000830 1191 #define IMX6SDL_IOMUXC_ESAI_RX_HF_CLK_SELECT_INPUT 0x00000834 1192 #define IMX6SDL_IOMUXC_ESAI_TX_HF_CLK_SELECT_INPUT 0x00000838 1193 #define IMX6SDL_IOMUXC_ESAI_RX_CLK_SELECT_INPUT 0x0000083c 1194 #define IMX6SDL_IOMUXC_ESAI_TX_CLK_SELECT_INPUT 0x00000840 1195 #define IMX6SDL_IOMUXC_ESAI_SDO0_SELECT_INPUT 0x00000844 1196 #define IMX6SDL_IOMUXC_ESAI_SDO1_SELECT_INPUT 0x00000848 1197 #define IMX6SDL_IOMUXC_ESAI_SDO2_SDI3_SELECT_INPUT 0x0000084c 1198 #define IMX6SDL_IOMUXC_ESAI_SDO3_SDI2_SELECT_INPUT 0x00000850 1199 #define IMX6SDL_IOMUXC_ESAI_SDO4_SDI1_SELECT_INPUT 0x00000854 1200 #define IMX6SDL_IOMUXC_ESAI_SDO5_SDI0_SELECT_INPUT 0x00000858 1201 #define IMX6SDL_IOMUXC_HDMI_ICECIN_SELECT_INPUT 0x0000085c 1202 #define IMX6SDL_IOMUXC_HDMI_II2C_CLKIN_SELECT_INPUT 0x00000860 1203 #define IMX6SDL_IOMUXC_HDMI_II2C_DATAIN_SELECT_INPUT 0x00000864 1204 #define IMX6SDL_IOMUXC_I2C1_SCL_IN_SELECT_INPUT 0x00000868 1205 #define IMX6SDL_IOMUXC_I2C1_SDA_IN_SELECT_INPUT 0x0000086c 1206 #define IMX6SDL_IOMUXC_I2C2_SCL_IN_SELECT_INPUT 0x00000870 1207 #define IMX6SDL_IOMUXC_I2C2_SDA_IN_SELECT_INPUT 0x00000874 1208 #define IMX6SDL_IOMUXC_I2C3_SCL_IN_SELECT_INPUT 0x00000878 1209 #define IMX6SDL_IOMUXC_I2C3_SDA_IN_SELECT_INPUT 0x0000087c 1210 #define IMX6SDL_IOMUXC_I2C4_SCL_IN_SELECT_INPUT 0x00000880 1211 #define IMX6SDL_IOMUXC_I2C4_SDA_IN_SELECT_INPUT 0x00000884 1212 #define IMX6SDL_IOMUXC_IPU1_SENS1_DATA10_SELECT_INPUT 0x00000888 1213 #define IMX6SDL_IOMUXC_IPU1_SENS1_DATA11_SELECT_INPUT 0x0000088c 1214 #define IMX6SDL_IOMUXC_IPU1_SENS1_DATA12_SELECT_INPUT 0x00000890 1215 #define IMX6SDL_IOMUXC_IPU1_SENS1_DATA13_SELECT_INPUT 0x00000894 1216 #define IMX6SDL_IOMUXC_IPU1_SENS1_DATA14_SELECT_INPUT 0x00000898 1217 #define IMX6SDL_IOMUXC_IPU1_SENS1_DATA15_SELECT_INPUT 0x0000089c 1218 #define IMX6SDL_IOMUXC_IPU1_SENS1_DATA16_SELECT_INPUT 0x000008a0 1219 #define IMX6SDL_IOMUXC_IPU1_SENS1_DATA17_SELECT_INPUT 0x000008a4 1220 #define IMX6SDL_IOMUXC_IPU1_SENS1_DATA18_SELECT_INPUT 0x000008a8 1221 #define IMX6SDL_IOMUXC_IPU1_SENS1_DATA19_SELECT_INPUT 0x000008ac 1222 #define IMX6SDL_IOMUXC_IPU1_SENS1_DATA_EN_SELECT_INPUT 0x000008b0 1223 #define IMX6SDL_IOMUXC_IPU1_SENS1_HSYNC_SELECT_INPUT 0x000008b4 1224 #define IMX6SDL_IOMUXC_IPU1_SENS1_PIX_CLK_SELECT_INPUT 0x000008b8 1225 #define IMX6SDL_IOMUXC_IPU1_SENS1_VSYNC_SELECT_INPUT 0x000008bc 1226 #define IMX6SDL_IOMUXC_KEY_COL5_SELECT_INPUT 0x000008c0 1227 #define IMX6SDL_IOMUXC_KEY_COL6_SELECT_INPUT 0x000008c4 1228 #define IMX6SDL_IOMUXC_KEY_COL7_SELECT_INPUT 0x000008c8 1229 #define IMX6SDL_IOMUXC_KEY_ROW5_SELECT_INPUT 0x000008cc 1230 #define IMX6SDL_IOMUXC_KEY_ROW6_SELECT_INPUT 0x000008d0 1231 #define IMX6SDL_IOMUXC_KEY_ROW7_SELECT_INPUT 0x000008d4 1232 #define IMX6SDL_IOMUXC_MLB_MLB_CLK_IN_SELECT_INPUT 0x000008dc 1233 #define IMX6SDL_IOMUXC_MLB_MLB_DATA_IN_SELECT_INPUT 0x000008e0 1234 #define IMX6SDL_IOMUXC_MLB_MLB_SIG_IN_SELECT_INPUT 0x000008e4 1235 #define IMX6SDL_IOMUXC_SDMA_EVENTS14_SELECT_INPUT 0x000008e8 1236 #define IMX6SDL_IOMUXC_SDMA_EVENTS15_SELECT_INPUT 0x000008ec 1237 #define IMX6SDL_IOMUXC_SPDIF_SPDIF_IN1_SELECT_INPUT 0x000008f0 1238 #define IMX6SDL_IOMUXC_SPDIF_TX_CLK2_SELECT_INPUT 0x000008f4 1239 #define IMX6SDL_IOMUXC_UART1_UART_RTS_B_SELECT_INPUT 0x000008f8 1240 #define IMX6SDL_IOMUXC_UART1_UART_RX_DATA_SELECT_INPUT 0x000008fc 1241 #define IMX6SDL_IOMUXC_UART2_UART_RTS_B_SELECT_INPUT 0x00000900 1242 #define IMX6SDL_IOMUXC_UART2_UART_RX_DATA_SELECT_INPUT 0x00000904 1243 #define IMX6SDL_IOMUXC_UART3_UART_RTS_B_SELECT_INPUT 0x00000908 1244 #define IMX6SDL_IOMUXC_UART3_UART_RX_DATA_SELECT_INPUT 0x0000090c 1245 #define IMX6SDL_IOMUXC_UART4_UART_RTS_B_SELECT_INPUT 0x00000910 1246 #define IMX6SDL_IOMUXC_UART4_UART_RX_DATA_SELECT_INPUT 0x00000914 1247 #define IMX6SDL_IOMUXC_UART5_UART_RTS_B_SELECT_INPUT 0x00000918 1248 #define IMX6SDL_IOMUXC_UART5_UART_RX_DATA_SELECT_INPUT 0x0000091c 1249 #define IMX6SDL_IOMUXC_USB_OTG_OC_SELECT_INPUT 0x00000920 1250 #define IMX6SDL_IOMUXC_USB_H1_OC_SELECT_INPUT 0x00000924 1251 #define IMX6SDL_IOMUXC_USDHC1_CARD_CLK_IN_SELECT_INPUT 0x00000928 1252 #define IMX6SDL_IOMUXC_USDHC1_WP_ON_SELECT_INPUT 0x0000092c 1253 #define IMX6SDL_IOMUXC_USDHC2_CARD_CLK_IN_SELECT_INPUT 0x00000930 1254 #define IMX6SDL_IOMUXC_USDHC3_CARD_CLK_IN_SELECT_INPUT 0x00000934 1255 #define IMX6SDL_IOMUXC_USDHC4_CARD_CLK_IN_SELECT_INPUT 0x00000938 1256 1257 /* for iMX6SoloLite */ 1258 #define IMX6SL_IOMUXC_SW_MUX_CTL_PAD_AUD_MCLK 0x0000004c 1259 #define IMX6SL_IOMUXC_SW_MUX_CTL_PAD_AUD_RXC 0x00000050 1260 #define IMX6SL_IOMUXC_SW_MUX_CTL_PAD_AUD_RXD 0x00000054 1261 #define IMX6SL_IOMUXC_SW_MUX_CTL_PAD_AUD_RXFS 0x00000058 1262 #define IMX6SL_IOMUXC_SW_MUX_CTL_PAD_AUD_TXC 0x0000005c 1263 #define IMX6SL_IOMUXC_SW_MUX_CTL_PAD_AUD_TXD 0x00000060 1264 #define IMX6SL_IOMUXC_SW_MUX_CTL_PAD_AUD_TXFS 0x00000064 1265 #define IMX6SL_IOMUXC_SW_MUX_CTL_PAD_ECSPI1_MISO 0x00000068 1266 #define IMX6SL_IOMUXC_SW_MUX_CTL_PAD_ECSPI1_MOSI 0x0000006c 1267 #define IMX6SL_IOMUXC_SW_MUX_CTL_PAD_ECSPI1_SCLK 0x00000070 1268 #define IMX6SL_IOMUXC_SW_MUX_CTL_PAD_ECSPI1_SS0 0x00000074 1269 #define IMX6SL_IOMUXC_SW_MUX_CTL_PAD_ECSPI2_MISO 0x00000078 1270 #define IMX6SL_IOMUXC_SW_MUX_CTL_PAD_ECSPI2_MOSI 0x0000007c 1271 #define IMX6SL_IOMUXC_SW_MUX_CTL_PAD_ECSPI2_SCLK 0x00000080 1272 #define IMX6SL_IOMUXC_SW_MUX_CTL_PAD_ECSPI2_SS0 0x00000084 1273 #define IMX6SL_IOMUXC_SW_MUX_CTL_PAD_EPDC_BDR0 0x00000088 1274 #define IMX6SL_IOMUXC_SW_MUX_CTL_PAD_EPDC_BDR1 0x0000008c 1275 #define IMX6SL_IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA00 0x00000090 1276 #define IMX6SL_IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA01 0x00000094 1277 #define IMX6SL_IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA10 0x00000098 1278 #define IMX6SL_IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA11 0x0000009c 1279 #define IMX6SL_IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA12 0x000000a0 1280 #define IMX6SL_IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA13 0x000000a4 1281 #define IMX6SL_IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA14 0x000000a8 1282 #define IMX6SL_IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA15 0x000000ac 1283 #define IMX6SL_IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA02 0x000000b0 1284 #define IMX6SL_IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA03 0x000000b4 1285 #define IMX6SL_IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA04 0x000000b8 1286 #define IMX6SL_IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA05 0x000000bc 1287 #define IMX6SL_IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA06 0x000000c0 1288 #define IMX6SL_IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA07 0x000000c4 1289 #define IMX6SL_IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA08 0x000000c8 1290 #define IMX6SL_IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA09 0x000000cc 1291 #define IMX6SL_IOMUXC_SW_MUX_CTL_PAD_EPDC_GDCLK 0x000000d0 1292 #define IMX6SL_IOMUXC_SW_MUX_CTL_PAD_EPDC_GDOE 0x000000d4 1293 #define IMX6SL_IOMUXC_SW_MUX_CTL_PAD_EPDC_GDRL 0x000000d8 1294 #define IMX6SL_IOMUXC_SW_MUX_CTL_PAD_EPDC_GDSP 0x000000dc 1295 #define IMX6SL_IOMUXC_SW_MUX_CTL_PAD_EPDC_PWR_COM 0x000000e0 1296 #define IMX6SL_IOMUXC_SW_MUX_CTL_PAD_EPDC_PWR_CTRL0 0x000000e4 1297 #define IMX6SL_IOMUXC_SW_MUX_CTL_PAD_EPDC_PWR_CTRL1 0x000000e8 1298 #define IMX6SL_IOMUXC_SW_MUX_CTL_PAD_EPDC_PWR_CTRL2 0x000000ec 1299 #define IMX6SL_IOMUXC_SW_MUX_CTL_PAD_EPDC_PWR_CTRL3 0x000000f0 1300 #define IMX6SL_IOMUXC_SW_MUX_CTL_PAD_EPDC_PWR_IRQ 0x000000f4 1301 #define IMX6SL_IOMUXC_SW_MUX_CTL_PAD_EPDC_PWR_STAT 0x000000f8 1302 #define IMX6SL_IOMUXC_SW_MUX_CTL_PAD_EPDC_PWR_WAKE 0x000000fc 1303 #define IMX6SL_IOMUXC_SW_MUX_CTL_PAD_EPDC_SDCE0 0x00000100 1304 #define IMX6SL_IOMUXC_SW_MUX_CTL_PAD_EPDC_SDCE1 0x00000104 1305 #define IMX6SL_IOMUXC_SW_MUX_CTL_PAD_EPDC_SDCE2 0x00000108 1306 #define IMX6SL_IOMUXC_SW_MUX_CTL_PAD_EPDC_SDCE3 0x0000010c 1307 #define IMX6SL_IOMUXC_SW_MUX_CTL_PAD_EPDC_SDCLK 0x00000110 1308 #define IMX6SL_IOMUXC_SW_MUX_CTL_PAD_EPDC_SDLE 0x00000114 1309 #define IMX6SL_IOMUXC_SW_MUX_CTL_PAD_EPDC_SDOE 0x00000118 1310 #define IMX6SL_IOMUXC_SW_MUX_CTL_PAD_EPDC_SDSHR 0x0000011c 1311 #define IMX6SL_IOMUXC_SW_MUX_CTL_PAD_EPDC_VCOM0 0x00000120 1312 #define IMX6SL_IOMUXC_SW_MUX_CTL_PAD_EPDC_VCOM1 0x00000124 1313 #define IMX6SL_IOMUXC_SW_MUX_CTL_PAD_FEC_CRS_DV 0x00000128 1314 #define IMX6SL_IOMUXC_SW_MUX_CTL_PAD_FEC_MDC 0x0000012c 1315 #define IMX6SL_IOMUXC_SW_MUX_CTL_PAD_FEC_MDIO 0x00000130 1316 #define IMX6SL_IOMUXC_SW_MUX_CTL_PAD_FEC_REF_CLK 0x00000134 1317 #define IMX6SL_IOMUXC_SW_MUX_CTL_PAD_FEC_RX_ER 0x00000138 1318 #define IMX6SL_IOMUXC_SW_MUX_CTL_PAD_FEC_RX_DATA0 0x0000013c 1319 #define IMX6SL_IOMUXC_SW_MUX_CTL_PAD_FEC_RX_DATA1 0x00000140 1320 #define IMX6SL_IOMUXC_SW_MUX_CTL_PAD_FEC_TX_CLK 0x00000144 1321 #define IMX6SL_IOMUXC_SW_MUX_CTL_PAD_FEC_TX_EN 0x00000148 1322 #define IMX6SL_IOMUXC_SW_MUX_CTL_PAD_FEC_TX_DATA0 0x0000014c 1323 #define IMX6SL_IOMUXC_SW_MUX_CTL_PAD_FEC_TX_DATA1 0x00000150 1324 #define IMX6SL_IOMUXC_SW_MUX_CTL_PAD_USB_H_DATA 0x00000154 1325 #define IMX6SL_IOMUXC_SW_MUX_CTL_PAD_USB_H_STROBE 0x00000158 1326 #define IMX6SL_IOMUXC_SW_MUX_CTL_PAD_I2C1_SCL 0x0000015c 1327 #define IMX6SL_IOMUXC_SW_MUX_CTL_PAD_I2C1_SDA 0x00000160 1328 #define IMX6SL_IOMUXC_SW_MUX_CTL_PAD_I2C2_SCL 0x00000164 1329 #define IMX6SL_IOMUXC_SW_MUX_CTL_PAD_I2C2_SDA 0x00000168 1330 #define IMX6SL_IOMUXC_SW_MUX_CTL_PAD_KEY_COL0 0x0000016c 1331 #define IMX6SL_IOMUXC_SW_MUX_CTL_PAD_KEY_COL1 0x00000170 1332 #define IMX6SL_IOMUXC_SW_MUX_CTL_PAD_KEY_COL2 0x00000174 1333 #define IMX6SL_IOMUXC_SW_MUX_CTL_PAD_KEY_COL3 0x00000178 1334 #define IMX6SL_IOMUXC_SW_MUX_CTL_PAD_KEY_COL4 0x0000017c 1335 #define IMX6SL_IOMUXC_SW_MUX_CTL_PAD_KEY_COL5 0x00000180 1336 #define IMX6SL_IOMUXC_SW_MUX_CTL_PAD_KEY_COL6 0x00000184 1337 #define IMX6SL_IOMUXC_SW_MUX_CTL_PAD_KEY_COL7 0x00000188 1338 #define IMX6SL_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW0 0x0000018c 1339 #define IMX6SL_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW1 0x00000190 1340 #define IMX6SL_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW2 0x00000194 1341 #define IMX6SL_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW3 0x00000198 1342 #define IMX6SL_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW4 0x0000019c 1343 #define IMX6SL_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW5 0x000001a0 1344 #define IMX6SL_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW6 0x000001a4 1345 #define IMX6SL_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW7 0x000001a8 1346 #define IMX6SL_IOMUXC_SW_MUX_CTL_PAD_LCD_CLK 0x000001ac 1347 #define IMX6SL_IOMUXC_SW_MUX_CTL_PAD_LCD_DATA00 0x000001b0 1348 #define IMX6SL_IOMUXC_SW_MUX_CTL_PAD_LCD_DATA01 0x000001b4 1349 #define IMX6SL_IOMUXC_SW_MUX_CTL_PAD_LCD_DATA10 0x000001b8 1350 #define IMX6SL_IOMUXC_SW_MUX_CTL_PAD_LCD_DATA11 0x000001bc 1351 #define IMX6SL_IOMUXC_SW_MUX_CTL_PAD_LCD_DATA12 0x000001c0 1352 #define IMX6SL_IOMUXC_SW_MUX_CTL_PAD_LCD_DATA13 0x000001c4 1353 #define IMX6SL_IOMUXC_SW_MUX_CTL_PAD_LCD_DATA14 0x000001c8 1354 #define IMX6SL_IOMUXC_SW_MUX_CTL_PAD_LCD_DATA15 0x000001cc 1355 #define IMX6SL_IOMUXC_SW_MUX_CTL_PAD_LCD_DATA16 0x000001d0 1356 #define IMX6SL_IOMUXC_SW_MUX_CTL_PAD_LCD_DATA17 0x000001d4 1357 #define IMX6SL_IOMUXC_SW_MUX_CTL_PAD_LCD_DATA18 0x000001d8 1358 #define IMX6SL_IOMUXC_SW_MUX_CTL_PAD_LCD_DATA19 0x000001dc 1359 #define IMX6SL_IOMUXC_SW_MUX_CTL_PAD_LCD_DATA02 0x000001e0 1360 #define IMX6SL_IOMUXC_SW_MUX_CTL_PAD_LCD_DATA20 0x000001e4 1361 #define IMX6SL_IOMUXC_SW_MUX_CTL_PAD_LCD_DATA21 0x000001e8 1362 #define IMX6SL_IOMUXC_SW_MUX_CTL_PAD_LCD_DATA22 0x000001ec 1363 #define IMX6SL_IOMUXC_SW_MUX_CTL_PAD_LCD_DATA23 0x000001f0 1364 #define IMX6SL_IOMUXC_SW_MUX_CTL_PAD_LCD_DATA03 0x000001f4 1365 #define IMX6SL_IOMUXC_SW_MUX_CTL_PAD_LCD_DATA04 0x000001f8 1366 #define IMX6SL_IOMUXC_SW_MUX_CTL_PAD_LCD_DATA05 0x000001fc 1367 #define IMX6SL_IOMUXC_SW_MUX_CTL_PAD_LCD_DATA06 0x00000200 1368 #define IMX6SL_IOMUXC_SW_MUX_CTL_PAD_LCD_DATA07 0x00000204 1369 #define IMX6SL_IOMUXC_SW_MUX_CTL_PAD_LCD_DATA08 0x00000208 1370 #define IMX6SL_IOMUXC_SW_MUX_CTL_PAD_LCD_DATA09 0x0000020c 1371 #define IMX6SL_IOMUXC_SW_MUX_CTL_PAD_LCD_ENABLE 0x00000210 1372 #define IMX6SL_IOMUXC_SW_MUX_CTL_PAD_LCD_HSYNC 0x00000214 1373 #define IMX6SL_IOMUXC_SW_MUX_CTL_PAD_LCD_RESET 0x00000218 1374 #define IMX6SL_IOMUXC_SW_MUX_CTL_PAD_LCD_VSYNC 0x0000021c 1375 #define IMX6SL_IOMUXC_SW_MUX_CTL_PAD_PWM1 0x00000220 1376 #define IMX6SL_IOMUXC_SW_MUX_CTL_PAD_REF_CLK_24M 0x00000224 1377 #define IMX6SL_IOMUXC_SW_MUX_CTL_PAD_REF_CLK_32K 0x00000228 1378 #define IMX6SL_IOMUXC_SW_MUX_CTL_PAD_SD1_CLK 0x0000022c 1379 #define IMX6SL_IOMUXC_SW_MUX_CTL_PAD_SD1_CMD 0x00000230 1380 #define IMX6SL_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA0 0x00000234 1381 #define IMX6SL_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1 0x00000238 1382 #define IMX6SL_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA2 0x0000023c 1383 #define IMX6SL_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA3 0x00000240 1384 #define IMX6SL_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA4 0x00000244 1385 #define IMX6SL_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA5 0x00000248 1386 #define IMX6SL_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA6 0x0000024c 1387 #define IMX6SL_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA7 0x00000250 1388 #define IMX6SL_IOMUXC_SW_MUX_CTL_PAD_SD2_CLK 0x00000254 1389 #define IMX6SL_IOMUXC_SW_MUX_CTL_PAD_SD2_CMD 0x00000258 1390 #define IMX6SL_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA0 0x0000025c 1391 #define IMX6SL_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA1 0x00000260 1392 #define IMX6SL_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA2 0x00000264 1393 #define IMX6SL_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA3 0x00000268 1394 #define IMX6SL_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA4 0x0000026c 1395 #define IMX6SL_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA5 0x00000270 1396 #define IMX6SL_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA6 0x00000274 1397 #define IMX6SL_IOMUXC_SW_MUX_CTL_PAD_SD2_DATA7 0x00000278 1398 #define IMX6SL_IOMUXC_SW_MUX_CTL_PAD_SD2_RESET 0x0000027c 1399 #define IMX6SL_IOMUXC_SW_MUX_CTL_PAD_SD3_CLK 0x00000280 1400 #define IMX6SL_IOMUXC_SW_MUX_CTL_PAD_SD3_CMD 0x00000284 1401 #define IMX6SL_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0 0x00000288 1402 #define IMX6SL_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1 0x0000028c 1403 #define IMX6SL_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA2 0x00000290 1404 #define IMX6SL_IOMUXC_SW_MUX_CTL_PAD_SD3_DATA3 0x00000294 1405 #define IMX6SL_IOMUXC_SW_MUX_CTL_PAD_UART1_RXD 0x00000298 1406 #define IMX6SL_IOMUXC_SW_MUX_CTL_PAD_UART1_TXD 0x0000029c 1407 #define IMX6SL_IOMUXC_SW_MUX_CTL_PAD_WDOG_B 0x000002a0 1408 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_AUD_MCLK 0x000002a4 1409 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_AUD_RXC 0x000002a8 1410 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_AUD_RXD 0x000002ac 1411 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_AUD_RXFS 0x000002b0 1412 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_AUD_TXC 0x000002b4 1413 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_AUD_TXD 0x000002b8 1414 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_AUD_TXFS 0x000002bc 1415 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00 0x000002c0 1416 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01 0x000002c4 1417 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10 0x000002c8 1418 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11 0x000002cc 1419 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12 0x000002d0 1420 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13 0x000002d4 1421 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14 0x000002d8 1422 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15 0x000002dc 1423 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02 0x000002e0 1424 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03 0x000002e4 1425 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04 0x000002e8 1426 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05 0x000002ec 1427 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06 0x000002f0 1428 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07 0x000002f4 1429 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08 0x000002f8 1430 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09 0x000002fc 1431 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_B 0x00000300 1432 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_B 0x00000304 1433 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_B 0x00000308 1434 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0 0x0000030c 1435 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1 0x00000310 1436 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2 0x00000314 1437 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3 0x00000318 1438 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_B 0x0000031c 1439 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET 0x00000320 1440 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0 0x00000324 1441 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1 0x00000328 1442 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2 0x0000032c 1443 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0 0x00000330 1444 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1 0x00000334 1445 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P 0x00000338 1446 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0 0x0000033c 1447 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1 0x00000340 1448 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P 0x00000344 1449 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P 0x00000348 1450 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P 0x0000034c 1451 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P 0x00000350 1452 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_B 0x00000354 1453 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MISO 0x00000358 1454 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI 0x0000035c 1455 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK 0x00000360 1456 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SS0 0x00000364 1457 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_ECSPI2_MISO 0x00000368 1458 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_ECSPI2_MOSI 0x0000036c 1459 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_ECSPI2_SCLK 0x00000370 1460 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_ECSPI2_SS0 0x00000374 1461 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_EPDC_BDR0 0x00000378 1462 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_EPDC_BDR1 0x0000037c 1463 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA00 0x00000380 1464 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA01 0x00000384 1465 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA10 0x00000388 1466 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA11 0x0000038c 1467 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA12 0x00000390 1468 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA13 0x00000394 1469 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA14 0x00000398 1470 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA15 0x0000039c 1471 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA02 0x000003a0 1472 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA03 0x000003a4 1473 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA04 0x000003a8 1474 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA05 0x000003ac 1475 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA06 0x000003b0 1476 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA07 0x000003b4 1477 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA08 0x000003b8 1478 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA09 0x000003bc 1479 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_EPDC_GDCLK 0x000003c0 1480 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_EPDC_GDOE 0x000003c4 1481 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_EPDC_GDRL 0x000003c8 1482 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_EPDC_GDSP 0x000003cc 1483 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_EPDC_PWR_COM 0x000003d0 1484 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_EPDC_PWR_CTRL0 0x000003d4 1485 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_EPDC_PWR_CTRL1 0x000003d8 1486 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_EPDC_PWR_CTRL2 0x000003dc 1487 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_EPDC_PWR_CTRL3 0x000003e0 1488 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_EPDC_PWR_IRQ 0x000003e4 1489 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_EPDC_PWR_STAT 0x000003e8 1490 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_EPDC_PWR_WAKE 0x000003ec 1491 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE0 0x000003f0 1492 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE1 0x000003f4 1493 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE2 0x000003f8 1494 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE3 0x000003fc 1495 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCLK 0x00000400 1496 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_EPDC_SDLE 0x00000404 1497 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_EPDC_SDOE 0x00000408 1498 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_EPDC_SDSHR 0x0000040c 1499 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_EPDC_VCOM0 0x00000410 1500 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_EPDC_VCOM1 0x00000414 1501 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_FEC_CRS_DV 0x00000418 1502 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_FEC_MDC 0x0000041c 1503 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_FEC_MDIO 0x00000420 1504 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_FEC_REF_CLK 0x00000424 1505 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_FEC_RX_ER 0x00000428 1506 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_FEC_RX_DATA0 0x0000042c 1507 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_FEC_RX_DATA1 0x00000430 1508 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_FEC_TX_CLK 0x00000434 1509 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_FEC_TX_EN 0x00000438 1510 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_FEC_TX_DATA0 0x0000043c 1511 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_FEC_TX_DATA1 0x00000440 1512 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_USB_H_DATA 0x00000444 1513 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_USB_H_STROBE 0x00000448 1514 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_I2C1_SCL 0x0000044c 1515 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_I2C1_SDA 0x00000450 1516 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_I2C2_SCL 0x00000454 1517 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_I2C2_SDA 0x00000458 1518 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD 0x0000045c 1519 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK 0x00000460 1520 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI 0x00000464 1521 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO 0x00000468 1522 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS 0x0000046c 1523 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB 0x00000470 1524 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_KEY_COL0 0x00000474 1525 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_KEY_COL1 0x00000478 1526 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2 0x0000047c 1527 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_KEY_COL3 0x00000480 1528 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4 0x00000484 1529 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_KEY_COL5 0x00000488 1530 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_KEY_COL6 0x0000048c 1531 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_KEY_COL7 0x00000490 1532 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0 0x00000494 1533 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1 0x00000498 1534 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2 0x0000049c 1535 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3 0x000004a0 1536 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4 0x000004a4 1537 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW5 0x000004a8 1538 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW6 0x000004ac 1539 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW7 0x000004b0 1540 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_LCD_CLK 0x000004b4 1541 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_LCD_DATA00 0x000004b8 1542 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_LCD_DATA01 0x000004bc 1543 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_LCD_DATA10 0x000004c0 1544 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_LCD_DATA11 0x000004c4 1545 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_LCD_DATA12 0x000004c8 1546 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_LCD_DATA13 0x000004cc 1547 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_LCD_DATA14 0x000004d0 1548 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_LCD_DATA15 0x000004d4 1549 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_LCD_DATA16 0x000004d8 1550 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_LCD_DATA17 0x000004dc 1551 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_LCD_DATA18 0x000004e0 1552 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_LCD_DATA19 0x000004e4 1553 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_LCD_DATA02 0x000004e8 1554 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_LCD_DATA20 0x000004ec 1555 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_LCD_DATA21 0x000004f0 1556 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_LCD_DATA22 0x000004f4 1557 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_LCD_DATA23 0x000004f8 1558 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_LCD_DATA03 0x000004fc 1559 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_LCD_DATA04 0x00000500 1560 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_LCD_DATA05 0x00000504 1561 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_LCD_DATA06 0x00000508 1562 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_LCD_DATA07 0x0000050c 1563 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_LCD_DATA08 0x00000510 1564 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_LCD_DATA09 0x00000514 1565 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_LCD_ENABLE 0x00000518 1566 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_LCD_HSYNC 0x0000051c 1567 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_LCD_RESET 0x00000520 1568 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_LCD_VSYNC 0x00000524 1569 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_PWM1 0x00000528 1570 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_REF_CLK_24M 0x0000052c 1571 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_REF_CLK_32K 0x00000530 1572 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK 0x00000534 1573 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD 0x00000538 1574 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0 0x0000053c 1575 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1 0x00000540 1576 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2 0x00000544 1577 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3 0x00000548 1578 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA4 0x0000054c 1579 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA5 0x00000550 1580 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA6 0x00000554 1581 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA7 0x00000558 1582 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_SD2_CLK 0x0000055c 1583 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_SD2_CMD 0x00000560 1584 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0 0x00000564 1585 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1 0x00000568 1586 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2 0x0000056c 1587 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3 0x00000570 1588 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA4 0x00000574 1589 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA5 0x00000578 1590 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA6 0x0000057c 1591 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_SD2_DATA7 0x00000580 1592 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_SD2_RESET 0x00000584 1593 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_SD3_CLK 0x00000588 1594 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_SD3_CMD 0x0000058c 1595 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0 0x00000590 1596 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1 0x00000594 1597 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2 0x00000598 1598 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3 0x0000059c 1599 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_UART1_RXD 0x000005a0 1600 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_UART1_TXD 0x000005a4 1601 #define IMX6SL_IOMUXC_SW_PAD_CTL_PAD_WDOG_B 0x000005a8 1602 #define IMX6SL_IOMUXC_SW_PAD_CTL_GRP_ADDDS 0x000005ac 1603 #define IMX6SL_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL 0x000005b0 1604 #define IMX6SL_IOMUXC_SW_PAD_CTL_GRP_DDRPKE 0x000005b4 1605 #define IMX6SL_IOMUXC_SW_PAD_CTL_GRP_DDRPK 0x000005b8 1606 #define IMX6SL_IOMUXC_SW_PAD_CTL_GRP_DDRHYS 0x000005bc 1607 #define IMX6SL_IOMUXC_SW_PAD_CTL_GRP_DDRMODE 0x000005c0 1608 #define IMX6SL_IOMUXC_SW_PAD_CTL_GRP_B0DS 0x000005c4 1609 #define IMX6SL_IOMUXC_SW_PAD_CTL_GRP_CTLDS 0x000005c8 1610 #define IMX6SL_IOMUXC_SW_PAD_CTL_GRP_B1DS 0x000005cc 1611 #define IMX6SL_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE 0x000005d0 1612 #define IMX6SL_IOMUXC_SW_PAD_CTL_GRP_B2DS 0x000005d4 1613 #define IMX6SL_IOMUXC_SW_PAD_CTL_GRP_B3DS 0x000005d8 1614 #define IMX6SL_IOMUXC_ANALOG_USB_OTG_ID_SELECT_INPUT 0x000005dc 1615 #define IMX6SL_IOMUXC_ANALOG_USB_H1_ID_SELECT_INPUT 0x000005e0 1616 #define IMX6SL_IOMUXC_AUD4_INPUT_DA_AMX_SELECT_INPUT 0x000005e4 1617 #define IMX6SL_IOMUXC_AUD4_INPUT_DB_AMX_SELECT_INPUT 0x000005e8 1618 #define IMX6SL_IOMUXC_AUD4_INPUT_RXCLK_AMX_SELECT_INPUT 0x000005ec 1619 #define IMX6SL_IOMUXC_AUD4_INPUT_RXFS_AMX_SELECT_INPUT 0x000005f0 1620 #define IMX6SL_IOMUXC_AUD4_INPUT_TXCLK_AMX_SELECT_INPUT 0x000005f4 1621 #define IMX6SL_IOMUXC_AUD4_INPUT_TXFS_AMX_SELECT_INPUT 0x000005f8 1622 #define IMX6SL_IOMUXC_AUD5_INPUT_DA_AMX_SELECT_INPUT 0x000005fc 1623 #define IMX6SL_IOMUXC_AUD5_INPUT_DB_AMX_SELECT_INPUT 0x00000600 1624 #define IMX6SL_IOMUXC_AUD5_INPUT_RXCLK_AMX_SELECT_INPUT 0x00000604 1625 #define IMX6SL_IOMUXC_AUD5_INPUT_RXFS_AMX_SELECT_INPUT 0x00000608 1626 #define IMX6SL_IOMUXC_AUD5_INPUT_TXCLK_AMX_SELECT_INPUT 0x0000060c 1627 #define IMX6SL_IOMUXC_AUD5_INPUT_TXFS_AMX_SELECT_INPUT 0x00000610 1628 #define IMX6SL_IOMUXC_AUD6_INPUT_DA_AMX_SELECT_INPUT 0x00000614 1629 #define IMX6SL_IOMUXC_AUD6_INPUT_DB_AMX_SELECT_INPUT 0x00000618 1630 #define IMX6SL_IOMUXC_AUD6_INPUT_RXCLK_AMX_SELECT_INPUT 0x0000061c 1631 #define IMX6SL_IOMUXC_AUD6_INPUT_RXFS_AMX_SELECT_INPUT 0x00000620 1632 #define IMX6SL_IOMUXC_AUD6_INPUT_TXCLK_AMX_SELECT_INPUT 0x00000624 1633 #define IMX6SL_IOMUXC_AUD6_INPUT_TXFS_AMX_SELECT_INPUT 0x00000628 1634 #define IMX6SL_IOMUXC_CCM_PMIC_READY_SELECT_INPUT 0x0000062c 1635 #define IMX6SL_IOMUXC_CSI_CSI_DATA00_SELECT_INPUT 0x00000630 1636 #define IMX6SL_IOMUXC_CSI_CSI_DATA01_SELECT_INPUT 0x00000634 1637 #define IMX6SL_IOMUXC_CSI_CSI_DATA02_SELECT_INPUT 0x00000638 1638 #define IMX6SL_IOMUXC_CSI_CSI_DATA03_SELECT_INPUT 0x0000063c 1639 #define IMX6SL_IOMUXC_CSI_CSI_DATA04_SELECT_INPUT 0x00000640 1640 #define IMX6SL_IOMUXC_CSI_CSI_DATA05_SELECT_INPUT 0x00000644 1641 #define IMX6SL_IOMUXC_CSI_CSI_DATA06_SELECT_INPUT 0x00000648 1642 #define IMX6SL_IOMUXC_CSI_CSI_DATA07_SELECT_INPUT 0x0000064c 1643 #define IMX6SL_IOMUXC_CSI_CSI_DATA08_SELECT_INPUT 0x00000650 1644 #define IMX6SL_IOMUXC_CSI_CSI_DATA09_SELECT_INPUT 0x00000654 1645 #define IMX6SL_IOMUXC_CSI_CSI_DATA10_SELECT_INPUT 0x00000658 1646 #define IMX6SL_IOMUXC_CSI_CSI_DATA11_SELECT_INPUT 0x0000065c 1647 #define IMX6SL_IOMUXC_CSI_CSI_DATA12_SELECT_INPUT 0x00000660 1648 #define IMX6SL_IOMUXC_CSI_CSI_DATA13_SELECT_INPUT 0x00000664 1649 #define IMX6SL_IOMUXC_CSI_CSI_DATA14_SELECT_INPUT 0x00000668 1650 #define IMX6SL_IOMUXC_CSI_CSI_DATA15_SELECT_INPUT 0x0000066c 1651 #define IMX6SL_IOMUXC_CSI_CSI_HSYNC_SELECT_INPUT 0x00000670 1652 #define IMX6SL_IOMUXC_CSI_CSI_PIXCLK_SELECT_INPUT 0x00000674 1653 #define IMX6SL_IOMUXC_CSI_CSI_VSYNC_SELECT_INPUT 0x00000678 1654 #define IMX6SL_IOMUXC_ECSPI1_CSPI_CLK_IN_SELECT_INPUT 0x0000067c 1655 #define IMX6SL_IOMUXC_ECSPI1_DATAREADY_B_SELECT_INPUT 0x00000680 1656 #define IMX6SL_IOMUXC_ECSPI1_MISO_SELECT_INPUT 0x00000684 1657 #define IMX6SL_IOMUXC_ECSPI1_MOSI_SELECT_INPUT 0x00000688 1658 #define IMX6SL_IOMUXC_ECSPI1_SS0_SELECT_INPUT 0x0000068c 1659 #define IMX6SL_IOMUXC_ECSPI1_SS1_SELECT_INPUT 0x00000690 1660 #define IMX6SL_IOMUXC_ECSPI1_SS2_SELECT_INPUT 0x00000694 1661 #define IMX6SL_IOMUXC_ECSPI1_SS3_SELECT_INPUT 0x00000698 1662 #define IMX6SL_IOMUXC_ECSPI2_CSPI_CLK_IN_SELECT_INPUT 0x0000069c 1663 #define IMX6SL_IOMUXC_ECSPI2_MISO_SELECT_INPUT 0x000006a0 1664 #define IMX6SL_IOMUXC_ECSPI2_MOSI_SELECT_INPUT 0x000006a4 1665 #define IMX6SL_IOMUXC_ECSPI2_SS0_SELECT_INPUT 0x000006a8 1666 #define IMX6SL_IOMUXC_ECSPI2_SS1_SELECT_INPUT 0x000006ac 1667 #define IMX6SL_IOMUXC_ECSPI3_CSPI_CLK_IN_SELECT_INPUT 0x000006b0 1668 #define IMX6SL_IOMUXC_ECSPI3_DATAREADY_B_SELECT_INPUT 0x000006b4 1669 #define IMX6SL_IOMUXC_ECSPI3_MISO_SELECT_INPUT 0x000006b8 1670 #define IMX6SL_IOMUXC_ECSPI3_MOSI_SELECT_INPUT 0x000006bc 1671 #define IMX6SL_IOMUXC_ECSPI3_SS0_SELECT_INPUT 0x000006c0 1672 #define IMX6SL_IOMUXC_ECSPI3_SS1_SELECT_INPUT 0x000006c4 1673 #define IMX6SL_IOMUXC_ECSPI3_SS2_SELECT_INPUT 0x000006c8 1674 #define IMX6SL_IOMUXC_ECSPI3_SS3_SELECT_INPUT 0x000006cc 1675 #define IMX6SL_IOMUXC_ECSPI4_CSPI_CLK_IN_SELECT_INPUT 0x000006d0 1676 #define IMX6SL_IOMUXC_ECSPI4_MISO_SELECT_INPUT 0x000006d4 1677 #define IMX6SL_IOMUXC_ECSPI4_MOSI_SELECT_INPUT 0x000006d8 1678 #define IMX6SL_IOMUXC_ECSPI4_SS0_SELECT_INPUT 0x000006dc 1679 #define IMX6SL_IOMUXC_ECSPI4_SS1_SELECT_INPUT 0x000006e0 1680 #define IMX6SL_IOMUXC_ECSPI4_SS2_SELECT_INPUT 0x000006e4 1681 #define IMX6SL_IOMUXC_EPDC_EPDC_PWR_IRQ_SELECT_INPUT 0x000006e8 1682 #define IMX6SL_IOMUXC_EPDC_EPDC_PWR_STAT_SELECT_INPUT 0x000006ec 1683 #define IMX6SL_IOMUXC_FEC_FEC_COL_SELECT_INPUT 0x000006f0 1684 #define IMX6SL_IOMUXC_FEC_FEC_MDI_SELECT_INPUT 0x000006f4 1685 #define IMX6SL_IOMUXC_FEC_FEC_RX_DATA0_SELECT_INPUT 0x000006f8 1686 #define IMX6SL_IOMUXC_FEC_FEC_RX_DATA1_SELECT_INPUT 0x000006fc 1687 #define IMX6SL_IOMUXC_FEC_FEC_RX_CLK_SELECT_INPUT 0x00000700 1688 #define IMX6SL_IOMUXC_FEC_FEC_RX_DV_SELECT_INPUT 0x00000704 1689 #define IMX6SL_IOMUXC_FEC_FEC_RX_ER_SELECT_INPUT 0x00000708 1690 #define IMX6SL_IOMUXC_FEC_FEC_TX_CLK_SELECT_INPUT 0x0000070c 1691 #define IMX6SL_IOMUXC_GPT_CAPIN1_SELECT_INPUT 0x00000710 1692 #define IMX6SL_IOMUXC_GPT_CAPIN2_SELECT_INPUT 0x00000714 1693 #define IMX6SL_IOMUXC_GPT_CLKIN_SELECT_INPUT 0x00000718 1694 #define IMX6SL_IOMUXC_I2C1_SCL_IN_SELECT_INPUT 0x0000071c 1695 #define IMX6SL_IOMUXC_I2C1_SDA_IN_SELECT_INPUT 0x00000720 1696 #define IMX6SL_IOMUXC_I2C2_SCL_IN_SELECT_INPUT 0x00000724 1697 #define IMX6SL_IOMUXC_I2C2_SDA_IN_SELECT_INPUT 0x00000728 1698 #define IMX6SL_IOMUXC_I2C3_SCL_IN_SELECT_INPUT 0x0000072c 1699 #define IMX6SL_IOMUXC_I2C3_SDA_IN_SELECT_INPUT 0x00000730 1700 #define IMX6SL_IOMUXC_KEY_COL0_SELECT_INPUT 0x00000734 1701 #define IMX6SL_IOMUXC_KEY_COL1_SELECT_INPUT 0x00000738 1702 #define IMX6SL_IOMUXC_KEY_COL2_SELECT_INPUT 0x0000073c 1703 #define IMX6SL_IOMUXC_KEY_COL3_SELECT_INPUT 0x00000740 1704 #define IMX6SL_IOMUXC_KEY_COL4_SELECT_INPUT 0x00000744 1705 #define IMX6SL_IOMUXC_KEY_COL5_SELECT_INPUT 0x00000748 1706 #define IMX6SL_IOMUXC_KEY_COL6_SELECT_INPUT 0x0000074c 1707 #define IMX6SL_IOMUXC_KEY_COL7_SELECT_INPUT 0x00000750 1708 #define IMX6SL_IOMUXC_KEY_ROW0_SELECT_INPUT 0x00000754 1709 #define IMX6SL_IOMUXC_KEY_ROW1_SELECT_INPUT 0x00000758 1710 #define IMX6SL_IOMUXC_KEY_ROW2_SELECT_INPUT 0x0000075c 1711 #define IMX6SL_IOMUXC_KEY_ROW3_SELECT_INPUT 0x00000760 1712 #define IMX6SL_IOMUXC_KEY_ROW4_SELECT_INPUT 0x00000764 1713 #define IMX6SL_IOMUXC_KEY_ROW5_SELECT_INPUT 0x00000768 1714 #define IMX6SL_IOMUXC_KEY_ROW6_SELECT_INPUT 0x0000076c 1715 #define IMX6SL_IOMUXC_KEY_ROW7_SELECT_INPUT 0x00000770 1716 #define IMX6SL_IOMUXC_LCD_BUSY_SELECT_INPUT 0x00000774 1717 #define IMX6SL_IOMUXC_LCD_DATA00_SELECT_INPUT 0x00000778 1718 #define IMX6SL_IOMUXC_LCD_DATA01_SELECT_INPUT 0x0000077c 1719 #define IMX6SL_IOMUXC_LCD_DATA02_SELECT_INPUT 0x00000780 1720 #define IMX6SL_IOMUXC_LCD_DATA03_SELECT_INPUT 0x00000784 1721 #define IMX6SL_IOMUXC_LCD_DATA04_SELECT_INPUT 0x00000788 1722 #define IMX6SL_IOMUXC_LCD_DATA05_SELECT_INPUT 0x0000078c 1723 #define IMX6SL_IOMUXC_LCD_DATA06_SELECT_INPUT 0x00000790 1724 #define IMX6SL_IOMUXC_LCD_DATA07_SELECT_INPUT 0x00000794 1725 #define IMX6SL_IOMUXC_LCD_DATA08_SELECT_INPUT 0x00000798 1726 #define IMX6SL_IOMUXC_LCD_DATA09_SELECT_INPUT 0x0000079c 1727 #define IMX6SL_IOMUXC_LCD_DATA10_SELECT_INPUT 0x000007a0 1728 #define IMX6SL_IOMUXC_LCD_DATA11_SELECT_INPUT 0x000007a4 1729 #define IMX6SL_IOMUXC_LCD_DATA12_SELECT_INPUT 0x000007a8 1730 #define IMX6SL_IOMUXC_LCD_DATA13_SELECT_INPUT 0x000007ac 1731 #define IMX6SL_IOMUXC_LCD_DATA14_SELECT_INPUT 0x000007b0 1732 #define IMX6SL_IOMUXC_LCD_DATA15_SELECT_INPUT 0x000007b4 1733 #define IMX6SL_IOMUXC_LCD_DATA16_SELECT_INPUT 0x000007b8 1734 #define IMX6SL_IOMUXC_LCD_DATA17_SELECT_INPUT 0x000007bc 1735 #define IMX6SL_IOMUXC_LCD_DATA18_SELECT_INPUT 0x000007c0 1736 #define IMX6SL_IOMUXC_LCD_DATA19_SELECT_INPUT 0x000007c4 1737 #define IMX6SL_IOMUXC_LCD_DATA20_SELECT_INPUT 0x000007c8 1738 #define IMX6SL_IOMUXC_LCD_DATA21_SELECT_INPUT 0x000007cc 1739 #define IMX6SL_IOMUXC_LCD_DATA22_SELECT_INPUT 0x000007d0 1740 #define IMX6SL_IOMUXC_LCD_DATA23_SELECT_INPUT 0x000007d4 1741 #define IMX6SL_IOMUXC_SPDIF_SPDIF_IN1_SELECT_INPUT 0x000007f0 1742 #define IMX6SL_IOMUXC_SPDIF_TX_CLK2_SELECT_INPUT 0x000007f4 1743 #define IMX6SL_IOMUXC_UART1_UART_RTS_B_SELECT_INPUT 0x000007f8 1744 #define IMX6SL_IOMUXC_UART1_UART_RX_DATA_SELECT_INPUT 0x000007fc 1745 #define IMX6SL_IOMUXC_UART2_UART_RTS_B_SELECT_INPUT 0x00000800 1746 #define IMX6SL_IOMUXC_UART2_UART_RX_DATA_SELECT_INPUT 0x00000804 1747 #define IMX6SL_IOMUXC_UART3_UART_RTS_B_SELECT_INPUT 0x00000808 1748 #define IMX6SL_IOMUXC_UART3_UART_RX_DATA_SELECT_INPUT 0x0000080c 1749 #define IMX6SL_IOMUXC_UART4_UART_RTS_B_SELECT_INPUT 0x00000810 1750 #define IMX6SL_IOMUXC_UART4_UART_RX_DATA_SELECT_INPUT 0x00000814 1751 #define IMX6SL_IOMUXC_UART5_UART_RTS_B_SELECT_INPUT 0x00000818 1752 #define IMX6SL_IOMUXC_UART5_UART_RX_DATA_SELECT_INPUT 0x0000081c 1753 #define IMX6SL_IOMUXC_USB_OTG2_OC_SELECT_INPUT 0x00000820 1754 #define IMX6SL_IOMUXC_USB_OTG1_OC_SELECT_INPUT 0x00000824 1755 #define IMX6SL_IOMUXC_USDHC1_CARD_DET_SELECT_INPUT 0x00000828 1756 #define IMX6SL_IOMUXC_USDHC1_WP_ON_SELECT_INPUT 0x0000082c 1757 #define IMX6SL_IOMUXC_USDHC2_CARD_DET_SELECT_INPUT 0x00000830 1758 #define IMX6SL_IOMUXC_USDHC2_WP_ON_SELECT_INPUT 0x00000834 1759 #define IMX6SL_IOMUXC_USDHC3_CARD_DET_SELECT_INPUT 0x00000838 1760 #define IMX6SL_IOMUXC_USDHC3_DATA4_IN_SELECT_INPUT 0x0000083c 1761 #define IMX6SL_IOMUXC_USDHC3_DATA5_IN_SELECT_INPUT 0x00000840 1762 #define IMX6SL_IOMUXC_USDHC3_DATA6_IN_SELECT_INPUT 0x00000844 1763 #define IMX6SL_IOMUXC_USDHC3_DATA7_IN_SELECT_INPUT 0x00000848 1764 #define IMX6SL_IOMUXC_USDHC3_WP_ON_SELECT_INPUT 0x0000084c 1765 #define IMX6SL_IOMUXC_USDHC4_CARD_CLK_IN_SELECT_INPUT 0x00000850 1766 #define IMX6SL_IOMUXC_USDHC4_CARD_DET_SELECT_INPUT 0x00000854 1767 #define IMX6SL_IOMUXC_USDHC4_CMD_IN_SELECT_INPUT 0x00000858 1768 #define IMX6SL_IOMUXC_USDHC4_DATA0_IN_SELECT_INPUT 0x0000085c 1769 #define IMX6SL_IOMUXC_USDHC4_DATA1_IN_SELECT_INPUT 0x00000860 1770 #define IMX6SL_IOMUXC_USDHC4_DATA2_IN_SELECT_INPUT 0x00000864 1771 #define IMX6SL_IOMUXC_USDHC4_DATA3_IN_SELECT_INPUT 0x00000868 1772 #define IMX6SL_IOMUXC_USDHC4_DATA4_IN_SELECT_INPUT 0x0000086c 1773 #define IMX6SL_IOMUXC_USDHC4_DATA5_IN_SELECT_INPUT 0x00000870 1774 #define IMX6SL_IOMUXC_USDHC4_DATA6_IN_SELECT_INPUT 0x00000874 1775 #define IMX6SL_IOMUXC_USDHC4_DATA7_IN_SELECT_INPUT 0x00000878 1776 #define IMX6SL_IOMUXC_USDHC4_WP_ON_SELECT_INPUT 0x0000087c 1777 #define IMX6SL_IOMUXC_EIM_DTACK_B_SELECT_INPUT 0x00000880 1778 #define IMX6SL_IOMUXC_EIM_WAIT_B_SELECT_INPUT 0x00000884 1779 1780 /* for iMX6UltraLight */ 1781 #define IMX6UL_IOMUX_GPR0 0x00004000 1782 #define IMX6UL_IOMUX_GPR1 0x00004004 1783 #define IMX6UL_IOMUX_GPR1_ARMA7_CLK_AHB_EN __BIT(26) 1784 #define IMX6UL_IOMUX_GPR1_ARMA7_CLK_ATB_EN __BIT(25) 1785 #define IMX6UL_IOMUX_GPR1_ARMA7_CLK_APB_DBG_EN __BIT(24) 1786 #define IMX6UL_IOMUX_GPR1_TZASC1_BOOT_LOCK __BIT(23) 1787 #define IMX6UL_IOMUX_GPR1_EXC_MON __BIT(22) 1788 #define IMX6UL_IOMUX_GPR1_SAI3_MCLK_DIR __BIT(21) 1789 #define IMX6UL_IOMUX_GPR1_SAI2_MCLK_DIR __BIT(20) 1790 #define IMX6UL_IOMUX_GPR1_SAI1_MCLK_DIR __BIT(19) 1791 #define IMX6UL_IOMUX_GPR1_ENET2_TX_CLK_DIR __BIT(18) 1792 #define IMX6UL_IOMUX_GPR1_ENET1_TX_CLK_DIR __BIT(17) 1793 #define IMX6UL_IOMUX_GPR1_ADD_DS __BIT(16) 1794 #define IMX6UL_IOMUX_GPR1_USB_EXP_MODE __BIT(15) 1795 #define IMX6UL_IOMUX_GPR1_ENET2_CLK_SEL __BIT(14) 1796 #define IMX6UL_IOMUX_GPR1_ENET1_CLK_SEL __BIT(13) 1797 #define IMX6UL_IOMUX_GPR1_GINT __BIT(12) 1798 #define IMX6UL_IOMUX_GPR2 0x00004008 1799 #define IMX6UL_IOMUX_GPR3 0x0000400c 1800 #define IMX6UL_IOMUX_GPR4 0x00004010 1801 #define IMX6UL_IOMUX_GPR5 0x00004014 1802 #define IMX6UL_IOMUX_GPR9 0x00004024 1803 #define IMX6UL_IOMUX_GPR10 0x00004028 1804 #define IMX6UL_IOMUX_GPR14 0x00004038 1805 #define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_BOOT_MODE0 0x00000014 1806 #define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_BOOT_MODE1 0x00000018 1807 #define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_SNVS_TAMPER0 0x0000001c 1808 #define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_SNVS_TAMPER1 0x00000020 1809 #define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_SNVS_TAMPER2 0x00000024 1810 #define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_SNVS_TAMPER3 0x00000028 1811 #define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_SNVS_TAMPER4 0x0000002c 1812 #define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_SNVS_TAMPER5 0x00000030 1813 #define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_SNVS_TAMPER6 0x00000034 1814 #define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_SNVS_TAMPER7 0x00000038 1815 #define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_SNVS_TAMPER8 0x0000003c 1816 #define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_SNVS_TAMPER9 0x00000040 1817 #define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_JTAG_MOD 0x00000044 1818 #define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_JTAG_TMS 0x00000048 1819 #define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_JTAG_TDO 0x0000004c 1820 #define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_JTAG_TDI 0x00000050 1821 #define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_JTAG_TCK 0x00000054 1822 #define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_JTAG_TRST_B 0x00000058 1823 #define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO00 0x0000005c 1824 #define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO01 0x00000060 1825 #define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO02 0x00000064 1826 #define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO03 0x00000068 1827 #define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO04 0x0000006c 1828 #define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO05 0x00000070 1829 #define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO06 0x00000074 1830 #define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO07 0x00000078 1831 #define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO08 0x0000007c 1832 #define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO09 0x00000080 1833 #define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_UART1_TX_DATA 0x00000084 1834 #define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_UART1_RX_DATA 0x00000088 1835 #define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_UART1_CTS_B 0x0000008c 1836 #define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_UART1_RTS_B 0x00000090 1837 #define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_UART2_TX_DATA 0x00000094 1838 #define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_UART2_RX_DATA 0x00000098 1839 #define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_UART2_CTS_B 0x0000009c 1840 #define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_UART2_RTS_B 0x000000a0 1841 #define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_UART3_TX_DATA 0x000000a4 1842 #define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_UART3_RX_DATA 0x000000a8 1843 #define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_UART3_CTS_B 0x000000ac 1844 #define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_UART3_RTS_B 0x000000b0 1845 #define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_UART4_TX_DATA 0x000000b4 1846 #define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_UART4_RX_DATA 0x000000b8 1847 #define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_UART5_TX_DATA 0x000000bc 1848 #define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_UART5_RX_DATA 0x000000c0 1849 #define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_ENET1_RX_DATA0 0x000000c4 1850 #define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_ENET1_RX_DATA1 0x000000c8 1851 #define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_ENET1_RX_EN 0x000000cc 1852 #define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_ENET1_TX_DATA0 0x000000d0 1853 #define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_ENET1_TX_DATA1 0x000000d4 1854 #define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_ENET1_TX_EN 0x000000d8 1855 #define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_ENET1_TX_CLK 0x000000dc 1856 #define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_ENET1_RX_ER 0x000000e0 1857 #define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_ENET2_RX_DATA0 0x000000e4 1858 #define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_ENET2_RX_DATA1 0x000000e8 1859 #define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_ENET2_RX_EN 0x000000ec 1860 #define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_ENET2_TX_DATA0 0x000000f0 1861 #define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_ENET2_TX_DATA1 0x000000f4 1862 #define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_ENET2_TX_EN 0x000000f8 1863 #define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_ENET2_TX_CLK 0x000000fc 1864 #define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_ENET2_RX_ER 0x00000100 1865 #define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_LCD_CLK 0x00000104 1866 #define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_LCD_ENABLE 0x00000108 1867 #define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_LCD_HSYNC 0x0000010c 1868 #define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_LCD_VSYNC 0x00000110 1869 #define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_LCD_RESET 0x00000114 1870 #define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_LCD_DATA00 0x00000118 1871 #define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_LCD_DATA01 0x0000011c 1872 #define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_LCD_DATA02 0x00000120 1873 #define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_LCD_DATA03 0x00000124 1874 #define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_LCD_DATA04 0x00000128 1875 #define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_LCD_DATA05 0x0000012c 1876 #define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_LCD_DATA06 0x00000130 1877 #define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_LCD_DATA07 0x00000134 1878 #define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_LCD_DATA08 0x00000138 1879 #define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_LCD_DATA09 0x0000013c 1880 #define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_LCD_DATA10 0x00000140 1881 #define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_LCD_DATA11 0x00000144 1882 #define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_LCD_DATA12 0x00000148 1883 #define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_LCD_DATA13 0x0000014c 1884 #define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_LCD_DATA14 0x00000150 1885 #define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_LCD_DATA15 0x00000154 1886 #define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_LCD_DATA16 0x00000158 1887 #define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_LCD_DATA17 0x0000015c 1888 #define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_LCD_DATA18 0x00000160 1889 #define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_LCD_DATA19 0x00000164 1890 #define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_LCD_DATA20 0x00000168 1891 #define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_LCD_DATA21 0x0000016c 1892 #define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_LCD_DATA22 0x00000170 1893 #define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_LCD_DATA23 0x00000174 1894 #define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_NAND_RE_B 0x00000178 1895 #define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_NAND_WE_B 0x0000017c 1896 #define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00 0x00000180 1897 #define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01 0x00000184 1898 #define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02 0x00000188 1899 #define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03 0x0000018c 1900 #define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA04 0x00000190 1901 #define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05 0x00000194 1902 #define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06 0x00000198 1903 #define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07 0x0000019c 1904 #define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_NAND_ALE 0x000001a0 1905 #define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B 0x000001a4 1906 #define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_NAND_READY_B 0x000001a8 1907 #define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_NAND_CE0_B 0x000001ac 1908 #define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_NAND_CE1_B 0x000001b0 1909 #define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_NAND_CLE 0x000001b4 1910 #define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_NAND_DQS 0x000001b8 1911 #define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_SD1_CMD 0x000001bc 1912 #define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_SD1_CLK 0x000001c0 1913 #define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA0 0x000001c4 1914 #define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1 0x000001c8 1915 #define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA2 0x000001cc 1916 #define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_SD1_DATA3 0x000001d0 1917 #define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_CSI_MCLK 0x000001d4 1918 #define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_CSI_PIXCLK 0x000001d8 1919 #define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_CSI_VSYNC 0x000001dc 1920 #define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_CSI_HSYNC 0x000001e0 1921 #define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_CSI_DATA00 0x000001e4 1922 #define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_CSI_DATA01 0x000001e8 1923 #define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_CSI_DATA02 0x000001ec 1924 #define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_CSI_DATA03 0x000001f0 1925 #define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_CSI_DATA04 0x000001f4 1926 #define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_CSI_DATA05 0x000001f8 1927 #define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_CSI_DATA06 0x000001fc 1928 #define IMX6UL_IOMUXC_SW_MUX_CTL_PAD_CSI_DATA07 0x00000200 1929 #define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00 0x00000204 1930 #define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01 0x00000208 1931 #define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02 0x0000020c 1932 #define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03 0x00000210 1933 #define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04 0x00000214 1934 #define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05 0x00000218 1935 #define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06 0x0000021c 1936 #define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07 0x00000220 1937 #define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08 0x00000224 1938 #define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09 0x00000228 1939 #define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10 0x0000022c 1940 #define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11 0x00000230 1941 #define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12 0x00000234 1942 #define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13 0x00000238 1943 #define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14 0x0000023c 1944 #define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15 0x00000240 1945 #define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0 0x00000244 1946 #define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1 0x00000248 1947 #define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_B 0x0000024c 1948 #define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_B 0x00000250 1949 #define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_B 0x00000254 1950 #define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_B 0x00000258 1951 #define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_B 0x0000025c 1952 #define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0 0x00000260 1953 #define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1 0x00000264 1954 #define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0 0x00000268 1955 #define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1 0x0000026c 1956 #define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2 0x00000270 1957 #define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0 0x00000274 1958 #define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1 0x00000278 1959 #define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P 0x0000027c 1960 #define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P 0x00000280 1961 #define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P 0x00000284 1962 #define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET 0x00000288 1963 #define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_TEST_MODE 0x0000028c 1964 #define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_POR_B 0x00000290 1965 #define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_ONOFF 0x00000294 1966 #define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_SNVS_PMIC_ON_REQ 0x00000298 1967 #define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_CCM_PMIC_STBY_REQ 0x0000029c 1968 #define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_BOOT_MODE0 0x000002a0 1969 #define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_BOOT_MODE1 0x000002a4 1970 #define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_SNVS_TAMPER0 0x000002a8 1971 #define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_SNVS_TAMPER1 0x000002ac 1972 #define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_SNVS_TAMPER2 0x000002b0 1973 #define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_SNVS_TAMPER3 0x000002b4 1974 #define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_SNVS_TAMPER4 0x000002b8 1975 #define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_SNVS_TAMPER5 0x000002bc 1976 #define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_SNVS_TAMPER6 0x000002c0 1977 #define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_SNVS_TAMPER7 0x000002c4 1978 #define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_SNVS_TAMPER8 0x000002c8 1979 #define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_SNVS_TAMPER9 0x000002cc 1980 #define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD 0x000002d0 1981 #define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS 0x000002d4 1982 #define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO 0x000002d8 1983 #define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI 0x000002dc 1984 #define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK 0x000002e0 1985 #define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_JTAG_TRST_B 0x000002e4 1986 #define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO00 0x000002e8 1987 #define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO01 0x000002ec 1988 #define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO02 0x000002f0 1989 #define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO03 0x000002f4 1990 #define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO04 0x000002f8 1991 #define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO05 0x000002fc 1992 #define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO06 0x00000300 1993 #define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO07 0x00000304 1994 #define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO08 0x00000308 1995 #define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO09 0x0000030c 1996 #define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_UART1_TX_DATA 0x00000310 1997 #define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_UART1_RX_DATA 0x00000314 1998 #define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_UART1_CTS_B 0x00000318 1999 #define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_UART1_RTS_B 0x0000031c 2000 #define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_UART2_TX_DATA 0x00000320 2001 #define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_UART2_RX_DATA 0x00000324 2002 #define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_UART2_CTS_B 0x00000328 2003 #define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_UART2_RTS_B 0x0000032c 2004 #define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_UART3_TX_DATA 0x00000330 2005 #define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_UART3_RX_DATA 0x00000334 2006 #define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_UART3_CTS_B 0x00000338 2007 #define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_UART3_RTS_B 0x0000033c 2008 #define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_UART4_TX_DATA 0x00000340 2009 #define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_UART4_RX_DATA 0x00000344 2010 #define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_UART5_TX_DATA 0x00000348 2011 #define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_UART5_RX_DATA 0x0000034c 2012 #define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_ENET1_RX_DATA0 0x00000350 2013 #define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_ENET1_RX_DATA1 0x00000354 2014 #define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_ENET1_RX_EN 0x00000358 2015 #define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_ENET1_TX_DATA0 0x0000035c 2016 #define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_ENET1_TX_DATA1 0x00000360 2017 #define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_ENET1_TX_EN 0x00000364 2018 #define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_ENET1_TX_CLK 0x00000368 2019 #define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_ENET1_RX_ER 0x0000036c 2020 #define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_ENET2_RX_DATA0 0x00000370 2021 #define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_ENET2_RX_DATA1 0x00000374 2022 #define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_ENET2_RX_EN 0x00000378 2023 #define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_ENET2_TX_DATA0 0x0000037c 2024 #define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_ENET2_TX_DATA1 0x00000380 2025 #define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_ENET2_TX_EN 0x00000384 2026 #define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_ENET2_TX_CLK 0x00000388 2027 #define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_ENET2_RX_ER 0x0000038c 2028 #define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_LCD_CLK 0x00000390 2029 #define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_LCD_ENABLE 0x00000394 2030 #define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_LCD_HSYNC 0x00000398 2031 #define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_LCD_VSYNC 0x0000039c 2032 #define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_LCD_RESET 0x000003a0 2033 #define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_LCD_DATA00 0x000003a4 2034 #define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_LCD_DATA01 0x000003a8 2035 #define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_LCD_DATA02 0x000003ac 2036 #define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_LCD_DATA03 0x000003b0 2037 #define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_LCD_DATA04 0x000003b4 2038 #define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_LCD_DATA05 0x000003b8 2039 #define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_LCD_DATA06 0x000003bc 2040 #define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_LCD_DATA07 0x000003c0 2041 #define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_LCD_DATA08 0x000003c4 2042 #define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_LCD_DATA09 0x000003c8 2043 #define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_LCD_DATA10 0x000003cc 2044 #define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_LCD_DATA11 0x000003d0 2045 #define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_LCD_DATA12 0x000003d4 2046 #define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_LCD_DATA13 0x000003d8 2047 #define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_LCD_DATA14 0x000003dc 2048 #define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_LCD_DATA15 0x000003e0 2049 #define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_LCD_DATA16 0x000003e4 2050 #define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_LCD_DATA17 0x000003e8 2051 #define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_LCD_DATA18 0x000003ec 2052 #define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_LCD_DATA19 0x000003f0 2053 #define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_LCD_DATA20 0x000003f4 2054 #define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_LCD_DATA21 0x000003f8 2055 #define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_LCD_DATA22 0x000003fc 2056 #define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_LCD_DATA23 0x00000400 2057 #define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_NAND_RE_B 0x00000404 2058 #define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_NAND_WE_B 0x00000408 2059 #define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00 0x0000040c 2060 #define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01 0x00000410 2061 #define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02 0x00000414 2062 #define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03 0x00000418 2063 #define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04 0x0000041c 2064 #define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05 0x00000420 2065 #define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06 0x00000424 2066 #define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07 0x00000428 2067 #define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_NAND_ALE 0x0000042c 2068 #define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B 0x00000430 2069 #define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_NAND_READY_B 0x00000434 2070 #define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_NAND_CE0_B 0x00000438 2071 #define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_NAND_CE1_B 0x0000043c 2072 #define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_NAND_CLE 0x00000440 2073 #define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_NAND_DQS 0x00000444 2074 #define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_SD1_CMD 0x00000448 2075 #define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_SD1_CLK 0x0000044c 2076 #define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0 0x00000450 2077 #define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1 0x00000454 2078 #define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2 0x00000458 2079 #define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3 0x0000045c 2080 #define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_CSI_MCLK 0x00000460 2081 #define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_CSI_PIXCLK 0x00000464 2082 #define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_CSI_VSYNC 0x00000468 2083 #define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_CSI_HSYNC 0x0000046c 2084 #define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_CSI_DATA00 0x00000470 2085 #define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_CSI_DATA01 0x00000474 2086 #define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_CSI_DATA02 0x00000478 2087 #define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_CSI_DATA03 0x0000047c 2088 #define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_CSI_DATA04 0x00000480 2089 #define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_CSI_DATA05 0x00000484 2090 #define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_CSI_DATA06 0x00000488 2091 #define IMX6UL_IOMUXC_SW_PAD_CTL_PAD_CSI_DATA07 0x0000048c 2092 #define IMX6UL_IOMUXC_SW_PAD_CTL_GRP_ADDDS 0x00000490 2093 #define IMX6UL_IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL 0x00000494 2094 #define IMX6UL_IOMUXC_SW_PAD_CTL_GRP_B0DS 0x00000498 2095 #define IMX6UL_IOMUXC_SW_PAD_CTL_GRP_DDRPK 0x0000049c 2096 #define IMX6UL_IOMUXC_SW_PAD_CTL_GRP_CTLDS 0x000004a0 2097 #define IMX6UL_IOMUXC_SW_PAD_CTL_GRP_B1DS 0x000004a4 2098 #define IMX6UL_IOMUXC_SW_PAD_CTL_GRP_DDRHYS 0x000004a8 2099 #define IMX6UL_IOMUXC_SW_PAD_CTL_GRP_DDRPKE 0x000004ac 2100 #define IMX6UL_IOMUXC_SW_PAD_CTL_GRP_DDRMODE 0x000004b0 2101 #define IMX6UL_IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE 0x000004b4 2102 #define IMX6UL_IOMUXC_USB_OTG1_ID_SELECT_INPUT 0x000004b8 2103 #define IMX6UL_IOMUXC_USB_OTG2_ID_SELECT_INPUT 0x000004bc 2104 #define IMX6UL_IOMUXC_CCM_PMIC_READY_SELECT_INPUT 0x000004c0 2105 #define IMX6UL_IOMUXC_CSI_DATA02_SELECT_INPUT 0x000004c4 2106 #define IMX6UL_IOMUXC_CSI_DATA03_SELECT_INPUT 0x000004c8 2107 #define IMX6UL_IOMUXC_CSI_DATA05_SELECT_INPUT 0x000004cc 2108 #define IMX6UL_IOMUXC_CSI_DATA00_SELECT_INPUT 0x000004d0 2109 #define IMX6UL_IOMUXC_CSI_DATA01_SELECT_INPUT 0x000004d4 2110 #define IMX6UL_IOMUXC_CSI_DATA04_SELECT_INPUT 0x000004d8 2111 #define IMX6UL_IOMUXC_CSI_DATA06_SELECT_INPUT 0x000004dc 2112 #define IMX6UL_IOMUXC_CSI_DATA07_SELECT_INPUT 0x000004e0 2113 #define IMX6UL_IOMUXC_CSI_DATA08_SELECT_INPUT 0x000004e4 2114 #define IMX6UL_IOMUXC_CSI_DATA09_SELECT_INPUT 0x000004e8 2115 #define IMX6UL_IOMUXC_CSI_DATA10_SELECT_INPUT 0x000004ec 2116 #define IMX6UL_IOMUXC_CSI_DATA11_SELECT_INPUT 0x000004f0 2117 #define IMX6UL_IOMUXC_CSI_DATA12_SELECT_INPUT 0x000004f4 2118 #define IMX6UL_IOMUXC_CSI_DATA13_SELECT_INPUT 0x000004f8 2119 #define IMX6UL_IOMUXC_CSI_DATA14_SELECT_INPUT 0x000004fc 2120 #define IMX6UL_IOMUXC_CSI_DATA15_SELECT_INPUT 0x00000500 2121 #define IMX6UL_IOMUXC_CSI_DATA16_SELECT_INPUT 0x00000504 2122 #define IMX6UL_IOMUXC_CSI_DATA17_SELECT_INPUT 0x00000508 2123 #define IMX6UL_IOMUXC_CSI_DATA18_SELECT_INPUT 0x0000050c 2124 #define IMX6UL_IOMUXC_CSI_DATA19_SELECT_INPUT 0x00000510 2125 #define IMX6UL_IOMUXC_CSI_DATA20_SELECT_INPUT 0x00000514 2126 #define IMX6UL_IOMUXC_CSI_DATA21_SELECT_INPUT 0x00000518 2127 #define IMX6UL_IOMUXC_CSI_DATA22_SELECT_INPUT 0x0000051c 2128 #define IMX6UL_IOMUXC_CSI_DATA23_SELECT_INPUT 0x00000520 2129 #define IMX6UL_IOMUXC_CSI_HSYNC_SELECT_INPUT 0x00000524 2130 #define IMX6UL_IOMUXC_CSI_PIXCLK_SELECT_INPUT 0x00000528 2131 #define IMX6UL_IOMUXC_CSI_VSYNC_SELECT_INPUT 0x0000052c 2132 #define IMX6UL_IOMUXC_CSI_FIELD_SELECT_INPUT 0x00000530 2133 #define IMX6UL_IOMUXC_ECSPI1_SCLK_SELECT_INPUT 0x00000534 2134 #define IMX6UL_IOMUXC_ECSPI1_MISO_SELECT_INPUT 0x00000538 2135 #define IMX6UL_IOMUXC_ECSPI1_MOSI_SELECT_INPUT 0x0000053c 2136 #define IMX6UL_IOMUXC_ECSPI1_SS0_B_SELECT_INPUT 0x00000540 2137 #define IMX6UL_IOMUXC_ECSPI2_SCLK_SELECT_INPUT 0x00000544 2138 #define IMX6UL_IOMUXC_ECSPI2_MISO_SELECT_INPUT 0x00000548 2139 #define IMX6UL_IOMUXC_ECSPI2_MOSI_SELECT_INPUT 0x0000054c 2140 #define IMX6UL_IOMUXC_ECSPI2_SS0_B_SELECT_INPUT 0x00000550 2141 #define IMX6UL_IOMUXC_ECSPI3_SCLK_SELECT_INPUT 0x00000554 2142 #define IMX6UL_IOMUXC_ECSPI3_MISO_SELECT_INPUT 0x00000558 2143 #define IMX6UL_IOMUXC_ECSPI3_MOSI_SELECT_INPUT 0x0000055c 2144 #define IMX6UL_IOMUXC_ECSPI3_SS0_B_SELECT_INPUT 0x00000560 2145 #define IMX6UL_IOMUXC_ECSPI4_SCLK_SELECT_INPUT 0x00000564 2146 #define IMX6UL_IOMUXC_ECSPI4_MISO_SELECT_INPUT 0x00000568 2147 #define IMX6UL_IOMUXC_ECSPI4_MOSI_SELECT_INPUT 0x0000056c 2148 #define IMX6UL_IOMUXC_ECSPI4_SS0_B_SELECT_INPUT 0x00000570 2149 #define IMX6UL_IOMUXC_ENET1_REF_CLK1_SELECT_INPUT 0x00000574 2150 #define IMX6UL_IOMUXC_ENET1_MAC0_MDIO_SELECT_INPUT 0x00000578 2151 #define IMX6UL_IOMUXC_ENET2_REF_CLK2_SELECT_INPUT 0x0000057c 2152 #define IMX6UL_IOMUXC_ENET2_MAC0_MDIO_SELECT_INPUT 0x00000580 2153 #define IMX6UL_IOMUXC_FLEXCAN1_RX_SELECT_INPUT 0x00000584 2154 #define IMX6UL_IOMUXC_FLEXCAN2_RX_SELECT_INPUT 0x00000588 2155 #define IMX6UL_IOMUXC_GPT1_CAPTURE1_SELECT_INPUT 0x0000058c 2156 #define IMX6UL_IOMUXC_GPT1_CAPTURE2_SELECT_INPUT 0x00000590 2157 #define IMX6UL_IOMUXC_GPT1_CLK_SELECT_INPUT 0x00000594 2158 #define IMX6UL_IOMUXC_GPT2_CAPTURE1_SELECT_INPUT 0x00000598 2159 #define IMX6UL_IOMUXC_GPT2_CAPTURE2_SELECT_INPUT 0x0000059c 2160 #define IMX6UL_IOMUXC_GPT2_CLK_SELECT_INPUT 0x000005a0 2161 #define IMX6UL_IOMUXC_I2C1_SCL_SELECT_INPUT 0x000005a4 2162 #define IMX6UL_IOMUXC_I2C1_SDA_SELECT_INPUT 0x000005a8 2163 #define IMX6UL_IOMUXC_I2C2_SCL_SELECT_INPUT 0x000005ac 2164 #define IMX6UL_IOMUXC_I2C2_SDA_SELECT_INPUT 0x000005b0 2165 #define IMX6UL_IOMUXC_I2C3_SCL_SELECT_INPUT 0x000005b4 2166 #define IMX6UL_IOMUXC_I2C3_SDA_SELECT_INPUT 0x000005b8 2167 #define IMX6UL_IOMUXC_I2C4_SCL_SELECT_INPUT 0x000005bc 2168 #define IMX6UL_IOMUXC_I2C4_SDA_SELECT_INPUT 0x000005c0 2169 #define IMX6UL_IOMUXC_KPP_COL0_SELECT_INPUT 0x000005c4 2170 #define IMX6UL_IOMUXC_KPP_COL1_SELECT_INPUT 0x000005c8 2171 #define IMX6UL_IOMUXC_KPP_COL2_SELECT_INPUT 0x000005cc 2172 #define IMX6UL_IOMUXC_KPP_ROW0_SELECT_INPUT 0x000005d0 2173 #define IMX6UL_IOMUXC_KPP_ROW1_SELECT_INPUT 0x000005d4 2174 #define IMX6UL_IOMUXC_KPP_ROW2_SELECT_INPUT 0x000005d8 2175 #define IMX6UL_IOMUXC_LCD_BUSY_SELECT_INPUT 0x000005dc 2176 #define IMX6UL_IOMUXC_SAI1_MCLK_SELECT_INPUT 0x000005e0 2177 #define IMX6UL_IOMUXC_SAI1_RX_DATA_SELECT_INPUT 0x000005e4 2178 #define IMX6UL_IOMUXC_SAI1_TX_BCLK_SELECT_INPUT 0x000005e8 2179 #define IMX6UL_IOMUXC_SAI1_TX_SYNC_SELECT_INPUT 0x000005ec 2180 #define IMX6UL_IOMUXC_SAI2_MCLK_SELECT_INPUT 0x000005f0 2181 #define IMX6UL_IOMUXC_SAI2_RX_DATA_SELECT_INPUT 0x000005f4 2182 #define IMX6UL_IOMUXC_SAI2_TX_BCLK_SELECT_INPUT 0x000005f8 2183 #define IMX6UL_IOMUXC_SAI2_TX_SYNC_SELECT_INPUT 0x000005fc 2184 #define IMX6UL_IOMUXC_SAI3_MCLK_SELECT_INPUT 0x00000600 2185 #define IMX6UL_IOMUXC_SAI3_RX_DATA_SELECT_INPUT 0x00000604 2186 #define IMX6UL_IOMUXC_SAI3_TX_BCLK_SELECT_INPUT 0x00000608 2187 #define IMX6UL_IOMUXC_SAI3_TX_SYNC_SELECT_INPUT 0x0000060c 2188 #define IMX6UL_IOMUXC_SDMA_EVENTS0_SELECT_INPUT 0x00000610 2189 #define IMX6UL_IOMUXC_SDMA_EVENTS1_SELECT_INPUT 0x00000614 2190 #define IMX6UL_IOMUXC_SPDIF_IN_SELECT_INPUT 0x00000618 2191 #define IMX6UL_IOMUXC_SPDIF_EXT_CLK_SELECT_INPUT 0x0000061c 2192 #define IMX6UL_IOMUXC_UART1_RTS_B_SELECT_INPUT 0x00000620 2193 #define IMX6UL_IOMUXC_UART1_RX_DATA_SELECT_INPUT 0x00000624 2194 #define IMX6UL_IOMUXC_UART2_RTS_B_SELECT_INPUT 0x00000628 2195 #define IMX6UL_IOMUXC_UART2_RX_DATA_SELECT_INPUT 0x0000062c 2196 #define IMX6UL_IOMUXC_UART3_RTS_B_SELECT_INPUT 0x00000630 2197 #define IMX6UL_IOMUXC_UART3_RX_DATA_SELECT_INPUT 0x00000634 2198 #define IMX6UL_IOMUXC_UART4_RTS_B_SELECT_INPUT 0x00000638 2199 #define IMX6UL_IOMUXC_UART4_RX_DATA_SELECT_INPUT 0x0000063c 2200 #define IMX6UL_IOMUXC_UART5_RTS_B_SELECT_INPUT 0x00000640 2201 #define IMX6UL_IOMUXC_UART5_RX_DATA_SELECT_INPUT 0x00000644 2202 #define IMX6UL_IOMUXC_UART6_RTS_B_SELECT_INPUT 0x00000648 2203 #define IMX6UL_IOMUXC_UART6_RX_DATA_SELECT_INPUT 0x0000064c 2204 #define IMX6UL_IOMUXC_UART7_RTS_B_SELECT_INPUT 0x00000650 2205 #define IMX6UL_IOMUXC_UART7_RX_DATA_SELECT_INPUT 0x00000654 2206 #define IMX6UL_IOMUXC_UART8_RTS_B_SELECT_INPUT 0x00000658 2207 #define IMX6UL_IOMUXC_UART8_RX_DATA_SELECT_INPUT 0x0000065c 2208 #define IMX6UL_IOMUXC_USB_OTG2_OC_SELECT_INPUT 0x00000660 2209 #define IMX6UL_IOMUXC_USB_OTG_OC_SELECT_INPUT 0x00000664 2210 #define IMX6UL_IOMUXC_USDHC1_CD_B_SELECT_INPUT 0x00000668 2211 #define IMX6UL_IOMUXC_USDHC1_WP_SELECT_INPUT 0x0000066c 2212 #define IMX6UL_IOMUXC_USDHC2_CLK_SELECT_INPUT 0x00000670 2213 #define IMX6UL_IOMUXC_USDHC2_CD_B_SELECT_INPUT 0x00000674 2214 #define IMX6UL_IOMUXC_USDHC2_CMD_SELECT_INPUT 0x00000678 2215 #define IMX6UL_IOMUXC_USDHC2_DATA0_SELECT_INPUT 0x0000067c 2216 #define IMX6UL_IOMUXC_USDHC2_DATA1_SELECT_INPUT 0x00000680 2217 #define IMX6UL_IOMUXC_USDHC2_DATA2_SELECT_INPUT 0x00000684 2218 #define IMX6UL_IOMUXC_USDHC2_DATA3_SELECT_INPUT 0x00000688 2219 #define IMX6UL_IOMUXC_USDHC2_DATA4_SELECT_INPUT 0x0000068c 2220 #define IMX6UL_IOMUXC_USDHC2_DATA5_SELECT_INPUT 0x00000690 2221 #define IMX6UL_IOMUXC_USDHC2_DATA6_SELECT_INPUT 0x00000694 2222 #define IMX6UL_IOMUXC_USDHC2_DATA7_SELECT_INPUT 0x00000698 2223 #define IMX6UL_IOMUXC_USDHC2_WP_SELECT_INPUT 0x0000069c 2224 2225 2226 /* IOMUXC_SW_MUX_CTL_PAD_xxx */ 2227 #define IOMUX_CONFIG_SION __BIT(4) 2228 #define IOMUX_CONFIG_ALT0 0 2229 #define IOMUX_CONFIG_ALT1 1 2230 #define IOMUX_CONFIG_ALT2 2 2231 #define IOMUX_CONFIG_ALT3 3 2232 #define IOMUX_CONFIG_ALT4 4 2233 #define IOMUX_CONFIG_ALT5 5 2234 #define IOMUX_CONFIG_ALT6 6 2235 #define IOMUX_CONFIG_ALT7 7 2236 /* IOMUXC_SW_PAD_CTL_PAD_xxx */ 2237 #define PAD_CTL_DDR_SEL_MASK __BITS(19, 18) 2238 #define PAD_CTL_DDR_SEL_0 __SHIFTIN(0, PAD_CTL_DDR_SEL_MASK) 2239 #define PAD_CTL_DDR_SEL_1 __SHIFTIN(1, PAD_CTL_DDR_SEL_MASK) 2240 #define PAD_CTL_DDR_SEL_2 __SHIFTIN(2, PAD_CTL_DDR_SEL_MASK) 2241 #define PAD_CTL_DDR_SEL_3 __SHIFTIN(3, PAD_CTL_DDR_SEL_MASK) 2242 #define PAD_CTL_HYS __BIT(16) 2243 #define PAD_CTL_PUS_MASK __BITS(15, 14) 2244 #define PAD_CTL_PUS_100K_PD __SHIFTIN(0x0, PAD_CTL_PUS_MASK) 2245 #define PAD_CTL_PUS_47K_PU __SHIFTIN(0x1, PAD_CTL_PUS_MASK) 2246 #define PAD_CTL_PUS_100K_PU __SHIFTIN(0x2, PAD_CTL_PUS_MASK) 2247 #define PAD_CTL_PUS_22K_PU __SHIFTIN(0x3, PAD_CTL_PUS_MASK) 2248 #define PAD_CTL_PUE __BIT(13) 2249 #define PAD_CTL_PKE __BIT(12) 2250 #define PAD_CTL_PULL (PAD_CTL_PKE|PAD_CTL_PUE) 2251 #define PAD_CTL_KEEPER (PAD_CTL_PKE|0) 2252 #define PAD_CTL_ODE __BIT(11) 2253 #define PAD_CTL_ODT __BITS(10, 8) 2254 #define PAD_CTL_SPEED_MASK __BITS(7, 6) 2255 #define PAD_CTL_SPEED_LOW50MHZ __SHIFTIN(0, PAD_CTL_SPEED_MASK) 2256 #define PAD_CTL_SPEED_50MHZ __SHIFTIN(1, PAD_CTL_SPEED_MASK) 2257 #define PAD_CTL_SPEED_100MHZ __SHIFTIN(2, PAD_CTL_SPEED_MASK) 2258 #define PAD_CTL_SPEED_200MHZ __SHIFTIN(3, PAD_CTL_SPEED_MASK) 2259 #define PAD_CTL_DSE_MASK __BITS(5, 3) 2260 #define PAD_CTL_DSE_HIZ __SHIFTIN(0x0, PAD_CTL_DSE_MASK) 2261 #define PAD_CTL_DSE_290OHM __SHIFTIN(0x1, PAD_CTL_DSE_MASK) 2262 #define PAD_CTL_DSE_240OHM __SHIFTIN(0x1, PAD_CTL_DSE_MASK) 2263 #define PAD_CTL_DSE_121OHM __SHIFTIN(0x2, PAD_CTL_DSE_MASK) 2264 #define PAD_CTL_DSE_120OHM __SHIFTIN(0x2, PAD_CTL_DSE_MASK) 2265 #define PAD_CTL_DSE_80OHM __SHIFTIN(0x3, PAD_CTL_DSE_MASK) 2266 #define PAD_CTL_DSE_76OHM __SHIFTIN(0x3, PAD_CTL_DSE_MASK) 2267 #define PAD_CTL_DSE_60OHM __SHIFTIN(0x4, PAD_CTL_DSE_MASK) 2268 #define PAD_CTL_DSE_48OHM __SHIFTIN(0x5, PAD_CTL_DSE_MASK) 2269 #define PAD_CTL_DSE_47OHM __SHIFTIN(0x4, PAD_CTL_DSE_MASK) 2270 #define PAD_CTL_DSE_45OHM __SHIFTIN(0x5, PAD_CTL_DSE_MASK) 2271 #define PAD_CTL_DSE_40OHM __SHIFTIN(0x6, PAD_CTL_DSE_MASK) 2272 #define PAD_CTL_DSE_37OHM __SHIFTIN(0x6, PAD_CTL_DSE_MASK) 2273 #define PAD_CTL_DSE_34OHM __SHIFTIN(0x7, PAD_CTL_DSE_MASK) 2274 #define PAD_CTL_DSE_31OHM __SHIFTIN(0x7, PAD_CTL_DSE_MASK) 2275 #define PAD_CTL_SRE __BIT(0) 2276 #define PAD_CTL_SRE_SLOW 0 2277 #define PAD_CTL_SRE_FAST PAD_CTL_SRE 2278 /* IOMUXC_SW_PAD_CTL_PAD_xxx */ 2279 #define INPUT_DAISY_0 0 2280 #define INPUT_DAISY_1 1 2281 #define INPUT_DAISY_2 2 2282 #define INPUT_DAISY_3 3 2283 #define INPUT_DAISY_4 4 2284 #define INPUT_DAISY_5 5 2285 #define INPUT_DAISY_6 6 2286 #define INPUT_DAISY_7 7 2287 2288 /* 2289 * IOMUX index macro 2290 */ 2291 #define IOMUX_PIN_TO_MUX_ADDRESS(pin) (((pin) >> 16) & 0xffff) 2292 #define IOMUX_PIN_TO_PAD_ADDRESS(pin) (((pin) >> 0) & 0xffff) 2293 #define IOMUX_MUX_NONE 0xffff 2294 #define IOMUX_PAD_NONE 0xffff 2295 #define IOMUX_PIN(mux_adr, pad_adr) \ 2296 (((mux_adr) << 16) | (((pad_adr) << 0))) 2297 #define MUX_PIN(prefix, name) \ 2298 IOMUX_PIN(prefix##_IOMUXC_SW_MUX_CTL_PAD_##name, \ 2299 prefix##_IOMUXC_SW_PAD_CTL_PAD_##name) 2300 2301 #endif /* _ARM_NXP_IMX6_IOMUXREG_H_ */ 2302
Indexes created Tue Sep 30 07:10:03 GMT 2025