imx6_pcie.c revision 1.1
1 /* $NetBSD: imx6_pcie.c,v 1.1 2020/12/23 14:42:38 skrll Exp $ */ 2 3 /*- 4 * Copyright (c) 2019 Genetec Corporation. All rights reserved. 5 * Written by Hashimoto Kenichi for Genetec Corporation. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: imx6_pcie.c,v 1.1 2020/12/23 14:42:38 skrll Exp $"); 31 32 #include "opt_pci.h" 33 #include "opt_fdt.h" 34 35 #include "pci.h" 36 #include "locators.h" 37 38 #define _INTR_PRIVATE 39 40 #include <sys/bus.h> 41 #include <sys/device.h> 42 #include <sys/intr.h> 43 #include <sys/systm.h> 44 #include <sys/param.h> 45 #include <sys/kernel.h> 46 #include <sys/queue.h> 47 #include <sys/mutex.h> 48 #include <sys/kmem.h> 49 #include <sys/gpio.h> 50 51 #include <machine/frame.h> 52 #include <arm/cpufunc.h> 53 54 #include <dev/fdt/fdtvar.h> 55 56 #include <dev/pci/pcireg.h> 57 #include <dev/pci/pcivar.h> 58 #include <dev/pci/pciconf.h> 59 60 #include <arm/imx/imxpcievar.h> 61 #include <arm/imx/imxgpioreg.h> 62 #include <arm/imx/imxgpiovar.h> 63 #include <arm/nxp/imx6_iomuxreg.h> 64 #include <arm/nxp/imx6_ccmreg.h> 65 #include <arm/nxp/imx6_ccmvar.h> 66 67 struct imxpcie_fdt_softc { 68 struct imxpcie_softc sc_imxpcie; 69 70 struct fdtbus_gpio_pin *sc_pin_reset; 71 struct fdtbus_regulator *sc_reg_vpcie; 72 }; 73 74 static int imx6_pcie_match(device_t, cfdata_t, void *); 75 static void imx6_pcie_attach(device_t, device_t, void *); 76 77 static void imx6_pcie_configure(void *); 78 static uint32_t imx6_pcie_gpr_read(void *, uint32_t); 79 static void imx6_pcie_gpr_write(void *, uint32_t, uint32_t); 80 static void imx6_pcie_reset(void *); 81 82 #define IMX6_PCIE_MEM_BASE 0x01000000 83 #define IMX6_PCIE_MEM_SIZE 0x00f00000 /* 15MB */ 84 #define IMX6_PCIE_ROOT_BASE 0x01f00000 85 #define IMX6_PCIE_ROOT_SIZE 0x00080000 /* 512KB */ 86 #define IMX6_PCIE_IO_BASE 0x01f80000 87 #define IMX6_PCIE_IO_SIZE 0x00010000 /* 64KB */ 88 89 CFATTACH_DECL_NEW(imxpcie_fdt, sizeof(struct imxpcie_fdt_softc), 90 imx6_pcie_match, imx6_pcie_attach, NULL, NULL); 91 92 static const struct of_compat_data compat_data[] = { 93 { "fsl,imx6q-pcie", false }, 94 { "fsl,imx6qp-pcie", true }, 95 { NULL } 96 }; 97 98 static int 99 imx6_pcie_match(device_t parent, cfdata_t cf, void *aux) 100 { 101 struct fdt_attach_args * const faa = aux; 102 103 return of_match_compat_data(faa->faa_phandle, compat_data); 104 } 105 106 static void 107 imx6_pcie_attach(device_t parent, device_t self, void *aux) 108 { 109 struct imxpcie_fdt_softc * const ifsc = device_private(self); 110 struct imxpcie_softc * const sc = &ifsc->sc_imxpcie; 111 struct fdt_attach_args * const faa = aux; 112 const int phandle = faa->faa_phandle; 113 bus_space_tag_t bst = faa->faa_bst; 114 char intrstr[128]; 115 bus_addr_t addr; 116 bus_size_t size; 117 118 aprint_naive("\n"); 119 aprint_normal(": PCI Express Controller\n"); 120 121 sc->sc_dev = self; 122 sc->sc_iot = bst; 123 sc->sc_dmat = faa->faa_dmat; 124 sc->sc_cookie = ifsc; 125 sc->sc_pci_netbsd_configure = imx6_pcie_configure; 126 sc->sc_gpr_read = imx6_pcie_gpr_read; 127 sc->sc_gpr_write = imx6_pcie_gpr_write; 128 sc->sc_reset = imx6_pcie_reset; 129 sc->sc_have_sw_reset = of_search_compatible(phandle, compat_data)->data; 130 131 if (fdtbus_get_reg_byname(phandle, "dbi", &addr, &size) != 0) { 132 aprint_error(": couldn't get registers\n"); 133 return; 134 } 135 if (bus_space_map(sc->sc_iot, addr, size, 0, &sc->sc_ioh)) { 136 aprint_error_dev(self, "Cannot map registers\n"); 137 return; 138 } 139 if (fdtbus_get_reg_byname(phandle, "config", &addr, &size) != 0) { 140 aprint_error(": couldn't get registers\n"); 141 return; 142 } 143 sc->sc_root_addr = addr; 144 sc->sc_root_size = size; 145 146 const int gpr_phandle = OF_finddevice("/soc/aips-bus/iomuxc-gpr"); 147 fdtbus_get_reg(gpr_phandle, 0, &addr, &size); 148 if (bus_space_map(sc->sc_iot, addr, size, 0, &sc->sc_gpr_ioh)) { 149 aprint_error_dev(self, "Cannot map registers\n"); 150 return; 151 } 152 153 ifsc->sc_pin_reset = fdtbus_gpio_acquire(phandle, "reset-gpio", 154 GPIO_PIN_OUTPUT); 155 if (!ifsc->sc_pin_reset) { 156 aprint_error(": couldn't acquire reset gpio\n"); 157 return; 158 } 159 160 sc->sc_clk_pcie = fdtbus_clock_get(phandle, "pcie"); 161 if (sc->sc_clk_pcie == NULL) { 162 aprint_error(": couldn't get clock pcie_axi\n"); 163 return; 164 } 165 sc->sc_clk_pcie_bus = fdtbus_clock_get(phandle, "pcie_bus"); 166 if (sc->sc_clk_pcie_bus == NULL) { 167 aprint_error(": couldn't get clock lvds1_gate\n"); 168 return; 169 } 170 sc->sc_clk_pcie_phy = fdtbus_clock_get(phandle, "pcie_phy"); 171 if (sc->sc_clk_pcie_phy == NULL) { 172 aprint_error(": couldn't get clock pcie_ref\n"); 173 return; 174 } 175 176 if (of_hasprop(phandle, "vpcie-supply")) { 177 ifsc->sc_reg_vpcie = fdtbus_regulator_acquire(phandle, "vpcie-supply"); 178 if (ifsc->sc_reg_vpcie == NULL) { 179 aprint_error(": couldn't acquire regulator\n"); 180 return; 181 } 182 aprint_normal_dev(self, "regulator On\n"); 183 fdtbus_regulator_enable(ifsc->sc_reg_vpcie); 184 } 185 186 if (of_hasprop(phandle, "ext_osc")) { 187 aprint_normal_dev(self, "Use external OSC\n"); 188 sc->sc_ext_osc = true; 189 190 sc->sc_clk_pcie_ext = fdtbus_clock_get(phandle, "pcie_ext"); 191 if (sc->sc_clk_pcie_ext == NULL) { 192 aprint_error(": couldn't get clock pcie_ext\n"); 193 return; 194 } 195 sc->sc_clk_pcie_ext_src = fdtbus_clock_get(phandle, "pcie_ext_src"); 196 if (sc->sc_clk_pcie_ext_src == NULL) { 197 aprint_error(": couldn't get clock pcie_ext_src\n"); 198 return; 199 } 200 } else { 201 sc->sc_ext_osc = false; 202 sc->sc_clk_pcie_ext = NULL; 203 sc->sc_clk_pcie_ext_src = NULL; 204 } 205 206 if (!fdtbus_intr_str(phandle, 0, intrstr, sizeof(intrstr))) { 207 aprint_error_dev(self, "failed to decode interrupt\n"); 208 return; 209 } 210 211 sc->sc_ih = fdtbus_intr_establish(phandle, 0, IPL_VM, 212 FDT_INTR_MPSAFE, imxpcie_intr, sc); 213 if (sc->sc_ih == NULL) { 214 aprint_error_dev(self, "failed to establish interrupt on %s\n", 215 intrstr); 216 return; 217 } 218 aprint_normal_dev(self, "interrupting on %s\n", intrstr); 219 220 imxpcie_attach_common(sc); 221 } 222 223 static void 224 imx6_pcie_configure(void *cookie) 225 { 226 struct imxpcie_fdt_softc * const ifsc = cookie; 227 struct imxpcie_softc * const sc = &ifsc->sc_imxpcie; 228 229 #ifdef PCI_NETBSD_CONFIGURE 230 struct pciconf_resources *pcires = pciconf_resource_init(); 231 232 pciconf_resource_add(pcires, PCICONF_RESOURCE_IO, 233 IMX6_PCIE_IO_BASE, IMX6_PCIE_IO_SIZE); 234 pciconf_resource_add(pcires, PCICONF_RESOURCE_MEM, 235 IMX6_PCIE_MEM_BASE, IMX6_PCIE_MEM_SIZE); 236 237 int error = pci_configure_bus(&sc->sc_pc, pcires, 0, arm_dcache_align); 238 239 pciconf_resource_fini(pcires); 240 241 if (error) { 242 aprint_error_dev(sc->sc_dev, "configuration failed (%d)\n", 243 error); 244 } 245 #endif 246 } 247 248 static uint32_t 249 imx6_pcie_gpr_read(void *cookie, uint32_t reg) 250 { 251 struct imxpcie_fdt_softc * const ifsc = cookie; 252 struct imxpcie_softc * const sc = &ifsc->sc_imxpcie; 253 return bus_space_read_4(sc->sc_iot, sc->sc_gpr_ioh, reg); 254 } 255 256 static void 257 imx6_pcie_gpr_write(void *cookie, uint32_t reg, uint32_t val) 258 { 259 struct imxpcie_fdt_softc * const ifsc = cookie; 260 struct imxpcie_softc * const sc = &ifsc->sc_imxpcie; 261 bus_space_write_4(sc->sc_iot, sc->sc_gpr_ioh, reg, val); 262 } 263 264 static void 265 imx6_pcie_reset(void *cookie) 266 { 267 struct imxpcie_fdt_softc * const ifsc = cookie; 268 269 fdtbus_gpio_write(ifsc->sc_pin_reset, 1); 270 delay(20 * 1000); 271 fdtbus_gpio_write(ifsc->sc_pin_reset, 0); 272 } 273
Indexes created Tue Sep 23 07:09:52 GMT 2025