imx6_platform.c revision 1.4
1 /* $NetBSD: imx6_platform.c,v 1.4 2021/02/04 22:36:53 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2019 Genetec Corporation. All rights reserved. 5 * Written by Hashimoto Kenichi for Genetec Corporation. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: imx6_platform.c,v 1.4 2021/02/04 22:36:53 thorpej Exp $"); 31 32 #include "arml2cc.h" 33 #include "opt_console.h" 34 #include "opt_fdt.h" 35 #include "opt_multiprocessor.h" 36 #include "opt_soc.h" 37 38 #include <sys/param.h> 39 #include <sys/bus.h> 40 #include <sys/cpu.h> 41 #include <sys/device.h> 42 #include <sys/termios.h> 43 44 #include <dev/fdt/fdtvar.h> 45 #include <arm/fdt/arm_fdtvar.h> 46 47 #include <uvm/uvm_extern.h> 48 49 #include <arm/arm32/machdep.h> 50 51 #include <machine/bootconfig.h> 52 #include <arm/cpufunc.h> 53 54 #include <arm/cortex/a9tmr_var.h> 55 #include <arm/cortex/scu_reg.h> 56 #include <arm/cortex/gic_reg.h> 57 #include <arm/cortex/pl310_var.h> 58 59 #include <arm/nxp/imx6_reg.h> 60 #include <arm/nxp/imx6_srcreg.h> 61 #include <arm/imx/imxuartreg.h> 62 #include <arm/imx/imxwdogreg.h> 63 64 #include <arm/nxp/imx6_platform.h> 65 66 #include <libfdt.h> 67 68 #define IMX_REF_FREQ 80000000 69 70 #ifdef VERBOSE_INIT_ARM 71 #define VPRINTF(...) printf(__VA_ARGS__) 72 #else 73 #define VPRINTF(...) __nothing 74 #endif 75 76 extern struct bus_space armv7_generic_bs_tag; 77 extern struct arm32_bus_dma_tag arm_generic_dma_tag; 78 79 static const struct pmap_devmap * 80 imx_platform_devmap(void) 81 { 82 static const struct pmap_devmap devmap[] = { 83 DEVMAP_ENTRY(KERNEL_IO_IOREG_VBASE, IMX6_IOREG_PBASE, IMX6_IOREG_SIZE), 84 DEVMAP_ENTRY(KERNEL_IO_ARMCORE_VBASE, IMX6_ARMCORE_PBASE, IMX6_ARMCORE_SIZE), 85 DEVMAP_ENTRY_END 86 }; 87 88 return devmap; 89 } 90 91 static void 92 imx_platform_init_attach_args(struct fdt_attach_args *faa) 93 { 94 faa->faa_bst = &armv7_generic_bs_tag; 95 faa->faa_dmat = &arm_generic_dma_tag; 96 } 97 98 void imx_platform_early_putchar(char); 99 100 void __noasan 101 imx_platform_early_putchar(char c) 102 { 103 #ifdef CONSADDR 104 #define CONSADDR_VA ((CONSADDR - IMX6_IOREG_PBASE) + KERNEL_IO_IOREG_VBASE) 105 106 volatile uint32_t *uartaddr = cpu_earlydevice_va_p() ? 107 (volatile uint32_t *)CONSADDR_VA : 108 (volatile uint32_t *)CONSADDR; 109 110 while ((le32toh(uartaddr[(IMX_USR2/4)]) & IMX_USR2_TXDC) == 0) 111 ; 112 113 uartaddr[(IMX_UTXD/4)] = htole32(c); 114 #endif 115 } 116 117 static void 118 imx_platform_device_register(device_t self, void *aux) 119 { 120 prop_dictionary_t prop = device_properties(self); 121 122 fdtbus_device_register(dev, aux); 123 124 if (device_is_a(self, "atphy")) { 125 static const struct device_compatible_entry compat_data[] = { 126 { .compat = "fsl,imx6dl-sabresd" }, 127 { .compat = "fsl,imx6q-sabresd" }, 128 { .compat = "fsl,imx6qp-sabresd" }, 129 { .compat = "solidrun,hummingboard2/q" }, 130 { .compat = "solidrun,hummingboard2/dl" }, 131 DEVICE_COMPAT_EOL 132 }; 133 if (of_compatible_match(OF_finddevice("/"), compat_data)) 134 prop_dictionary_set_uint32(prop, "clk_25m", 125000000); 135 } 136 } 137 138 static u_int 139 imx_platform_uart_freq(void) 140 { 141 return IMX_REF_FREQ; 142 } 143 144 static void 145 imx_platform_bootstrap(void) 146 { 147 #if NARML2CC > 0 148 bus_space_tag_t bst = &armv7_generic_bs_tag; 149 bus_space_handle_t bsh; 150 if (bus_space_map(bst, IMX6_ARMCORE_PBASE, IMX6_ARMCORE_SIZE, 0, &bsh)) 151 panic("couldn't map armcore registers"); 152 arml2cc_init(bst, bsh, ARMCORE_L2C_BASE); 153 bus_space_unmap(bst, bsh, IMX6_ARMCORE_SIZE); 154 #endif 155 156 arm_fdt_cpu_bootstrap(); 157 } 158 159 static int 160 imx_platform_mpstart(void) 161 { 162 #if defined(MULTIPROCESSOR) 163 bus_space_tag_t bst = &armv7_generic_bs_tag; 164 bus_space_handle_t bsh; 165 166 if (bus_space_map(bst, IMX6_ARMCORE_PBASE, IMX6_ARMCORE_SIZE, 0, &bsh) != 0) 167 panic("couldn't map armcore registers"); 168 169 /* Enable Snoop Control Unit */ 170 bus_space_write_4(bst, bsh, SCU_INV_ALL_REG, 0xff); 171 bus_space_write_4(bst, bsh, SCU_CTL, 172 bus_space_read_4(bst, bsh, SCU_CTL) | SCU_CTL_SCU_ENA); 173 174 bus_space_unmap(bst, bsh, AIPS1_SRC_SIZE); 175 176 if (bus_space_map(bst, IMX6_AIPS1_BASE + AIPS1_SRC_BASE, AIPS1_SRC_SIZE, 0, &bsh) != 0) 177 panic("couldn't map SRC"); 178 179 uint32_t srcctl = bus_space_read_4(bst, bsh, SRC_SCR); 180 const paddr_t mpstart = KERN_VTOPHYS((vaddr_t)cpu_mpstart); 181 182 srcctl &= ~(SRC_SCR_CORE1_ENABLE | SRC_SCR_CORE2_ENABLE | 183 SRC_SCR_CORE3_ENABLE); 184 bus_space_write_4(bst, bsh, SRC_SCR, srcctl); 185 186 for (int i = 1; i < arm_cpu_max; i++) { 187 bus_space_write_4(bst, bsh, SRC_GPRN_ENTRY(i), mpstart); 188 srcctl |= SRC_SCR_COREN_RST(i); 189 srcctl |= SRC_SCR_COREN_ENABLE(i); 190 } 191 bus_space_write_4(bst, bsh, SRC_SCR, srcctl); 192 193 bus_space_unmap(bst, bsh, AIPS1_SRC_SIZE); 194 195 return arm_fdt_cpu_mpstart(); 196 #else 197 return 0; 198 #endif 199 } 200 201 static void 202 imx6_platform_reset(void) 203 { 204 bus_space_tag_t bst = &armv7_generic_bs_tag; 205 bus_space_handle_t bsh; 206 207 if (bus_space_map(bst, IMX6_AIPS1_BASE + AIPS1_WDOG1_BASE, AIPS1_WDOG_SIZE, 0, &bsh)) 208 panic("couldn't map wdog1 registers"); 209 210 delay(1000); /* wait for flushing FIFO of serial console */ 211 212 cpsid(I32_bit|F32_bit); 213 214 /* software reset signal on wdog */ 215 bus_space_write_2(bst, bsh, IMX_WDOG_WCR, WCR_WDE); 216 217 /* 218 * write twice due to errata. 219 * Reference: ERR004346: IMX6DQCE Chip Errata for the i.MX 6Dual/6Quad 220 */ 221 bus_space_write_2(bst, bsh, IMX_WDOG_WCR, WCR_WDE); 222 223 for (;;) 224 __asm("wfi"); 225 } 226 227 const struct arm_platform imx6_platform = { 228 .ap_devmap = imx_platform_devmap, 229 .ap_bootstrap = imx_platform_bootstrap, 230 .ap_init_attach_args = imx_platform_init_attach_args, 231 .ap_device_register = imx_platform_device_register, 232 .ap_reset = imx6_platform_reset, 233 .ap_delay = a9ptmr_delay, 234 .ap_uart_freq = imx_platform_uart_freq, 235 .ap_mpstart = imx_platform_mpstart, 236 }; 237 238 ARM_PLATFORM(imx6dl, "fsl,imx6dl", &imx6_platform); 239 ARM_PLATFORM(imx6q, "fsl,imx6q", &imx6_platform); 240 ARM_PLATFORM(imx6qp, "fsl,imx6qp", &imx6_platform); 241
Indexes created Wed Oct 01 15:09:59 GMT 2025