imx6_platform.c revision 1.7
1 /* $NetBSD: imx6_platform.c,v 1.7 2023/04/07 08:55:30 skrll Exp $ */ 2 3 /*- 4 * Copyright (c) 2019 Genetec Corporation. All rights reserved. 5 * Written by Hashimoto Kenichi for Genetec Corporation. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: imx6_platform.c,v 1.7 2023/04/07 08:55:30 skrll Exp $"); 31 32 #include "arml2cc.h" 33 #include "opt_console.h" 34 #include "opt_fdt.h" 35 #include "opt_multiprocessor.h" 36 #include "opt_soc.h" 37 38 #include <sys/param.h> 39 #include <sys/bus.h> 40 #include <sys/cpu.h> 41 #include <sys/device.h> 42 #include <sys/termios.h> 43 44 #include <dev/fdt/fdtvar.h> 45 46 #include <arm/fdt/arm_fdtvar.h> 47 48 #include <uvm/uvm_extern.h> 49 50 #include <arm/arm32/machdep.h> 51 52 #include <machine/bootconfig.h> 53 #include <arm/cpufunc.h> 54 55 #include <arm/cortex/a9tmr_var.h> 56 #include <arm/cortex/scu_reg.h> 57 #include <arm/cortex/gic_reg.h> 58 #include <arm/cortex/pl310_var.h> 59 60 #include <arm/nxp/imx6_reg.h> 61 #include <arm/nxp/imx6_srcreg.h> 62 #include <arm/imx/imxuartreg.h> 63 #include <arm/imx/imxwdogreg.h> 64 65 #include <arm/nxp/imx6_platform.h> 66 67 #include <libfdt.h> 68 69 #define IMX_REF_FREQ 80000000 70 71 #ifdef VERBOSE_INIT_ARM 72 #define VPRINTF(...) printf(__VA_ARGS__) 73 #else 74 #define VPRINTF(...) __nothing 75 #endif 76 77 extern struct bus_space armv7_generic_bs_tag; 78 extern struct arm32_bus_dma_tag arm_generic_dma_tag; 79 80 static const struct pmap_devmap * 81 imx_platform_devmap(void) 82 { 83 static const struct pmap_devmap devmap[] = { 84 DEVMAP_ENTRY(KERNEL_IO_IOREG_VBASE, IMX6_IOREG_PBASE, IMX6_IOREG_SIZE), 85 DEVMAP_ENTRY(KERNEL_IO_ARMCORE_VBASE, IMX6_ARMCORE_PBASE, IMX6_ARMCORE_SIZE), 86 DEVMAP_ENTRY_END 87 }; 88 89 return devmap; 90 } 91 92 static void 93 imx_platform_init_attach_args(struct fdt_attach_args *faa) 94 { 95 faa->faa_bst = &armv7_generic_bs_tag; 96 faa->faa_dmat = &arm_generic_dma_tag; 97 } 98 99 void imx_platform_early_putchar(char); 100 101 void __noasan 102 imx_platform_early_putchar(char c) 103 { 104 #ifdef CONSADDR 105 #define CONSADDR_VA ((CONSADDR - IMX6_IOREG_PBASE) + KERNEL_IO_IOREG_VBASE) 106 107 volatile uint32_t *uartaddr = cpu_earlydevice_va_p() ? 108 (volatile uint32_t *)CONSADDR_VA : 109 (volatile uint32_t *)CONSADDR; 110 111 while ((le32toh(uartaddr[(IMX_USR2/4)]) & IMX_USR2_TXDC) == 0) 112 ; 113 114 uartaddr[(IMX_UTXD/4)] = htole32(c); 115 #endif 116 } 117 118 static void 119 imx_platform_device_register(device_t self, void *aux) 120 { 121 prop_dictionary_t prop = device_properties(self); 122 123 if (device_is_a(self, "atphy")) { 124 static const struct device_compatible_entry compat_data[] = { 125 { .compat = "fsl,imx6dl-sabresd" }, 126 { .compat = "fsl,imx6q-sabresd" }, 127 { .compat = "fsl,imx6qp-sabresd" }, 128 { .compat = "solidrun,hummingboard2/q" }, 129 { .compat = "solidrun,hummingboard2/dl" }, 130 DEVICE_COMPAT_EOL 131 }; 132 if (of_compatible_match(OF_finddevice("/"), compat_data)) 133 prop_dictionary_set_uint32(prop, "clk_25m", 125000000); 134 } 135 } 136 137 static u_int 138 imx_platform_uart_freq(void) 139 { 140 return IMX_REF_FREQ; 141 } 142 143 static void 144 imx_platform_bootstrap(void) 145 { 146 #if NARML2CC > 0 147 bus_space_tag_t bst = &armv7_generic_bs_tag; 148 bus_space_handle_t bsh; 149 if (bus_space_map(bst, IMX6_ARMCORE_PBASE, IMX6_ARMCORE_SIZE, 0, &bsh)) 150 panic("couldn't map armcore registers"); 151 arml2cc_init(bst, bsh, ARMCORE_L2C_BASE); 152 bus_space_unmap(bst, bsh, IMX6_ARMCORE_SIZE); 153 #endif 154 155 arm_fdt_cpu_bootstrap(); 156 } 157 158 static int 159 imx_platform_mpstart(void) 160 { 161 #if defined(MULTIPROCESSOR) 162 bus_space_tag_t bst = &armv7_generic_bs_tag; 163 bus_space_handle_t bsh; 164 165 if (bus_space_map(bst, IMX6_ARMCORE_PBASE, IMX6_ARMCORE_SIZE, 0, &bsh) != 0) 166 panic("couldn't map armcore registers"); 167 168 /* Enable Snoop Control Unit */ 169 bus_space_write_4(bst, bsh, SCU_INV_ALL_REG, 0xff); 170 bus_space_write_4(bst, bsh, SCU_CTL, 171 bus_space_read_4(bst, bsh, SCU_CTL) | SCU_CTL_SCU_ENA); 172 173 bus_space_unmap(bst, bsh, AIPS1_SRC_SIZE); 174 175 if (bus_space_map(bst, IMX6_AIPS1_BASE + AIPS1_SRC_BASE, AIPS1_SRC_SIZE, 0, &bsh) != 0) 176 panic("couldn't map SRC"); 177 178 uint32_t srcctl = bus_space_read_4(bst, bsh, SRC_SCR); 179 const paddr_t mpstart = KERN_VTOPHYS((vaddr_t)cpu_mpstart); 180 181 srcctl &= ~(SRC_SCR_CORE1_ENABLE | SRC_SCR_CORE2_ENABLE | 182 SRC_SCR_CORE3_ENABLE); 183 bus_space_write_4(bst, bsh, SRC_SCR, srcctl); 184 185 for (int i = 1; i < arm_cpu_max; i++) { 186 bus_space_write_4(bst, bsh, SRC_GPRN_ENTRY(i), mpstart); 187 srcctl |= SRC_SCR_COREN_RST(i); 188 srcctl |= SRC_SCR_COREN_ENABLE(i); 189 } 190 bus_space_write_4(bst, bsh, SRC_SCR, srcctl); 191 192 bus_space_unmap(bst, bsh, AIPS1_SRC_SIZE); 193 194 return arm_fdt_cpu_mpstart(); 195 #else 196 return 0; 197 #endif 198 } 199 200 static void 201 imx6_platform_reset(void) 202 { 203 bus_space_tag_t bst = &armv7_generic_bs_tag; 204 bus_space_handle_t bsh; 205 206 if (bus_space_map(bst, IMX6_AIPS1_BASE + AIPS1_WDOG1_BASE, AIPS1_WDOG_SIZE, 0, &bsh)) 207 panic("couldn't map wdog1 registers"); 208 209 delay(1000); /* wait for flushing FIFO of serial console */ 210 211 cpsid(I32_bit|F32_bit); 212 213 /* software reset signal on wdog */ 214 bus_space_write_2(bst, bsh, IMX_WDOG_WCR, WCR_WDE); 215 216 /* 217 * write twice due to errata. 218 * Reference: ERR004346: IMX6DQCE Chip Errata for the i.MX 6Dual/6Quad 219 */ 220 bus_space_write_2(bst, bsh, IMX_WDOG_WCR, WCR_WDE); 221 222 for (;;) 223 __asm("wfi"); 224 } 225 226 static const struct fdt_platform imx6_platform = { 227 .fp_devmap = imx_platform_devmap, 228 .fp_bootstrap = imx_platform_bootstrap, 229 .fp_init_attach_args = imx_platform_init_attach_args, 230 .fp_device_register = imx_platform_device_register, 231 .fp_reset = imx6_platform_reset, 232 .fp_delay = a9ptmr_delay, 233 .fp_uart_freq = imx_platform_uart_freq, 234 .fp_mpstart = imx_platform_mpstart, 235 }; 236 237 FDT_PLATFORM(imx6dl, "fsl,imx6dl", &imx6_platform); 238 FDT_PLATFORM(imx6q, "fsl,imx6q", &imx6_platform); 239 FDT_PLATFORM(imx6qp, "fsl,imx6qp", &imx6_platform); 240
Indexes created Fri Sep 26 20:09:58 GMT 2025