1 1.3 bouyer /* $NetBSD: imx6_usbphy.c,v 1.3 2023/05/04 13:29:33 bouyer Exp $ */ 2 1.1 skrll 3 1.1 skrll /*- 4 1.1 skrll * Copyright (c) 2019 Genetec Corporation. All rights reserved. 5 1.1 skrll * Written by Hashimoto Kenichi for Genetec Corporation. 6 1.1 skrll * 7 1.1 skrll * Redistribution and use in source and binary forms, with or without 8 1.1 skrll * modification, are permitted provided that the following conditions 9 1.1 skrll * are met: 10 1.1 skrll * 1. Redistributions of source code must retain the above copyright 11 1.1 skrll * notice, this list of conditions and the following disclaimer. 12 1.1 skrll * 2. Redistributions in binary form must reproduce the above copyright 13 1.1 skrll * notice, this list of conditions and the following disclaimer in the 14 1.1 skrll * documentation and/or other materials provided with the distribution. 15 1.1 skrll * 16 1.1 skrll * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 1.1 skrll * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 1.1 skrll * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 1.1 skrll * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 1.1 skrll * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 1.1 skrll * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 1.1 skrll * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 1.1 skrll * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 1.1 skrll * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 1.1 skrll * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 1.1 skrll * SUCH DAMAGE. 27 1.1 skrll */ 28 1.1 skrll 29 1.1 skrll #include <sys/cdefs.h> 30 1.3 bouyer __KERNEL_RCSID(1, "$NetBSD: imx6_usbphy.c,v 1.3 2023/05/04 13:29:33 bouyer Exp $"); 31 1.1 skrll 32 1.1 skrll #include "opt_fdt.h" 33 1.1 skrll 34 1.1 skrll #include "locators.h" 35 1.1 skrll #include "ohci.h" 36 1.1 skrll #include "ehci.h" 37 1.1 skrll 38 1.1 skrll #include <sys/param.h> 39 1.1 skrll #include <sys/bus.h> 40 1.1 skrll #include <sys/device.h> 41 1.1 skrll 42 1.1 skrll #include <arm/nxp/imx6_usbphyreg.h> 43 1.1 skrll 44 1.1 skrll #include <dev/fdt/fdtvar.h> 45 1.1 skrll 46 1.1 skrll struct imx6_usbphy_softc { 47 1.1 skrll device_t sc_dev; 48 1.1 skrll 49 1.1 skrll bus_space_tag_t sc_iot; 50 1.1 skrll bus_space_handle_t sc_ioh; 51 1.1 skrll 52 1.1 skrll struct clk *sc_clk; 53 1.1 skrll }; 54 1.1 skrll 55 1.1 skrll static int imx6_usbphy_match(device_t, cfdata_t, void *); 56 1.1 skrll static void imx6_usbphy_attach(device_t, device_t, void *); 57 1.1 skrll 58 1.1 skrll static int imx6_usbphy_init_clocks(device_t); 59 1.1 skrll static int imx6_usbphy_enable(device_t, void *, bool); 60 1.1 skrll 61 1.1 skrll CFATTACH_DECL_NEW(imxusbphy, sizeof(struct imx6_usbphy_softc), 62 1.1 skrll imx6_usbphy_match, imx6_usbphy_attach, NULL, NULL); 63 1.1 skrll 64 1.2 thorpej static const struct device_compatible_entry compat_data[] = { 65 1.2 thorpej { .compat = "fsl,imx6q-usbphy" }, 66 1.3 bouyer { .compat = "fsl,imx6sx-usbphy" }, 67 1.2 thorpej DEVICE_COMPAT_EOL 68 1.1 skrll }; 69 1.1 skrll 70 1.1 skrll static int 71 1.1 skrll imx6_usbphy_match(device_t parent, cfdata_t cf, void *aux) 72 1.1 skrll { 73 1.1 skrll struct fdt_attach_args * const faa = aux; 74 1.1 skrll 75 1.2 thorpej return of_compatible_match(faa->faa_phandle, compat_data); 76 1.1 skrll } 77 1.1 skrll 78 1.1 skrll static void 79 1.1 skrll imx6_usbphy_attach(device_t parent, device_t self, void *aux) 80 1.1 skrll { 81 1.1 skrll struct imx6_usbphy_softc *sc = device_private(self); 82 1.1 skrll struct fdt_attach_args * const faa = aux; 83 1.1 skrll const int phandle = faa->faa_phandle; 84 1.1 skrll bus_space_tag_t bst = faa->faa_bst; 85 1.1 skrll bus_space_handle_t bsh; 86 1.1 skrll bus_addr_t addr; 87 1.1 skrll bus_size_t size; 88 1.1 skrll int error; 89 1.1 skrll 90 1.1 skrll if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 91 1.1 skrll aprint_error(": couldn't get iomux registers\n"); 92 1.1 skrll return; 93 1.1 skrll } 94 1.1 skrll 95 1.1 skrll error = bus_space_map(bst, addr, size, 0, &bsh); 96 1.1 skrll if (error) { 97 1.1 skrll aprint_error(": couldn't map %#" PRIxBUSADDR ": %d", addr, error); 98 1.1 skrll return; 99 1.1 skrll } 100 1.1 skrll 101 1.1 skrll sc->sc_clk = fdtbus_clock_get_index(phandle, 0); 102 1.1 skrll if (sc->sc_clk == NULL) { 103 1.1 skrll aprint_error(": couldn't get clock\n"); 104 1.1 skrll return; 105 1.1 skrll } 106 1.1 skrll 107 1.1 skrll sc->sc_dev = self; 108 1.1 skrll sc->sc_iot = bst; 109 1.1 skrll sc->sc_ioh = bsh; 110 1.1 skrll 111 1.1 skrll aprint_naive("\n"); 112 1.1 skrll aprint_normal(": USB PHY\n"); 113 1.1 skrll 114 1.1 skrll imx6_usbphy_init_clocks(self); 115 1.1 skrll imx6_usbphy_enable(self, NULL, true); 116 1.1 skrll } 117 1.1 skrll 118 1.1 skrll static int 119 1.1 skrll imx6_usbphy_init_clocks(device_t dev) 120 1.1 skrll { 121 1.1 skrll struct imx6_usbphy_softc * const sc = device_private(dev); 122 1.1 skrll int error; 123 1.1 skrll 124 1.1 skrll error = clk_enable(sc->sc_clk); 125 1.1 skrll if (error) { 126 1.1 skrll aprint_error_dev(sc->sc_dev, "couldn't enable: %d\n", error); 127 1.1 skrll return error; 128 1.1 skrll } 129 1.1 skrll 130 1.1 skrll return 0; 131 1.1 skrll } 132 1.1 skrll 133 1.1 skrll #define USBPHY_READ(sc, reg) \ 134 1.1 skrll bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg)) 135 1.1 skrll #define USBPHY_WRITE(sc, reg, val) \ 136 1.1 skrll bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val)) 137 1.1 skrll 138 1.1 skrll static int 139 1.1 skrll imx6_usbphy_enable(device_t dev, void *priv, bool enable) 140 1.1 skrll { 141 1.1 skrll struct imx6_usbphy_softc * const sc = device_private(dev); 142 1.1 skrll 143 1.1 skrll /* USBPHY enable */ 144 1.1 skrll USBPHY_WRITE(sc, USBPHY_CTRL, USBPHY_CTRL_CLKGATE); 145 1.1 skrll 146 1.1 skrll /* do reset */ 147 1.1 skrll USBPHY_WRITE(sc, USBPHY_CTRL_SET, USBPHY_CTRL_SFTRST); 148 1.1 skrll delay(100); 149 1.1 skrll 150 1.1 skrll /* clear reset, and run clocks */ 151 1.1 skrll USBPHY_WRITE(sc, USBPHY_CTRL_CLR, 152 1.1 skrll USBPHY_CTRL_SFTRST | USBPHY_CTRL_CLKGATE); 153 1.1 skrll delay(100); 154 1.1 skrll 155 1.1 skrll /* power on */ 156 1.1 skrll USBPHY_WRITE(sc, USBPHY_PWD, 0); 157 1.1 skrll 158 1.1 skrll /* UTMI+Level2, Level3 */ 159 1.1 skrll USBPHY_WRITE(sc, USBPHY_CTRL_SET, 160 1.1 skrll USBPHY_CTRL_ENUTMILEVEL2 | USBPHY_CTRL_ENUTMILEVEL3); 161 1.1 skrll 162 1.1 skrll return 0; 163 1.1 skrll } 164 1.1 skrll 165