ofw_irqhandler.c revision 1.1.2.3
1 1.1.2.3 nathanw /* $NetBSD: ofw_irqhandler.c,v 1.1.2.3 2002/10/18 02:35:39 nathanw Exp $ */ 2 1.1.2.2 nathanw 3 1.1.2.2 nathanw /* 4 1.1.2.2 nathanw * Copyright (c) 1994-1998 Mark Brinicombe. 5 1.1.2.2 nathanw * Copyright (c) 1994 Brini. 6 1.1.2.2 nathanw * All rights reserved. 7 1.1.2.2 nathanw * 8 1.1.2.2 nathanw * This code is derived from software written for Brini by Mark Brinicombe 9 1.1.2.2 nathanw * 10 1.1.2.2 nathanw * Redistribution and use in source and binary forms, with or without 11 1.1.2.2 nathanw * modification, are permitted provided that the following conditions 12 1.1.2.2 nathanw * are met: 13 1.1.2.2 nathanw * 1. Redistributions of source code must retain the above copyright 14 1.1.2.2 nathanw * notice, this list of conditions and the following disclaimer. 15 1.1.2.2 nathanw * 2. Redistributions in binary form must reproduce the above copyright 16 1.1.2.2 nathanw * notice, this list of conditions and the following disclaimer in the 17 1.1.2.2 nathanw * documentation and/or other materials provided with the distribution. 18 1.1.2.2 nathanw * 3. All advertising materials mentioning features or use of this software 19 1.1.2.2 nathanw * must display the following acknowledgement: 20 1.1.2.2 nathanw * This product includes software developed by Mark Brinicombe 21 1.1.2.2 nathanw * for the NetBSD Project. 22 1.1.2.2 nathanw * 4. The name of the company nor the name of the author may be used to 23 1.1.2.2 nathanw * endorse or promote products derived from this software without specific 24 1.1.2.2 nathanw * prior written permission. 25 1.1.2.2 nathanw * 26 1.1.2.2 nathanw * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 27 1.1.2.2 nathanw * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 28 1.1.2.2 nathanw * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 29 1.1.2.2 nathanw * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 30 1.1.2.2 nathanw * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 31 1.1.2.2 nathanw * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 32 1.1.2.2 nathanw * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 33 1.1.2.2 nathanw * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 34 1.1.2.2 nathanw * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 35 1.1.2.2 nathanw * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 36 1.1.2.2 nathanw * 37 1.1.2.2 nathanw * from: irqhandler.c 38 1.1.2.2 nathanw * 39 1.1.2.2 nathanw * IRQ/FIQ initialisation, claim, release and handler routines 40 1.1.2.2 nathanw * 41 1.1.2.2 nathanw * Created : 30/09/94 42 1.1.2.2 nathanw */ 43 1.1.2.2 nathanw 44 1.1.2.2 nathanw #include "opt_irqstats.h" 45 1.1.2.2 nathanw 46 1.1.2.2 nathanw #include <sys/param.h> 47 1.1.2.2 nathanw #include <sys/systm.h> 48 1.1.2.2 nathanw #include <sys/syslog.h> 49 1.1.2.2 nathanw #include <sys/malloc.h> 50 1.1.2.2 nathanw 51 1.1.2.2 nathanw #include <uvm/uvm_extern.h> 52 1.1.2.2 nathanw 53 1.1.2.2 nathanw #include <machine/intr.h> 54 1.1.2.2 nathanw #include <machine/cpu.h> 55 1.1.2.2 nathanw 56 1.1.2.2 nathanw irqhandler_t *irqhandlers[NIRQS]; 57 1.1.2.2 nathanw 58 1.1.2.2 nathanw int current_intr_depth; 59 1.1.2.2 nathanw u_int current_mask; 60 1.1.2.2 nathanw u_int actual_mask; 61 1.1.2.2 nathanw u_int disabled_mask; 62 1.1.2.2 nathanw u_int spl_mask; 63 1.1.2.2 nathanw u_int irqmasks[IPL_LEVELS]; 64 1.1.2.2 nathanw u_int irqblock[NIRQS]; 65 1.1.2.2 nathanw extern u_int intrcnt[]; 66 1.1.2.2 nathanw 67 1.1.2.2 nathanw extern u_int soft_interrupts; /* Only so we can initialise it */ 68 1.1.2.2 nathanw 69 1.1.2.2 nathanw extern char *_intrnames; 70 1.1.2.2 nathanw 71 1.1.2.2 nathanw /* Prototypes */ 72 1.1.2.2 nathanw 73 1.1.2.2 nathanw int podule_irqhandler __P((void)); 74 1.1.2.2 nathanw extern void set_spl_masks __P((void)); 75 1.1.2.2 nathanw 76 1.1.2.2 nathanw /* 77 1.1.2.2 nathanw * void irq_init(void) 78 1.1.2.2 nathanw * 79 1.1.2.2 nathanw * Initialise the IRQ/FIQ sub system 80 1.1.2.2 nathanw */ 81 1.1.2.2 nathanw 82 1.1.2.2 nathanw void 83 1.1.2.2 nathanw irq_init() 84 1.1.2.2 nathanw { 85 1.1.2.2 nathanw int loop; 86 1.1.2.2 nathanw 87 1.1.2.2 nathanw /* Clear all the IRQ handlers and the irq block masks */ 88 1.1.2.2 nathanw for (loop = 0; loop < NIRQS; ++loop) { 89 1.1.2.2 nathanw irqhandlers[loop] = NULL; 90 1.1.2.2 nathanw irqblock[loop] = 0; 91 1.1.2.2 nathanw } 92 1.1.2.2 nathanw 93 1.1.2.2 nathanw /* 94 1.1.2.2 nathanw * Setup the irqmasks for the different Interrupt Priority Levels 95 1.1.2.2 nathanw * We will start with no bits set and these will be updated as handlers 96 1.1.2.2 nathanw * are installed at different IPL's. 97 1.1.2.2 nathanw */ 98 1.1.2.2 nathanw for (loop = 0; loop < IPL_LEVELS; ++loop) 99 1.1.2.2 nathanw irqmasks[loop] = 0; 100 1.1.2.2 nathanw 101 1.1.2.2 nathanw current_intr_depth = 0; 102 1.1.2.2 nathanw current_mask = 0x00000000; 103 1.1.2.2 nathanw disabled_mask = 0x00000000; 104 1.1.2.2 nathanw actual_mask = 0x00000000; 105 1.1.2.2 nathanw spl_mask = 0x00000000; 106 1.1.2.2 nathanw soft_interrupts = 0x00000000; 107 1.1.2.2 nathanw 108 1.1.2.2 nathanw set_spl_masks(); 109 1.1.2.2 nathanw 110 1.1.2.2 nathanw /* Enable IRQ's and FIQ's */ 111 1.1.2.2 nathanw enable_interrupts(I32_bit | F32_bit); 112 1.1.2.2 nathanw } 113 1.1.2.2 nathanw 114 1.1.2.2 nathanw 115 1.1.2.2 nathanw /* 116 1.1.2.2 nathanw * int irq_claim(int irq, irqhandler_t *handler) 117 1.1.2.2 nathanw * 118 1.1.2.2 nathanw * Enable an IRQ and install a handler for it. 119 1.1.2.2 nathanw */ 120 1.1.2.2 nathanw 121 1.1.2.2 nathanw int 122 1.1.2.2 nathanw irq_claim(irq, handler) 123 1.1.2.2 nathanw int irq; 124 1.1.2.2 nathanw irqhandler_t *handler; 125 1.1.2.2 nathanw { 126 1.1.2.2 nathanw int level; 127 1.1.2.2 nathanw int loop; 128 1.1.2.2 nathanw 129 1.1.2.2 nathanw #ifdef DIAGNOSTIC 130 1.1.2.2 nathanw /* Sanity check */ 131 1.1.2.2 nathanw if (handler == NULL) 132 1.1.2.3 nathanw panic("NULL interrupt handler"); 133 1.1.2.2 nathanw if (handler->ih_func == NULL) 134 1.1.2.3 nathanw panic("Interrupt handler does not have a function"); 135 1.1.2.2 nathanw #endif /* DIAGNOSTIC */ 136 1.1.2.2 nathanw 137 1.1.2.2 nathanw /* 138 1.1.2.2 nathanw * IRQ_INSTRUCT indicates that we should get the irq number 139 1.1.2.2 nathanw * from the irq structure 140 1.1.2.2 nathanw */ 141 1.1.2.2 nathanw if (irq == IRQ_INSTRUCT) 142 1.1.2.2 nathanw irq = handler->ih_num; 143 1.1.2.2 nathanw 144 1.1.2.2 nathanw /* Make sure the irq number is valid */ 145 1.1.2.2 nathanw if (irq < 0 || irq >= NIRQS) 146 1.1.2.2 nathanw return(-1); 147 1.1.2.2 nathanw 148 1.1.2.2 nathanw /* Make sure the level is valid */ 149 1.1.2.2 nathanw if (handler->ih_level < 0 || handler->ih_level >= IPL_LEVELS) 150 1.1.2.2 nathanw return(-1); 151 1.1.2.2 nathanw 152 1.1.2.2 nathanw /* Attach handler at top of chain */ 153 1.1.2.2 nathanw handler->ih_next = irqhandlers[irq]; 154 1.1.2.2 nathanw irqhandlers[irq] = handler; 155 1.1.2.2 nathanw 156 1.1.2.2 nathanw /* 157 1.1.2.2 nathanw * Reset the flags for this handler. 158 1.1.2.2 nathanw * As the handler is now in the chain mark it as active. 159 1.1.2.2 nathanw */ 160 1.1.2.2 nathanw handler->ih_flags = 0 | IRQ_FLAG_ACTIVE; 161 1.1.2.2 nathanw 162 1.1.2.2 nathanw /* 163 1.1.2.2 nathanw * Record the interrupt number for accounting. 164 1.1.2.2 nathanw * Done here as the accounting number may not be the same as the 165 1.1.2.2 nathanw * IRQ number though for the moment they are 166 1.1.2.2 nathanw */ 167 1.1.2.2 nathanw handler->ih_num = irq; 168 1.1.2.2 nathanw 169 1.1.2.2 nathanw #ifdef IRQSTATS 170 1.1.2.2 nathanw /* Get the interrupt name from the head of the list */ 171 1.1.2.2 nathanw if (handler->ih_name) { 172 1.1.2.2 nathanw char *ptr = _intrnames + (irq * 14); 173 1.1.2.2 nathanw strcpy(ptr, " "); 174 1.1.2.2 nathanw strncpy(ptr, handler->ih_name, 175 1.1.2.2 nathanw min(strlen(handler->ih_name), 13)); 176 1.1.2.2 nathanw } else { 177 1.1.2.2 nathanw char *ptr = _intrnames + (irq * 14); 178 1.1.2.2 nathanw sprintf(ptr, "irq %2d ", irq); 179 1.1.2.2 nathanw } 180 1.1.2.2 nathanw #endif /* IRQSTATS */ 181 1.1.2.2 nathanw 182 1.1.2.2 nathanw /* 183 1.1.2.2 nathanw * Update the irq masks. 184 1.1.2.2 nathanw * Find the lowest interrupt priority on the irq chain. 185 1.1.2.2 nathanw * Interrupt is allowable at priorities lower than this. 186 1.1.2.2 nathanw * If ih_level is out of range then don't bother to update 187 1.1.2.2 nathanw * the masks. 188 1.1.2.2 nathanw */ 189 1.1.2.2 nathanw if (handler->ih_level >= 0 && handler->ih_level < IPL_LEVELS) { 190 1.1.2.2 nathanw irqhandler_t *ptr; 191 1.1.2.2 nathanw 192 1.1.2.2 nathanw /* 193 1.1.2.2 nathanw * Find the lowest interrupt priority on the irq chain. 194 1.1.2.2 nathanw * Interrupt is allowable at priorities lower than this. 195 1.1.2.2 nathanw */ 196 1.1.2.2 nathanw ptr = irqhandlers[irq]; 197 1.1.2.2 nathanw if (ptr) { 198 1.1.2.2 nathanw level = ptr->ih_level - 1; 199 1.1.2.2 nathanw while (ptr) { 200 1.1.2.2 nathanw if (ptr->ih_level - 1 < level) 201 1.1.2.2 nathanw level = ptr->ih_level - 1; 202 1.1.2.2 nathanw ptr = ptr->ih_next; 203 1.1.2.2 nathanw } 204 1.1.2.2 nathanw while (level >= 0) { 205 1.1.2.2 nathanw irqmasks[level] |= (1 << irq); 206 1.1.2.2 nathanw --level; 207 1.1.2.2 nathanw } 208 1.1.2.2 nathanw } 209 1.1.2.2 nathanw 210 1.1.2.2 nathanw #include "sl.h" 211 1.1.2.2 nathanw #include "ppp.h" 212 1.1.2.2 nathanw #if NSL > 0 || NPPP > 0 213 1.1.2.2 nathanw /* In the presence of SLIP or PPP, splimp > spltty. */ 214 1.1.2.2 nathanw irqmasks[IPL_NET] &= irqmasks[IPL_TTY]; 215 1.1.2.2 nathanw #endif 216 1.1.2.2 nathanw } 217 1.1.2.2 nathanw 218 1.1.2.2 nathanw /* 219 1.1.2.2 nathanw * We now need to update the irqblock array. This array indicates 220 1.1.2.2 nathanw * what other interrupts should be blocked when interrupt is asserted 221 1.1.2.2 nathanw * This basically emulates hardware interrupt priorities e.g. by 222 1.1.2.2 nathanw * blocking all other IPL_BIO interrupts with an IPL_BIO interrupt 223 1.1.2.2 nathanw * is asserted. For each interrupt we find the highest IPL and set 224 1.1.2.2 nathanw * the block mask to the interrupt mask for that level. 225 1.1.2.2 nathanw */ 226 1.1.2.2 nathanw 227 1.1.2.2 nathanw for (loop = 0; loop < NIRQS; ++loop) { 228 1.1.2.2 nathanw irqhandler_t *ptr; 229 1.1.2.2 nathanw 230 1.1.2.2 nathanw ptr = irqhandlers[loop]; 231 1.1.2.2 nathanw if (ptr) { 232 1.1.2.2 nathanw /* There is at least 1 handler so scan the chain */ 233 1.1.2.2 nathanw level = ptr->ih_level; 234 1.1.2.2 nathanw while (ptr) { 235 1.1.2.2 nathanw if (ptr->ih_level > level) 236 1.1.2.2 nathanw level = ptr->ih_level; 237 1.1.2.2 nathanw ptr = ptr->ih_next; 238 1.1.2.2 nathanw } 239 1.1.2.2 nathanw irqblock[loop] = ~irqmasks[level]; 240 1.1.2.2 nathanw } else 241 1.1.2.2 nathanw /* No handlers for this irq so nothing to block */ 242 1.1.2.2 nathanw irqblock[loop] = 0; 243 1.1.2.2 nathanw } 244 1.1.2.2 nathanw 245 1.1.2.2 nathanw enable_irq(irq); 246 1.1.2.2 nathanw set_spl_masks(); 247 1.1.2.2 nathanw 248 1.1.2.2 nathanw return(0); 249 1.1.2.2 nathanw } 250 1.1.2.2 nathanw 251 1.1.2.2 nathanw 252 1.1.2.2 nathanw /* 253 1.1.2.2 nathanw * int irq_release(int irq, irqhandler_t *handler) 254 1.1.2.2 nathanw * 255 1.1.2.2 nathanw * Disable an IRQ and remove a handler for it. 256 1.1.2.2 nathanw */ 257 1.1.2.2 nathanw 258 1.1.2.2 nathanw int 259 1.1.2.2 nathanw irq_release(irq, handler) 260 1.1.2.2 nathanw int irq; 261 1.1.2.2 nathanw irqhandler_t *handler; 262 1.1.2.2 nathanw { 263 1.1.2.2 nathanw int level; 264 1.1.2.2 nathanw int loop; 265 1.1.2.2 nathanw irqhandler_t *irqhand; 266 1.1.2.2 nathanw irqhandler_t **prehand; 267 1.1.2.2 nathanw extern char *_intrnames; 268 1.1.2.2 nathanw 269 1.1.2.2 nathanw /* 270 1.1.2.2 nathanw * IRQ_INSTRUCT indicates that we should get the irq number 271 1.1.2.2 nathanw * from the irq structure 272 1.1.2.2 nathanw */ 273 1.1.2.2 nathanw if (irq == IRQ_INSTRUCT) 274 1.1.2.2 nathanw irq = handler->ih_num; 275 1.1.2.2 nathanw 276 1.1.2.2 nathanw /* Make sure the irq number is valid */ 277 1.1.2.2 nathanw if (irq < 0 || irq >= NIRQS) 278 1.1.2.2 nathanw return(-1); 279 1.1.2.2 nathanw 280 1.1.2.2 nathanw /* Locate the handler */ 281 1.1.2.2 nathanw irqhand = irqhandlers[irq]; 282 1.1.2.2 nathanw prehand = &irqhandlers[irq]; 283 1.1.2.2 nathanw 284 1.1.2.2 nathanw while (irqhand && handler != irqhand) { 285 1.1.2.2 nathanw prehand = &irqhand; 286 1.1.2.2 nathanw irqhand = irqhand->ih_next; 287 1.1.2.2 nathanw } 288 1.1.2.2 nathanw 289 1.1.2.2 nathanw /* Remove the handler if located */ 290 1.1.2.2 nathanw if (irqhand) 291 1.1.2.2 nathanw *prehand = irqhand->ih_next; 292 1.1.2.2 nathanw else 293 1.1.2.2 nathanw return(-1); 294 1.1.2.2 nathanw 295 1.1.2.2 nathanw /* Now the handler has been removed from the chain mark is as inactive */ 296 1.1.2.2 nathanw irqhand->ih_flags &= ~IRQ_FLAG_ACTIVE; 297 1.1.2.2 nathanw 298 1.1.2.2 nathanw /* Make sure the head of the handler list is active */ 299 1.1.2.2 nathanw if (irqhandlers[irq]) 300 1.1.2.2 nathanw irqhandlers[irq]->ih_flags |= IRQ_FLAG_ACTIVE; 301 1.1.2.2 nathanw 302 1.1.2.2 nathanw #ifdef IRQSTATS 303 1.1.2.2 nathanw /* Get the interrupt name from the head of the list */ 304 1.1.2.2 nathanw if (irqhandlers[irq] && irqhandlers[irq]->ih_name) { 305 1.1.2.2 nathanw char *ptr = _intrnames + (irq * 14); 306 1.1.2.2 nathanw strcpy(ptr, " "); 307 1.1.2.2 nathanw strncpy(ptr, irqhandlers[irq]->ih_name, 308 1.1.2.2 nathanw min(strlen(irqhandlers[irq]->ih_name), 13)); 309 1.1.2.2 nathanw } else { 310 1.1.2.2 nathanw char *ptr = _intrnames + (irq * 14); 311 1.1.2.2 nathanw sprintf(ptr, "irq %2d ", irq); 312 1.1.2.2 nathanw } 313 1.1.2.2 nathanw #endif /* IRQSTATS */ 314 1.1.2.2 nathanw 315 1.1.2.2 nathanw /* 316 1.1.2.2 nathanw * Update the irq masks. 317 1.1.2.2 nathanw * If ih_level is out of range then don't bother to update 318 1.1.2.2 nathanw * the masks. 319 1.1.2.2 nathanw */ 320 1.1.2.2 nathanw if (handler->ih_level >= 0 && handler->ih_level < IPL_LEVELS) { 321 1.1.2.2 nathanw irqhandler_t *ptr; 322 1.1.2.2 nathanw 323 1.1.2.2 nathanw /* Clean the bit from all the masks */ 324 1.1.2.2 nathanw for (level = 0; level < IPL_LEVELS; ++level) 325 1.1.2.2 nathanw irqmasks[level] &= ~(1 << irq); 326 1.1.2.2 nathanw 327 1.1.2.2 nathanw /* 328 1.1.2.2 nathanw * Find the lowest interrupt priority on the irq chain. 329 1.1.2.2 nathanw * Interrupt is allowable at priorities lower than this. 330 1.1.2.2 nathanw */ 331 1.1.2.2 nathanw ptr = irqhandlers[irq]; 332 1.1.2.2 nathanw if (ptr) { 333 1.1.2.2 nathanw level = ptr->ih_level - 1; 334 1.1.2.2 nathanw while (ptr) { 335 1.1.2.2 nathanw if (ptr->ih_level - 1 < level) 336 1.1.2.2 nathanw level = ptr->ih_level - 1; 337 1.1.2.2 nathanw ptr = ptr->ih_next; 338 1.1.2.2 nathanw } 339 1.1.2.2 nathanw while (level >= 0) { 340 1.1.2.2 nathanw irqmasks[level] |= (1 << irq); 341 1.1.2.2 nathanw --level; 342 1.1.2.2 nathanw } 343 1.1.2.2 nathanw } 344 1.1.2.2 nathanw } 345 1.1.2.2 nathanw 346 1.1.2.2 nathanw /* 347 1.1.2.2 nathanw * We now need to update the irqblock array. This array indicates 348 1.1.2.2 nathanw * what other interrupts should be blocked when interrupt is asserted 349 1.1.2.2 nathanw * This basically emulates hardware interrupt priorities e.g. by 350 1.1.2.2 nathanw * blocking all other IPL_BIO interrupts with an IPL_BIO interrupt 351 1.1.2.2 nathanw * is asserted. For each interrupt we find the highest IPL and set 352 1.1.2.2 nathanw * the block mask to the interrupt mask for that level. 353 1.1.2.2 nathanw */ 354 1.1.2.2 nathanw for (loop = 0; loop < NIRQS; ++loop) { 355 1.1.2.2 nathanw irqhandler_t *ptr; 356 1.1.2.2 nathanw 357 1.1.2.2 nathanw ptr = irqhandlers[loop]; 358 1.1.2.2 nathanw if (ptr) { 359 1.1.2.2 nathanw /* There is at least 1 handler so scan the chain */ 360 1.1.2.2 nathanw level = ptr->ih_level; 361 1.1.2.2 nathanw while (ptr) { 362 1.1.2.2 nathanw if (ptr->ih_level > level) 363 1.1.2.2 nathanw level = ptr->ih_level; 364 1.1.2.2 nathanw ptr = ptr->ih_next; 365 1.1.2.2 nathanw } 366 1.1.2.2 nathanw irqblock[loop] = ~irqmasks[level]; 367 1.1.2.2 nathanw } else 368 1.1.2.2 nathanw /* No handlers for this irq so nothing to block */ 369 1.1.2.2 nathanw irqblock[loop] = 0; 370 1.1.2.2 nathanw } 371 1.1.2.2 nathanw 372 1.1.2.2 nathanw /* 373 1.1.2.2 nathanw * Disable the appropriate mask bit if there are no handlers left for 374 1.1.2.2 nathanw * this IRQ. 375 1.1.2.2 nathanw */ 376 1.1.2.2 nathanw if (irqhandlers[irq] == NULL) 377 1.1.2.2 nathanw disable_irq(irq); 378 1.1.2.2 nathanw 379 1.1.2.2 nathanw set_spl_masks(); 380 1.1.2.2 nathanw 381 1.1.2.2 nathanw return(0); 382 1.1.2.2 nathanw } 383 1.1.2.2 nathanw 384 1.1.2.2 nathanw 385 1.1.2.2 nathanw void * 386 1.1.2.2 nathanw intr_claim(irq, level, name, ih_func, ih_arg) 387 1.1.2.2 nathanw int irq; 388 1.1.2.2 nathanw int level; 389 1.1.2.2 nathanw const char *name; 390 1.1.2.2 nathanw int (*ih_func) __P((void *)); 391 1.1.2.2 nathanw void *ih_arg; 392 1.1.2.2 nathanw { 393 1.1.2.2 nathanw irqhandler_t *ih; 394 1.1.2.2 nathanw 395 1.1.2.2 nathanw ih = malloc(sizeof(*ih), M_DEVBUF, M_NOWAIT); 396 1.1.2.2 nathanw if (!ih) 397 1.1.2.3 nathanw panic("intr_claim(): Cannot malloc handler memory"); 398 1.1.2.2 nathanw 399 1.1.2.2 nathanw ih->ih_level = level; 400 1.1.2.2 nathanw ih->ih_name = name; 401 1.1.2.2 nathanw ih->ih_func = ih_func; 402 1.1.2.2 nathanw ih->ih_arg = ih_arg; 403 1.1.2.2 nathanw ih->ih_flags = 0; 404 1.1.2.2 nathanw 405 1.1.2.2 nathanw if (irq_claim(irq, ih) != 0) 406 1.1.2.2 nathanw return(NULL); 407 1.1.2.2 nathanw return(ih); 408 1.1.2.2 nathanw } 409 1.1.2.2 nathanw 410 1.1.2.2 nathanw 411 1.1.2.2 nathanw int 412 1.1.2.2 nathanw intr_release(arg) 413 1.1.2.2 nathanw void *arg; 414 1.1.2.2 nathanw { 415 1.1.2.2 nathanw irqhandler_t *ih = (irqhandler_t *)arg; 416 1.1.2.2 nathanw 417 1.1.2.2 nathanw if (irq_release(ih->ih_num, ih) == 0) { 418 1.1.2.2 nathanw free(ih, M_DEVBUF); 419 1.1.2.2 nathanw return(0); 420 1.1.2.2 nathanw } 421 1.1.2.2 nathanw return(1); 422 1.1.2.2 nathanw } 423 1.1.2.2 nathanw 424 1.1.2.2 nathanw 425 1.1.2.2 nathanw /* 426 1.1.2.2 nathanw * void disable_irq(int irq) 427 1.1.2.2 nathanw * 428 1.1.2.2 nathanw * Disables a specific irq. The irq is removed from the master irq mask 429 1.1.2.2 nathanw */ 430 1.1.2.2 nathanw 431 1.1.2.2 nathanw void 432 1.1.2.2 nathanw disable_irq(irq) 433 1.1.2.2 nathanw int irq; 434 1.1.2.2 nathanw { 435 1.1.2.2 nathanw register int oldirqstate; 436 1.1.2.2 nathanw 437 1.1.2.2 nathanw oldirqstate = disable_interrupts(I32_bit); 438 1.1.2.2 nathanw current_mask &= ~(1 << irq); 439 1.1.2.2 nathanw irq_setmasks(); 440 1.1.2.2 nathanw restore_interrupts(oldirqstate); 441 1.1.2.2 nathanw } 442 1.1.2.2 nathanw 443 1.1.2.2 nathanw 444 1.1.2.2 nathanw /* 445 1.1.2.2 nathanw * void enable_irq(int irq) 446 1.1.2.2 nathanw * 447 1.1.2.2 nathanw * Enables a specific irq. The irq is added to the master irq mask 448 1.1.2.2 nathanw * This routine should be used with caution. A handler should already 449 1.1.2.2 nathanw * be installed. 450 1.1.2.2 nathanw */ 451 1.1.2.2 nathanw 452 1.1.2.2 nathanw void 453 1.1.2.2 nathanw enable_irq(irq) 454 1.1.2.2 nathanw int irq; 455 1.1.2.2 nathanw { 456 1.1.2.2 nathanw register u_int oldirqstate; 457 1.1.2.2 nathanw 458 1.1.2.2 nathanw oldirqstate = disable_interrupts(I32_bit); 459 1.1.2.2 nathanw current_mask |= (1 << irq); 460 1.1.2.2 nathanw irq_setmasks(); 461 1.1.2.2 nathanw restore_interrupts(oldirqstate); 462 1.1.2.2 nathanw } 463 1.1.2.2 nathanw 464 1.1.2.2 nathanw 465 1.1.2.2 nathanw /* 466 1.1.2.2 nathanw * void stray_irqhandler(u_int mask) 467 1.1.2.2 nathanw * 468 1.1.2.2 nathanw * Handler for stray interrupts. This gets called if a handler cannot be 469 1.1.2.2 nathanw * found for an interrupt. 470 1.1.2.2 nathanw */ 471 1.1.2.2 nathanw 472 1.1.2.2 nathanw void 473 1.1.2.2 nathanw stray_irqhandler(mask) 474 1.1.2.2 nathanw u_int mask; 475 1.1.2.2 nathanw { 476 1.1.2.2 nathanw static u_int stray_irqs = 0; 477 1.1.2.2 nathanw 478 1.1.2.2 nathanw if (++stray_irqs <= 8) 479 1.1.2.2 nathanw log(LOG_ERR, "Stray interrupt %08x%s\n", mask, 480 1.1.2.2 nathanw stray_irqs >= 8 ? ": stopped logging" : ""); 481 1.1.2.2 nathanw } 482
Indexes created Wed Oct 01 07:09:59 GMT 2025