rk3288_cru.c revision 1.1
1 /* $NetBSD: rk3288_cru.c,v 1.1 2021/11/12 22:02:08 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2021 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 31 __KERNEL_RCSID(1, "$NetBSD: rk3288_cru.c,v 1.1 2021/11/12 22:02:08 jmcneill Exp $"); 32 33 #include <sys/param.h> 34 #include <sys/bus.h> 35 #include <sys/device.h> 36 #include <sys/systm.h> 37 38 #include <dev/fdt/fdtvar.h> 39 40 #include <arm/rockchip/rk_cru.h> 41 #include <arm/rockchip/rk3288_cru.h> 42 43 #define PLL_CON(n) (0x0000 + (n) * 4) 44 #define MODE_CON 0x0050 45 #define CLKSEL_CON(n) (0x0060 + (n) * 4) 46 #define CLKGATE_CON(n) (0x0160 + (n) * 4) 47 #define SOFTRST_CON(n) (0x01b8 + (n) * 4) 48 49 #define GRF_SOC_CON4 0x0410 50 #define GRF_MAC_CON1 0x0904 51 52 static int rk3288_cru_match(device_t, cfdata_t, void *); 53 static void rk3288_cru_attach(device_t, device_t, void *); 54 55 static const struct device_compatible_entry compat_data[] = { 56 { .compat = "rockchip,rk3288-cru" }, 57 DEVICE_COMPAT_EOL 58 }; 59 60 CFATTACH_DECL_NEW(rk3288_cru, sizeof(struct rk_cru_softc), 61 rk3288_cru_match, rk3288_cru_attach, NULL, NULL); 62 63 static const char * pll_parents[] = { "xin24m" }; 64 static const char * aclk_cpu_src_parents[] = { "cpll_aclk_cpu", "gpll_aclk_cpu" }; 65 static const char * uart0_parents[] = { "clk_uart0_div", "clk_uart0_frac", "xin24m" }; 66 static const char * uart1_parents[] = { "clk_uart1_div", "clk_uart1_frac", "xin24m" }; 67 static const char * uart2_parents[] = { "clk_uart2_div", "clk_uart2_frac", "xin24m" }; 68 static const char * uart3_parents[] = { "clk_uart3_div", "clk_uart3_frac", "xin24m" }; 69 static const char * uart4_parents[] = { "clk_uart4_div", "clk_uart4_frac", "xin24m" }; 70 static const char * mmc_parents[] = { "cpll", "gpll", "xin24m", "xin24m" }; 71 static const char * mac_parents[] = { "mac_pll_src", "ext_gmac" }; 72 static const char * mux_2plls_parents[] = { "cpll", "gpll" }; 73 static const char * mux_npll_cpll_gpll_parents[] = { "npll", "cpll", "gpll" }; 74 static const char * mux_3plls_usb_parents[] = { "cpll", "gpll", "usbphy480m_src", "npll" }; 75 76 static struct rk_cru_pll_rate rk3288_pll_rates[] = { 77 /* TODO */ 78 }; 79 80 static struct rk_cru_clk rk3288_cru_clks[] = { 81 RK3288_PLL(RK3288_PLL_CPLL, "cpll", pll_parents, 82 PLL_CON(8), /* con_base */ 83 MODE_CON, /* mode_reg */ 84 __BIT(8), /* mode_mask */ 85 __BIT(2), /* lock_mask */ 86 rk3288_pll_rates), 87 RK3288_PLL(RK3288_PLL_GPLL, "gpll", pll_parents, 88 PLL_CON(12), /* con_base */ 89 MODE_CON, /* mode_reg */ 90 __BIT(12), /* mode_mask */ 91 __BIT(3), /* lock_mask */ 92 rk3288_pll_rates), 93 RK3288_PLL(RK3288_PLL_NPLL, "npll", pll_parents, 94 PLL_CON(16), /* con_base */ 95 MODE_CON, /* mode_reg */ 96 __BIT(14), /* mode_mask */ 97 __BIT(4), /* lock_mask */ 98 rk3288_pll_rates), 99 100 RK_COMPOSITE_NOGATE(0, "aclk_cpu_src", aclk_cpu_src_parents, 101 CLKSEL_CON(1), /* muxdiv_reg */ 102 __BIT(15), /* mux_mask */ 103 __BITS(7,3), /* div_mask */ 104 0), 105 RK_COMPOSITE_NOMUX(RK3288_PCLK_CPU, "pclk_cpu", "aclk_cpu_pre", 106 CLKSEL_CON(1), /* div_reg */ 107 __BITS(14,12), /* div_mask */ 108 CLKGATE_CON(0), /* gate_reg */ 109 __BIT(5), /* gate_mask */ 110 0), 111 RK_COMPOSITE_NOMUX(RK3288_HCLK_PERI, "hclk_peri", "aclk_peri_src", 112 CLKSEL_CON(10), /* div_reg */ 113 __BITS(9,8), /* div_mask */ 114 CLKGATE_CON(2), /* gate_reg */ 115 __BIT(2), /* gate_mask */ 116 RK_COMPOSITE_POW2), 117 RK_COMPOSITE(0, "aclk_peri_src", mux_2plls_parents, 118 CLKSEL_CON(10), /* muxdiv_reg */ 119 __BIT(15), /* mux_mask */ 120 __BITS(4,0), /* div_mask */ 121 CLKGATE_CON(2), /* gate_reg */ 122 __BIT(0), /* gate_mask */ 123 0), 124 RK_COMPOSITE_NOMUX(0, "pclk_pd_pmu", "gpll", 125 CLKSEL_CON(33), /* div_reg */ 126 __BITS(4,0), /* div_mask */ 127 CLKGATE_CON(5), /* gate_reg */ 128 __BIT(8), /* gate_mask */ 129 0), 130 RK_COMPOSITE_NOMUX(RK3288_PCLK_PERI, "pclk_peri", "aclk_peri_src", 131 CLKSEL_CON(10), /* div_reg */ 132 __BITS(13,12), /* div_mask */ 133 CLKGATE_CON(2), /* gate_reg */ 134 __BIT(3), /* gate_mask */ 135 0), 136 137 /* UARTs */ 138 RK_COMPOSITE(0, "clk_uart0_div", mux_3plls_usb_parents, 139 CLKSEL_CON(13), /* muxdiv_reg */ 140 __BITS(14,13), /* mux_mask */ 141 __BITS(6,0), /* div_mask */ 142 CLKGATE_CON(1), /* gate_reg */ 143 __BIT(8), /* gate_mask */ 144 0), 145 /* XXX TODO: CRU_CLKGATE1_CON bit 9 (clk_uart0_frac_src_gate_en) */ 146 RK_COMPOSITE_FRAC(0, "clk_uart0_frac", "clk_uart0_div", 147 CLKSEL_CON(17), /* fracdiv_reg */ 148 0), 149 RK_COMPOSITE_NOMUX(0, "clk_uart1_div", "uart_src", 150 CLKSEL_CON(14), /* div_reg */ 151 __BITS(6,0), /* div_mask */ 152 CLKGATE_CON(1), /* gate_reg */ 153 __BIT(10), /* gate_mask */ 154 0), 155 /* XXX TODO: CRU_CLKGATE1_CON bit 11 (clk_uart1_frac_src_gate_en) */ 156 RK_COMPOSITE_FRAC(0, "clk_uart1_frac", "clk_uart1_div", 157 CLKSEL_CON(18), /* fracdiv_reg */ 158 0), 159 RK_COMPOSITE_NOMUX(0, "clk_uart2_div", "uart_src", 160 CLKSEL_CON(15), /* div_reg */ 161 __BITS(6,0), /* div_mask */ 162 CLKGATE_CON(1), /* gate_reg */ 163 __BIT(12), /* gate_mask */ 164 0), 165 /* XXX TODO: CRU_CLKGATE1_CON bit 13 (clk_uart2_frac_src_gate_en) */ 166 RK_COMPOSITE_FRAC(0, "clk_uart2_frac", "clk_uart2_div", 167 CLKSEL_CON(19), /* fracdiv_reg */ 168 0), 169 RK_COMPOSITE_NOMUX(0, "clk_uart3_div", "uart_src", 170 CLKSEL_CON(16), /* div_reg */ 171 __BITS(6,0), /* div_mask */ 172 CLKGATE_CON(1), /* gate_reg */ 173 __BIT(14), /* gate_mask */ 174 0), 175 /* XXX TODO: CRU_CLKGATE1_CON bit 15 (clk_uart3_frac_src_gate_en) */ 176 RK_COMPOSITE_FRAC(0, "clk_uart3_frac", "clk_uart3_div", 177 CLKSEL_CON(20), /* fracdiv_reg */ 178 0), 179 RK_COMPOSITE_NOMUX(0, "clk_uart4_div", "uart_src", 180 CLKSEL_CON(3), /* div_reg */ 181 __BITS(6,0), /* div_mask */ 182 CLKGATE_CON(2), /* gate_reg */ 183 __BIT(12), /* gate_mask */ 184 0), 185 /* XXX TODO: CRU_CLKGATE2_CON bit 13 (clk_uart4_frac_src_gate_en) */ 186 RK_COMPOSITE_FRAC(0, "clk_uart4_frac", "clk_uart4_div", 187 CLKSEL_CON(7), /* fracdiv_reg */ 188 0), 189 190 /* SD/eMMC/SDIO */ 191 RK_COMPOSITE(RK3288_SCLK_SDMMC, "sclk_sdmmc", mmc_parents, 192 CLKSEL_CON(11), /* muxdiv_reg */ 193 __BITS(7,6), /* mux_mask */ 194 __BITS(5,0), /* div_mask */ 195 CLKGATE_CON(13), /* gate_reg */ 196 __BIT(0), /* gate_mask */ 197 0), 198 RK_COMPOSITE(RK3288_SCLK_SDIO0, "sclk_sdio0", mmc_parents, 199 CLKSEL_CON(12), /* muxdiv_reg */ 200 __BITS(7,6), /* mux_mask */ 201 __BITS(5,0), /* div_mask */ 202 CLKGATE_CON(13), /* gate_reg */ 203 __BIT(1), /* gate_mask */ 204 0), 205 RK_COMPOSITE(RK3288_SCLK_SDIO1, "sclk_sdio1", mmc_parents, 206 CLKSEL_CON(34), /* muxdiv_reg */ 207 __BITS(15,14), /* mux_mask */ 208 __BITS(13,8), /* div_mask */ 209 CLKGATE_CON(13), /* gate_reg */ 210 __BIT(2), /* gate_mask */ 211 0), 212 RK_COMPOSITE(RK3288_SCLK_EMMC, "sclk_emmc", mmc_parents, 213 CLKSEL_CON(12), /* muxdiv_reg */ 214 __BITS(15,14), /* mux_mask */ 215 __BITS(13,8), /* div_mask */ 216 CLKGATE_CON(13), /* gate_reg */ 217 __BIT(3), /* gate_mask */ 218 0), 219 220 /* MAC */ 221 RK_COMPOSITE(0, "mac_pll_src", mux_npll_cpll_gpll_parents, 222 CLKSEL_CON(21), /* muxdiv_reg */ 223 __BITS(1,0), /* mux_mask */ 224 __BITS(12,8), /* div_mask */ 225 CLKGATE_CON(2), /* gate_reg */ 226 __BIT(5), /* gate_mask */ 227 0), 228 229 RK_DIV(0, "aclk_cpu_pre", "aclk_cpu_src", CLKSEL_CON(1), __BITS(3,0), 0), 230 RK_DIV(0, "clk_24m", "xin24m", CLKSEL_CON(2), __BITS(12,8), 0), 231 RK_DIV(0, "pclk_pd_alive", "gpll", CLKSEL_CON(33), __BITS(12,8), 0), 232 233 RK_MUX(RK3288_SCLK_UART0, "sclk_uart0", uart0_parents, CLKSEL_CON(13), __BITS(9,8)), 234 RK_MUX(RK3288_SCLK_UART1, "sclk_uart1", uart1_parents, CLKSEL_CON(14), __BITS(9,8)), 235 RK_MUX(RK3288_SCLK_UART2, "sclk_uart2", uart2_parents, CLKSEL_CON(15), __BITS(9,8)), 236 RK_MUX(RK3288_SCLK_UART3, "sclk_uart3", uart3_parents, CLKSEL_CON(16), __BITS(9,8)), 237 RK_MUX(RK3288_SCLK_UART4, "sclk_uart4", uart4_parents, CLKSEL_CON(3), __BITS(9,8)), 238 RK_MUX(0, "uart_src", mux_2plls_parents, CLKSEL_CON(15), __BIT(15)), 239 RK_MUX(RK3288_SCLK_MAC, "mac_clk", mac_parents, CLKSEL_CON(21), __BIT(4)), 240 241 RK_GATE(0, "gpll_aclk_cpu", "gpll", CLKGATE_CON(0), 10), 242 RK_GATE(0, "cpll_aclk_cpu", "cpll", CLKGATE_CON(0), 11), 243 RK_GATE(RK3288_ACLK_PERI, "aclk_peri", "aclk_peri_src", CLKGATE_CON(2), 1), 244 RK_GATE(RK3288_SCLK_MAC_RX, "sclk_mac_rx", "mac_clk", CLKGATE_CON(5), 0), 245 RK_GATE(RK3288_SCLK_MAC_TX, "sclk_mac_tx", "mac_clk", CLKGATE_CON(5), 1), 246 RK_GATE(RK3288_SCLK_MACREF, "sclk_macref", "mac_clk", CLKGATE_CON(5), 2), 247 RK_GATE(RK3288_SCLK_MACREF_OUT, "sclk_macref_out", "mac_clk", CLKGATE_CON(5), 3), 248 RK_GATE(RK3288_PCLK_I2C1, "pclk_i2c1", "pclk_peri", CLKGATE_CON(6), 13), 249 RK_GATE(RK3288_PCLK_I2C3, "pclk_i2c3", "pclk_peri", CLKGATE_CON(6), 14), 250 RK_GATE(RK3288_PCLK_I2C4, "pclk_i2c4", "pclk_peri", CLKGATE_CON(6), 15), 251 RK_GATE(RK3288_PCLK_I2C5, "pclk_i2c5", "pclk_peri", CLKGATE_CON(7), 0), 252 RK_GATE(RK3288_HCLK_USBHOST0, "hclk_host0", "hclk_peri", CLKGATE_CON(7), 6), 253 RK_GATE(RK3288_HCLK_USBHOST1, "hclk_host1", "hclk_peri", CLKGATE_CON(7), 7), 254 RK_GATE(RK3288_HCLK_HSIC, "hclk_hsic", "hclk_peri", CLKGATE_CON(7), 8), 255 RK_GATE(RK3288_PCLK_GMAC, "pclk_gmac", "pclk_peri", CLKGATE_CON(8), 1), 256 RK_GATE(RK3288_HCLK_SDMMC, "hclk_sdmmc", "hclk_peri", CLKGATE_CON(8), 3), 257 RK_GATE(RK3288_HCLK_SDIO0, "hclk_sdio0", "hclk_peri", CLKGATE_CON(8), 4), 258 RK_GATE(RK3288_HCLK_SDIO1, "hclk_sdio1", "hclk_peri", CLKGATE_CON(8), 5), 259 RK_GATE(RK3288_ACLK_GMAC, "aclk_gmac", "aclk_peri", CLKGATE_CON(8), 0), 260 RK_GATE(RK3288_HCLK_EMMC, "hclk_emmc", "hclk_peri", CLKGATE_CON(8), 6), 261 RK_GATE(RK3288_PCLK_I2C0, "pclk_i2c0", "pclk_cpu", CLKGATE_CON(10), 2), 262 RK_GATE(RK3288_PCLK_I2C2, "pclk_i2c2", "pclk_cpu", CLKGATE_CON(10), 3), 263 RK_GATE(RK3288_PCLK_UART2, "pclk_uart2", "pclk_cpu", CLKGATE_CON(11), 9), 264 RK_GATE(RK3288_SCLK_OTGPHY0, "sclk_otgphy0", "xin24m", CLKGATE_CON(13), 4), 265 RK_GATE(RK3288_SCLK_OTGPHY1, "sclk_otgphy1", "xin24m", CLKGATE_CON(13), 5), 266 RK_GATE(RK3288_SCLK_OTGPHY2, "sclk_otgphy2", "xin24m", CLKGATE_CON(13), 6), 267 RK_GATE(RK3288_PCLK_GPIO1, "pclk_gpio1", "pclk_pd_alive", CLKGATE_CON(14), 1), 268 RK_GATE(RK3288_PCLK_GPIO2, "pclk_gpio2", "pclk_pd_alive", CLKGATE_CON(14), 2), 269 RK_GATE(RK3288_PCLK_GPIO3, "pclk_gpio3", "pclk_pd_alive", CLKGATE_CON(14), 3), 270 RK_GATE(RK3288_PCLK_GPIO4, "pclk_gpio4", "pclk_pd_alive", CLKGATE_CON(14), 4), 271 RK_GATE(RK3288_PCLK_GPIO5, "pclk_gpio5", "pclk_pd_alive", CLKGATE_CON(14), 5), 272 RK_GATE(RK3288_PCLK_GPIO6, "pclk_gpio6", "pclk_pd_alive", CLKGATE_CON(14), 6), 273 RK_GATE(RK3288_PCLK_GPIO7, "pclk_gpio7", "pclk_pd_alive", CLKGATE_CON(14), 7), 274 RK_GATE(RK3288_PCLK_GPIO8, "pclk_gpio8", "pclk_pd_alive", CLKGATE_CON(14), 8), 275 RK_GATE(RK3288_PCLK_GPIO0, "pclk_gpio0", "pclk_pd_pmu", CLKGATE_CON(17), 4), 276 }; 277 278 static int 279 rk3288_cru_match(device_t parent, cfdata_t cf, void *aux) 280 { 281 struct fdt_attach_args * const faa = aux; 282 283 return of_compatible_match(faa->faa_phandle, compat_data); 284 } 285 286 static void 287 rk3288_cru_attach(device_t parent, device_t self, void *aux) 288 { 289 struct rk_cru_softc * const sc = device_private(self); 290 struct fdt_attach_args * const faa = aux; 291 292 sc->sc_dev = self; 293 sc->sc_phandle = faa->faa_phandle; 294 sc->sc_bst = faa->faa_bst; 295 296 sc->sc_clks = rk3288_cru_clks; 297 sc->sc_nclks = __arraycount(rk3288_cru_clks); 298 299 sc->sc_grf_soc_status = 0x0284; 300 sc->sc_softrst_base = SOFTRST_CON(0); 301 302 if (rk_cru_attach(sc) != 0) 303 return; 304 305 aprint_naive("\n"); 306 aprint_normal(": RK3288 CRU\n"); 307 308 rk_cru_print(sc); 309 } 310
Indexes created Tue Sep 30 11:09:46 GMT 2025