rk3399_pcie.c revision 1.1.4.2
1 /* $NetBSD: rk3399_pcie.c,v 1.1.4.2 2019/06/10 22:05:55 christos Exp $ */ 2 /* 3 * Copyright (c) 2018 Mark Kettenis <kettenis (at) openbsd.org> 4 * 5 * Permission to use, copy, modify, and distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 */ 17 18 #include <sys/cdefs.h> 19 20 __KERNEL_RCSID(1, "$NetBSD: rk3399_pcie.c,v 1.1.4.2 2019/06/10 22:05:55 christos Exp $"); 21 22 #include <sys/param.h> 23 #include <sys/systm.h> 24 #include <sys/bitops.h> 25 #include <sys/device.h> 26 #include <sys/extent.h> 27 #include <sys/kmem.h> 28 29 #include <machine/intr.h> 30 #include <sys/bus.h> 31 #include <dev/fdt/fdtvar.h> 32 #include <dev/fdt/syscon.h> 33 #include <arm/cpufunc.h> 34 35 #include <dev/pci/pcidevs.h> 36 #include <dev/pci/pcireg.h> 37 #include <dev/pci/pcivar.h> 38 #include <dev/pci/pciconf.h> 39 40 #include <arm/fdt/pcihost_fdtvar.h> 41 #include <sys/gpio.h> 42 43 #define SETREG(m, v) ((m)<<16|__SHIFTIN((v), (m))) 44 #define GETREG(m, v) (__SHIFTOUT((v), (m))) 45 46 /* APB region */ 47 #define PCIE_CLIENT_BASE 0x000000 48 #define PCIE_CLIENT_BASIC_STRAP_CONF 0x0000 49 #define PCBSC_PCIE_GEN_SEL __BIT(7) 50 #define PCBSC_PGS_GEN1 SETREG(PCBSC_PCIE_GEN_SEL, 0) 51 #define PCBSC_PGS_GEN2 SETREG(PCBSC_PCIE_GEN_SEL, 1) 52 #define PCBSC_MODE_SELECT __BIT(6) 53 #define PCBSC_MS_ENDPOINT SETREG(PCBSC_MODE_SELECT, 0) 54 #define PCBSC_MS_ROOTPORT SETREG(PCBSC_MODE_SELECT, 1) 55 #define PCBSC_LANE_COUNT __BITS(5,4) 56 #define PCBSC_LC(x) SETREG(PCBSC_LANE_COUNT, ilog2(x)) /* valid for x1,2,4 */ 57 #define PCBSC_ARI_EN SETREG(__BIT(3), 1) /* Alternate Routing ID Enable */ 58 #define PCBSC_SR_IOV_EN SETREG(__BIT(2), 1) 59 #define PCBSC_LINK_TRAIN_EN SETREG(__BIT(1), 1) 60 #define PCBSC_CONF_EN SETREG(__BIT(0), 1) /* Config enable */ 61 #define PCIE_CLIENT_DEBUG_OUT_0 0x003c 62 #define PCIE_CLIENT_DEBUG_OUT_1 0x0040 63 #define PCIE_CLIENT_BASIC_STATUS0 0x0044 64 #define PCIE_CLIENT_BASIC_STATUS1 0x0048 65 #define PCBS1_LINK_ST(x) (u_int)__SHIFTOUT((x), __BITS(21,20)) 66 #define PCBS1_LS_NO_RECV 0 /* no receivers */ 67 #define PCBS1_LS_TRAINING 1 /* link training */ 68 #define PCBS1_LS_DL_INIT 2 /* link up, DL init progressing */ 69 #define PCBS1_LS_DL_DONE 3 /* link up, DL init complete */ 70 #define PCIE_CLIENT_INT_MASK 0x004c 71 #define PCIM_INTx_MASK(x) SETREG(__BIT((x)+5), 1) 72 #define PCIM_INTx_ENAB(x) SETREG(__BIT((x)+5), 0) 73 74 #define PCIE_CORE_BASE 0x800000 75 #define PCIE_RC_NORMAL_BASE (PCIE_CORE_BASE + 0x00000) 76 77 #define PCIE_LM_BASE 0x900000 78 #define PCIE_LM_CORE_CTRL (PCIE_LM_BASE + 0x00) 79 #define PCIE_CORE_PL_CONF_SPEED_5G 0x00000008 80 #define PCIE_CORE_PL_CONF_SPEED_MASK 0x00000018 81 #define PCIE_CORE_PL_CONF_LANE_MASK 0x00000006 82 #define PCIE_CORE_PL_CONF_LANE_SHIFT 1 83 #define PCIE_LM_PLC1 (PCIE_LM_BASE + 0x04) 84 #define PCIE_LM_PLC1_FTS_MASK __BITS(23, 8) 85 #define PCIE_LM_VENDOR_ID (PCIE_LM_BASE + 0x44) 86 #define PCIE_LM_LINKWIDTH (PCIE_LM_BASE + 0x50) 87 #define PCIE_LM_LANEMAP (PCIE_LM_BASE + 0x200) 88 #define PCIE_LM_DEBUG_MUX_CONTROL (PCIE_LM_BASE + 0x208) 89 #define PCIE_LM_RCBAR (PCIE_LM_BASE + 0x300) 90 #define PCIE_LM_RCBARPME __BIT(17) 91 #define PCIE_LM_RCBARPMS __BIT(18) 92 #define PCIE_LM_RCBARPIE __BIT(19) 93 #define PCIE_LM_RCBARPIS __BIT(20) 94 95 #define PCIE_RC_BASE 0xa00000 96 #define PCIE_RC_CONFIG_DCSR (PCIE_RC_BASE + 0x0c0 + PCIE_DCSR) 97 #define PCIE_RC_PCIE_LCAP (PCIE_RC_BASE + 0x0c0 + PCIE_LCAP) 98 #define PCIE_RC_CONFIG_LCSR (PCIE_RC_BASE + 0x0c0 + PCIE_LCSR) 99 #define PCIE_RC_CONFIG_THP_CAP (PCIE_RC_BASE + 0x274) 100 #define PCIE_RC_CONFIG_THP_CAP_NEXT_MASK __BITS(31, 20) 101 102 103 #define PCIE_ATR_BASE 0xc00000 104 #define PCIE_ATR_OB_ADDR0(i) (PCIE_ATR_BASE + 0x000 + (i) * 0x20) 105 #define PCIE_ATR_OB_ADDR1(i) (PCIE_ATR_BASE + 0x004 + (i) * 0x20) 106 #define PCIE_ATR_OB_DESC0(i) (PCIE_ATR_BASE + 0x008 + (i) * 0x20) 107 #define PCIE_ATR_OB_DESC1(i) (PCIE_ATR_BASE + 0x00c + (i) * 0x20) 108 #define PCIE_ATR_IB_ADDR0(i) (PCIE_ATR_BASE + 0x800 + (i) * 0x8) 109 #define PCIE_ATR_IB_ADDR1(i) (PCIE_ATR_BASE + 0x804 + (i) * 0x8) 110 #define PCIE_ATR_HDR_MEM 0x2 111 #define PCIE_ATR_HDR_IO 0x6 112 #define PCIE_ATR_HDR_CFG_TYPE0 0xa 113 #define PCIE_ATR_HDR_CFG_TYPE1 0xb 114 #define PCIE_ATR_HDR_RID __BIT(23) 115 116 /* AXI region */ 117 #define PCIE_ATR_OB_REGION0_SIZE (32 * 1024 * 1024) 118 #define PCIE_ATR_OB_REGION_SIZE (1 * 1024 * 1024) 119 120 #define HREAD4(sc, reg) \ 121 (bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg))) 122 #define HWRITE4(sc, reg, val) \ 123 bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val)) 124 125 struct rkpcie_softc { 126 struct pcihost_softc sc_phsc; 127 bus_space_tag_t sc_iot; 128 bus_space_handle_t sc_ioh; 129 bus_space_handle_t sc_bus_cfgh[32]; 130 bus_addr_t sc_axi_addr; 131 bus_addr_t sc_apb_addr; 132 bus_size_t sc_axi_size; 133 bus_size_t sc_apb_size; 134 135 struct extent *sc_regionex; 136 }; 137 138 static int rkpcie_match(device_t, cfdata_t, void *); 139 static void rkpcie_attach(device_t, device_t, void *); 140 141 CFATTACH_DECL_NEW(rkpcie, sizeof(struct rkpcie_softc), 142 rkpcie_match, rkpcie_attach, NULL, NULL); 143 144 static int 145 rkpcie_match(device_t parent, cfdata_t cf, void *aux) 146 { 147 const char * const compatible[] = { 148 "rockchip,rk3399-pcie", 149 NULL 150 }; 151 struct fdt_attach_args *faa = aux; 152 153 return of_match_compatible(faa->faa_phandle, compatible); 154 } 155 156 static void rkpcie_atr_init(struct rkpcie_softc *); 157 158 static int rkpcie_bus_maxdevs(void *, int); 159 static pcitag_t rkpcie_make_tag(void *, int, int, int); 160 static void rkpcie_decompose_tag(void *, pcitag_t, int *, int *, int *); 161 static pcireg_t rkpcie_conf_read(void *, pcitag_t, int); 162 static void rkpcie_conf_write(void *, pcitag_t, int, pcireg_t); 163 static int rkpcie_conf_hook(void *, int, int, int, pcireg_t); 164 165 static struct fdtbus_interrupt_controller_func rkpcie_intrfuncs; 166 167 static inline int 168 OF_getpropintarray(int handle, const char *prop, uint32_t *buf, int buflen) 169 { 170 int len; 171 int i; 172 173 len = OF_getprop(handle, prop, buf, buflen); 174 if (len < 0 || (len % sizeof(uint32_t))) 175 return -1; 176 177 for (i = 0; i < len / sizeof(uint32_t); i++) 178 buf[i] = be32toh(buf[i]); 179 180 return len; 181 } 182 183 static inline void 184 clock_enable_all(int phandle) 185 { 186 for (u_int i = 0; i < 4; i++) { 187 struct clk * clk = fdtbus_clock_get_index(phandle, i); 188 if (clk == NULL) 189 continue; 190 if (clk_enable(clk) != 0) 191 continue; 192 } 193 } 194 195 static inline void 196 clock_enable(int phandle, const char *name) 197 { 198 struct clk * clk = fdtbus_clock_get(phandle, name); 199 if (clk == NULL) 200 return; 201 if (clk_enable(clk) != 0) 202 return; 203 } 204 205 static void 206 reset_assert(int phandle, const char *name) 207 { 208 struct fdtbus_reset *rst; 209 210 rst = fdtbus_reset_get(phandle, name); 211 fdtbus_reset_assert(rst); 212 fdtbus_reset_put(rst); 213 } 214 215 static void 216 reset_deassert(int phandle, const char *name) 217 { 218 struct fdtbus_reset *rst; 219 220 rst = fdtbus_reset_get(phandle, name); 221 fdtbus_reset_deassert(rst); 222 fdtbus_reset_put(rst); 223 } 224 225 static void 226 rkpcie_attach(device_t parent, device_t self, void *aux) 227 { 228 struct rkpcie_softc *sc = device_private(self); 229 struct pcihost_softc * const phsc = &sc->sc_phsc; 230 struct fdt_attach_args *faa = aux; 231 //struct pcibus_attach_args pba; 232 struct fdtbus_gpio_pin *ep_gpio; 233 uint32_t bus_range[2]; 234 uint32_t status; 235 bool retry = false; 236 int timo; 237 238 phsc->sc_dev = self; 239 phsc->sc_bst = faa->faa_bst; 240 phsc->sc_dmat = faa->faa_dmat; 241 sc->sc_iot = phsc->sc_bst; 242 phsc->sc_phandle = faa->faa_phandle; 243 const int phandle = phsc->sc_phandle; 244 245 if (fdtbus_get_reg_byname(faa->faa_phandle, "axi-base", &sc->sc_axi_addr, &sc->sc_axi_size) != 0) { 246 aprint_error(": couldn't get axi registers\n"); 247 return; 248 } 249 if (fdtbus_get_reg_byname(faa->faa_phandle, "apb-base", &sc->sc_apb_addr, &sc->sc_apb_size) != 0) { 250 aprint_error(": couldn't get apb registers\n"); 251 sc->sc_axi_size = 0; 252 return; 253 } 254 255 if (bus_space_map(sc->sc_iot, sc->sc_apb_addr, 256 sc->sc_apb_size, 0, &sc->sc_ioh)) { 257 printf(": can't map registers\n"); 258 sc->sc_axi_size = 0; 259 sc->sc_apb_size = 0; 260 return; 261 } 262 263 aprint_naive("\n"); 264 aprint_normal(": RK3399 PCIe\n"); 265 266 struct fdtbus_regulator *regulator; 267 regulator = fdtbus_regulator_acquire(phandle, "vpcie3v3-supply"); 268 fdtbus_regulator_enable(regulator); 269 fdtbus_regulator_release(regulator); 270 271 fdtbus_clock_assign(phandle); 272 clock_enable_all(phandle); 273 274 ep_gpio = fdtbus_gpio_acquire(phandle, "ep-gpios", GPIO_PIN_OUTPUT); 275 //retry = true; 276 again: 277 fdtbus_gpio_write(ep_gpio, 0); 278 279 reset_assert(phandle, "aclk"); 280 reset_assert(phandle, "pclk"); 281 reset_assert(phandle, "pm"); 282 283 //device_printf(self, "%s phy0\n", __func__); 284 struct fdtbus_phy *phy[4]; 285 memset(phy, 0, sizeof(phy)); 286 phy[0] = fdtbus_phy_get(phandle, "pcie-phy-0"); 287 //device_printf(self, "%s phy1 %p\n", __func__, phy[0]); 288 if (phy[0] == NULL) { 289 phy[0] = fdtbus_phy_get(phandle, "pcie-phy"); 290 device_printf(self, "%s phy2 %p\n", __func__, phy); 291 } else { 292 /* XXX */ 293 phy[1] = fdtbus_phy_get(phandle, "pcie-phy-1"); 294 phy[2] = fdtbus_phy_get(phandle, "pcie-phy-2"); 295 phy[3] = fdtbus_phy_get(phandle, "pcie-phy-3"); 296 } 297 298 reset_assert(phandle, "core"); 299 reset_assert(phandle, "mgmt"); 300 reset_assert(phandle, "mgmt-sticky"); 301 reset_assert(phandle, "pipe"); 302 303 delay(10); 304 305 reset_deassert(phandle, "pm"); 306 reset_deassert(phandle, "aclk"); 307 reset_deassert(phandle, "pclk"); 308 309 if (retry) 310 HWRITE4(sc, PCIE_CLIENT_BASIC_STRAP_CONF, PCBSC_PGS_GEN1); 311 else 312 HWRITE4(sc, PCIE_CLIENT_BASIC_STRAP_CONF, PCBSC_PGS_GEN2); 313 314 /* Switch into Root Complex mode. */ 315 HWRITE4(sc, PCIE_CLIENT_BASIC_STRAP_CONF, 316 PCBSC_MS_ROOTPORT | PCBSC_CONF_EN | PCBSC_LC(4)); 317 //printf("%s PCBSC %x\n", __func__, HREAD4(sc, PCIE_CLIENT_BASIC_STRAP_CONF)); 318 319 if (phy[3] && fdtbus_phy_enable(phy[3], true) != 0) { 320 aprint_error(": couldn't enable phy3\n"); 321 } 322 if (phy[2] && fdtbus_phy_enable(phy[2], true) != 0) { 323 aprint_error(": couldn't enable phy2\n"); 324 } 325 if (phy[1] && fdtbus_phy_enable(phy[1], true) != 0) { 326 aprint_error(": couldn't enable phy1\n"); 327 } 328 if (phy[0] && fdtbus_phy_enable(phy[0], true) != 0) { 329 aprint_error(": couldn't enable phy0\n"); 330 } 331 332 reset_deassert(phandle, "mgmt-sticky"); 333 reset_deassert(phandle, "core"); 334 reset_deassert(phandle, "mgmt"); 335 reset_deassert(phandle, "pipe"); 336 337 /* FTS count */ 338 HWRITE4(sc, PCIE_LM_PLC1, HREAD4(sc, PCIE_LM_PLC1) | PCIE_LM_PLC1_FTS_MASK); 339 340 /* XXX Advertise power limits? */ 341 342 /* common clock */ 343 HWRITE4(sc, PCIE_RC_CONFIG_LCSR, HREAD4(sc, PCIE_RC_CONFIG_LCSR) | PCIE_LCSR_COMCLKCFG); 344 /* 128 RCB */ 345 HWRITE4(sc, PCIE_RC_CONFIG_LCSR, HREAD4(sc, PCIE_RC_CONFIG_LCSR) | PCIE_LCSR_RCB); 346 347 /* Start link training. */ 348 HWRITE4(sc, PCIE_CLIENT_BASIC_STRAP_CONF, PCBSC_LINK_TRAIN_EN); 349 350 fdtbus_gpio_write(ep_gpio, 1); 351 352 for (timo = 500; timo > 0; timo--) { 353 status = HREAD4(sc, PCIE_CLIENT_BASIC_STATUS1); 354 if (PCBS1_LINK_ST(status) == PCBS1_LS_DL_DONE) 355 break; 356 delay(1000); 357 } 358 if (timo == 0) { 359 device_printf(self, "link training timeout (link_st %u)\n", 360 PCBS1_LINK_ST(status)); 361 if (!retry) { 362 retry = true; 363 goto again; 364 } 365 return; 366 } 367 368 if (!retry) { 369 HWRITE4(sc, PCIE_RC_CONFIG_LCSR, HREAD4(sc, PCIE_RC_CONFIG_LCSR) | PCIE_LCSR_RETRAIN); 370 for (timo = 500; timo > 0; timo--) { 371 status = HREAD4(sc, PCIE_LM_CORE_CTRL); 372 if ((status & PCIE_CORE_PL_CONF_SPEED_MASK) == PCIE_CORE_PL_CONF_SPEED_5G) 373 break; 374 delay(1000); 375 } 376 if (timo == 0) { 377 device_printf(self, "Gen2 link training timeout\n"); 378 retry = true; 379 goto again; 380 } 381 } 382 383 #if 0 384 printf("%s CBS0 %x\n", __func__, HREAD4(sc, PCIE_CLIENT_BASIC_STATUS1)); 385 HWRITE4(sc, PCIE_LM_DEBUG_MUX_CONTROL, (HREAD4(sc, PCIE_LM_DEBUG_MUX_CONTROL) & ~0xf) | 0); 386 printf("%s CDO0 %x\n", __func__, HREAD4(sc, PCIE_CLIENT_DEBUG_OUT_0)); 387 HWRITE4(sc, PCIE_LM_DEBUG_MUX_CONTROL, (HREAD4(sc, PCIE_LM_DEBUG_MUX_CONTROL) & ~0xf) | 1); 388 printf("%s CDO0 %x\n", __func__, HREAD4(sc, PCIE_CLIENT_DEBUG_OUT_0)); 389 HWRITE4(sc, PCIE_LM_DEBUG_MUX_CONTROL, (HREAD4(sc, PCIE_LM_DEBUG_MUX_CONTROL) & ~0xf) | 4); 390 printf("%s CDO0 %x\n", __func__, HREAD4(sc, PCIE_CLIENT_DEBUG_OUT_0)); 391 HWRITE4(sc, PCIE_LM_DEBUG_MUX_CONTROL, (HREAD4(sc, PCIE_LM_DEBUG_MUX_CONTROL) & ~0xf) | 5); 392 printf("%s CDO0 %x\n", __func__, HREAD4(sc, PCIE_CLIENT_DEBUG_OUT_0)); 393 printf("%s LINKWIDTH %x\n", __func__, HREAD4(sc, PCIE_LM_LINKWIDTH)); 394 //HWRITE4(sc, PCIE_LM_LINKWIDTH, 0x1000f); 395 //printf("%s LINKWIDTH %x\n", __func__, HREAD4(sc, PCIE_LM_LINKWIDTH)); 396 printf("%s LANEMAP %x\n", __func__, HREAD4(sc, PCIE_LM_LANEMAP)); 397 #endif 398 399 fdtbus_gpio_release(ep_gpio); 400 401 HWRITE4(sc, PCIE_RC_BASE + PCI_CLASS_REG, 402 PCI_CLASS_BRIDGE << PCI_CLASS_SHIFT | 403 PCI_SUBCLASS_BRIDGE_PCI << PCI_SUBCLASS_SHIFT); 404 405 /* Initialize Root Complex registers. */ 406 HWRITE4(sc, PCIE_LM_VENDOR_ID, PCI_VENDOR_ROCKCHIP); 407 HWRITE4(sc, PCIE_RC_BASE + PCI_CLASS_REG, 408 PCI_CLASS_BRIDGE << PCI_CLASS_SHIFT | 409 PCI_SUBCLASS_BRIDGE_PCI << PCI_SUBCLASS_SHIFT); 410 HWRITE4(sc, PCIE_LM_RCBAR, PCIE_LM_RCBARPIE | PCIE_LM_RCBARPIS | PCIE_LM_RCBARPME | PCIE_LM_RCBARPMS); 411 412 /* remove L1 substate cap */ 413 status = HREAD4(sc, PCIE_RC_CONFIG_THP_CAP); 414 status &= ~PCIE_RC_CONFIG_THP_CAP_NEXT_MASK; 415 HWRITE4(sc, PCIE_RC_CONFIG_THP_CAP, status); 416 417 if (OF_getproplen(phandle, "aspm-no-l0s") == 0) { 418 status = HREAD4(sc, PCIE_RC_PCIE_LCAP); 419 status &= ~__SHIFTIN(1, PCIE_LCAP_ASPM); 420 HWRITE4(sc, PCIE_RC_PCIE_LCAP, status); 421 } 422 423 status = HREAD4(sc, PCIE_RC_CONFIG_DCSR); 424 status &= ~PCIE_DCSR_MAX_PAYLOAD; 425 status |= __SHIFTIN(1, PCIE_DCSR_MAX_PAYLOAD); 426 HWRITE4(sc, PCIE_RC_CONFIG_DCSR, status); 427 428 /* Create extents for our address space. */ 429 sc->sc_regionex = extent_create("rkpcie", sc->sc_axi_addr, 430 sc->sc_axi_addr - 1 + 64 * 1048576, NULL, 0, EX_WAITOK); 431 432 /* Set up bus range. */ 433 if (OF_getpropintarray(phandle, "bus-range", bus_range, 434 sizeof(bus_range)) != sizeof(bus_range) || 435 bus_range[0] >= 32 || bus_range[1] >= 32) { 436 bus_range[0] = 0; 437 bus_range[1] = 31; 438 } 439 sc->sc_phsc.sc_bus_min = bus_range[0]; 440 sc->sc_phsc.sc_bus_max = bus_range[1]; 441 442 if (sc->sc_phsc.sc_bus_min != 0) { 443 aprint_error_dev(self, "bus-range doesn't start at 0\n"); 444 return; 445 } 446 447 /* Configure Address Translation. */ 448 rkpcie_atr_init(sc); 449 450 fdtbus_register_interrupt_controller(self, OF_child(sc->sc_phsc.sc_phandle), 451 &rkpcie_intrfuncs); 452 453 sc->sc_phsc.sc_type = PCIHOST_ECAM; 454 pcihost_init(&sc->sc_phsc.sc_pc, sc); 455 sc->sc_phsc.sc_pc.pc_bus_maxdevs = rkpcie_bus_maxdevs; 456 sc->sc_phsc.sc_pc.pc_make_tag = rkpcie_make_tag; 457 sc->sc_phsc.sc_pc.pc_decompose_tag = rkpcie_decompose_tag; 458 sc->sc_phsc.sc_pc.pc_conf_read = rkpcie_conf_read; 459 sc->sc_phsc.sc_pc.pc_conf_write = rkpcie_conf_write; 460 sc->sc_phsc.sc_pc.pc_conf_hook = rkpcie_conf_hook; 461 pcihost_init2(&sc->sc_phsc); 462 } 463 464 static void 465 rkpcie_atr_init(struct rkpcie_softc *sc) 466 { 467 uint32_t *ranges = NULL; 468 struct extent * const ex = sc->sc_regionex; 469 bus_addr_t aaddr; 470 bus_addr_t addr; 471 bus_size_t size, offset; 472 uint32_t type; 473 int len, region; 474 int i; 475 476 /* get root bus's config space out of the APB space */ 477 bus_space_subregion(sc->sc_iot, sc->sc_ioh, PCIE_RC_NORMAL_BASE, PCI_EXTCONF_SIZE * 8, &sc->sc_bus_cfgh[0]); 478 479 len = OF_getproplen(sc->sc_phsc.sc_phandle, "ranges"); 480 if (len <= 0 || (len % (7 * sizeof(uint32_t))) != 0) 481 goto fail; 482 ranges = kmem_zalloc(len, KM_SLEEP); 483 OF_getpropintarray(sc->sc_phsc.sc_phandle, "ranges", ranges, len); 484 485 for (i = 0; i < len / sizeof(uint32_t); i += 7) { 486 /* Handle IO and MMIO. */ 487 switch (ranges[i] & 0x03000000) { 488 case 0x00000000: 489 type = PCIE_ATR_HDR_CFG_TYPE0; 490 break; 491 case 0x01000000: 492 type = PCIE_ATR_HDR_IO; 493 break; 494 case 0x02000000: 495 case 0x03000000: 496 type = PCIE_ATR_HDR_MEM; 497 break; 498 default: 499 continue; 500 } 501 502 addr = ((uint64_t)ranges[i + 1] << 32) + ranges[i + 2]; 503 aaddr = ((uint64_t)ranges[i + 3] << 32) + ranges[i + 4]; 504 size = (uint64_t)ranges[i+5] << 32 | ranges[i + 6]; 505 506 if (type == PCIE_ATR_HDR_CFG_TYPE0) { 507 addr = __SHIFTOUT(ranges[i], PHYS_HI_BUS) << 20; 508 } 509 510 /* Only support mappings aligned on a region boundary. */ 511 if (addr & (PCIE_ATR_OB_REGION_SIZE - 1)) 512 goto fail; 513 if (aaddr & (PCIE_ATR_OB_REGION_SIZE - 1)) 514 goto fail; 515 if (size & (PCIE_ATR_OB_REGION_SIZE - 1)) 516 goto fail; 517 518 /* Mappings should lie in AXI region. */ 519 if (aaddr < sc->sc_axi_addr) 520 goto fail; 521 if (aaddr + size > sc->sc_axi_addr + 64*1024*1024) 522 goto fail; 523 524 while (size > 0) { 525 offset = aaddr - sc->sc_axi_addr; 526 region = (offset / PCIE_ATR_OB_REGION_SIZE); 527 if (region >= 0x20) 528 region -= 0x1f; 529 if (region > 32) 530 continue; 531 u_long regionsize = region ? 532 PCIE_ATR_OB_REGION_SIZE : PCIE_ATR_OB_REGION0_SIZE; 533 uint32_t regionbits = ilog2(regionsize); 534 535 //printf("%s %lx %lx %lx\n", __func__, addr, aaddr, regionsize); 536 if (extent_alloc_region(ex, aaddr, regionsize, EX_WAITOK) != 0) 537 goto fail; 538 if (type == PCIE_ATR_HDR_CFG_TYPE0) { 539 const uint32_t bus = (addr >> 20) & 0xff; 540 if (bus == 0 || 541 bus >= __arraycount(sc->sc_bus_cfgh)) 542 continue; 543 bus_space_map(sc->sc_iot, aaddr, regionsize, 0, &sc->sc_bus_cfgh[bus]); 544 if (bus > 1) 545 type = PCIE_ATR_HDR_CFG_TYPE1; 546 } 547 HWRITE4(sc, PCIE_ATR_OB_ADDR0(region), 548 addr | (regionbits-1)); 549 HWRITE4(sc, PCIE_ATR_OB_ADDR1(region), addr >> 32); 550 HWRITE4(sc, PCIE_ATR_OB_DESC0(region), 551 type | PCIE_ATR_HDR_RID); 552 HWRITE4(sc, PCIE_ATR_OB_DESC1(region), 0); 553 554 aaddr += regionsize; 555 addr += regionsize; 556 size -= regionsize; 557 } 558 } 559 kmem_free(ranges, len); 560 561 /* Passthrought inbound translations unmodified. */ 562 HWRITE4(sc, PCIE_ATR_IB_ADDR0(2), 32 - 1); 563 HWRITE4(sc, PCIE_ATR_IB_ADDR1(2), 0); 564 565 return; 566 567 fail: 568 extent_print(ex); 569 device_printf(sc->sc_phsc.sc_dev, "can't map ranges\n"); 570 kmem_free(ranges, len); 571 } 572 573 int 574 rkpcie_bus_maxdevs(void *v, int bus) 575 { 576 struct rkpcie_softc *rksc = v; 577 struct pcihost_softc *sc = &rksc->sc_phsc; 578 579 if (bus == sc->sc_bus_min) 580 return 1; 581 return 32; 582 } 583 584 pcitag_t 585 rkpcie_make_tag(void *v, int bus, int device, int function) 586 { 587 /* Return ECAM address. */ 588 return ((bus << 20) | (device << 15) | (function << 12)); 589 } 590 591 void 592 rkpcie_decompose_tag(void *v, pcitag_t tag, int *bp, int *dp, int *fp) 593 { 594 if (bp != NULL) 595 *bp = (tag >> 20) & 0xff; 596 if (dp != NULL) 597 *dp = (tag >> 15) & 0x1f; 598 if (fp != NULL) 599 *fp = (tag >> 12) & 0x7; 600 } 601 602 pcireg_t 603 rkpcie_conf_read(void *v, pcitag_t tag, int reg) 604 { 605 struct rkpcie_softc *sc = v; 606 struct pcihost_softc *phsc = &sc->sc_phsc; 607 int bus, dev, fn; 608 bus_size_t offset; 609 uint32_t data; 610 611 KASSERT(reg >= 0); 612 KASSERT(reg < PCI_EXTCONF_SIZE); 613 614 rkpcie_decompose_tag(sc, tag, &bus, &dev, &fn); 615 if (bus > phsc->sc_bus_max) 616 return 0xffffffff; 617 if (bus == phsc->sc_bus_min + 1 && dev > 0) 618 return 0xffffffff; 619 offset = dev << 15 | fn << 12 | reg; 620 if (bus_space_peek_4(sc->sc_iot, sc->sc_bus_cfgh[bus], offset, &data) == 0) 621 return data; 622 623 return 0xffffffff; 624 } 625 626 void 627 rkpcie_conf_write(void *v, pcitag_t tag, int reg, pcireg_t data) 628 { 629 struct rkpcie_softc *sc = v; 630 struct pcihost_softc *phsc = &sc->sc_phsc; 631 int bus, dev, fn; 632 bus_size_t offset; 633 634 KASSERT(reg >= 0); 635 KASSERT(reg < PCI_EXTCONF_SIZE); 636 637 rkpcie_decompose_tag(sc, tag, &bus, &dev, &fn); 638 if (bus > phsc->sc_bus_max) 639 return; 640 if (bus == phsc->sc_bus_min + 1 && dev > 0) 641 return; 642 offset = dev << 15 | fn << 12 | reg; 643 bus_space_poke_4(sc->sc_iot, sc->sc_bus_cfgh[bus], offset, data); 644 } 645 646 static int 647 rkpcie_conf_hook(void *v, int b, int d, int f, pcireg_t id) 648 { 649 return (PCI_CONF_DEFAULT & ~PCI_CONF_ENABLE_BM) | PCI_CONF_MAP_ROM; 650 } 651 652 /* INTx interrupt controller */ 653 static void * 654 rkpcie_intx_establish(device_t dev, u_int *specifier, int ipl, int flags, 655 int (*func)(void *), void *arg) 656 { 657 struct rkpcie_softc *sc = device_private(dev); 658 void *cookie; 659 660 const u_int pin = be32toh(specifier[0]); 661 device_printf(sc->sc_phsc.sc_dev, "%s pin %u\n", __func__, pin); 662 663 /* Unmask legacy interrupts. */ 664 HWRITE4(sc, PCIE_CLIENT_INT_MASK, 665 PCIM_INTx_ENAB(0) | PCIM_INTx_ENAB(1) | 666 PCIM_INTx_ENAB(2) | PCIM_INTx_ENAB(3)); 667 668 cookie = fdtbus_intr_establish_byname(sc->sc_phsc.sc_phandle, "legacy", ipl, flags, func, arg); 669 670 return cookie; 671 } 672 673 static void 674 rkpcie_intx_disestablish(device_t dev, void *ih) 675 { 676 struct rkpcie_softc *sc = device_private(dev); 677 device_printf(dev, "%s\n", __func__); 678 fdtbus_intr_disestablish(sc->sc_phsc.sc_phandle, ih); 679 } 680 681 static bool 682 rkpcie_intx_intrstr(device_t dev, u_int *specifier, char *buf, size_t buflen) 683 { 684 struct rkpcie_softc *sc = device_private(dev); 685 686 fdtbus_intr_str(sc->sc_phsc.sc_phandle, 1, buf, buflen); 687 688 return true; 689 } 690 691 static struct fdtbus_interrupt_controller_func rkpcie_intrfuncs = { 692 .establish = rkpcie_intx_establish, 693 .disestablish = rkpcie_intx_disestablish, 694 .intrstr = rkpcie_intx_intrstr, 695 }; 696
Indexes created Sun Oct 19 02:09:48 GMT 2025