rk3399_pcie.c revision 1.11
1 /* $NetBSD: rk3399_pcie.c,v 1.11 2020/10/08 22:14:00 tnn Exp $ */ 2 /* 3 * Copyright (c) 2018 Mark Kettenis <kettenis (at) openbsd.org> 4 * 5 * Permission to use, copy, modify, and distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 */ 17 18 #include <sys/cdefs.h> 19 20 __KERNEL_RCSID(1, "$NetBSD: rk3399_pcie.c,v 1.11 2020/10/08 22:14:00 tnn Exp $"); 21 22 #include <sys/param.h> 23 #include <sys/systm.h> 24 #include <sys/bitops.h> 25 #include <sys/device.h> 26 #include <sys/kmem.h> 27 28 #include <machine/intr.h> 29 #include <sys/bus.h> 30 #include <dev/fdt/fdtvar.h> 31 #include <dev/fdt/syscon.h> 32 #include <arm/cpufunc.h> 33 34 #include <dev/pci/pcidevs.h> 35 #include <dev/pci/pcireg.h> 36 #include <dev/pci/pcivar.h> 37 #include <dev/pci/pciconf.h> 38 39 #include <arm/fdt/pcihost_fdtvar.h> 40 #include <sys/gpio.h> 41 42 #define SETREG(m, v) ((m)<<16|__SHIFTIN((v), (m))) 43 #define GETREG(m, v) (__SHIFTOUT((v), (m))) 44 45 /* APB region */ 46 #define PCIE_CLIENT_BASE 0x000000 47 #define PCIE_CLIENT_BASIC_STRAP_CONF 0x0000 48 #define PCBSC_PCIE_GEN_SEL __BIT(7) 49 #define PCBSC_PGS_GEN1 SETREG(PCBSC_PCIE_GEN_SEL, 0) 50 #define PCBSC_PGS_GEN2 SETREG(PCBSC_PCIE_GEN_SEL, 1) 51 #define PCBSC_MODE_SELECT __BIT(6) 52 #define PCBSC_MS_ENDPOINT SETREG(PCBSC_MODE_SELECT, 0) 53 #define PCBSC_MS_ROOTPORT SETREG(PCBSC_MODE_SELECT, 1) 54 #define PCBSC_LANE_COUNT __BITS(5,4) 55 #define PCBSC_LC(x) SETREG(PCBSC_LANE_COUNT, ilog2(x)) /* valid for x1,2,4 */ 56 #define PCBSC_ARI_EN SETREG(__BIT(3), 1) /* Alternate Routing ID Enable */ 57 #define PCBSC_SR_IOV_EN SETREG(__BIT(2), 1) 58 #define PCBSC_LINK_TRAIN_EN SETREG(__BIT(1), 1) 59 #define PCBSC_CONF_EN SETREG(__BIT(0), 1) /* Config enable */ 60 #define PCIE_CLIENT_DEBUG_OUT_0 0x003c 61 #define PCIE_CLIENT_DEBUG_OUT_1 0x0040 62 #define PCIE_CLIENT_BASIC_STATUS0 0x0044 63 #define PCIE_CLIENT_BASIC_STATUS1 0x0048 64 #define PCBS1_LINK_ST(x) (u_int)__SHIFTOUT((x), __BITS(21,20)) 65 #define PCBS1_LS_NO_RECV 0 /* no receivers */ 66 #define PCBS1_LS_TRAINING 1 /* link training */ 67 #define PCBS1_LS_DL_INIT 2 /* link up, DL init progressing */ 68 #define PCBS1_LS_DL_DONE 3 /* link up, DL init complete */ 69 #define PCIE_CLIENT_INT_MASK 0x004c 70 #define PCIM_INTx_MASK(x) SETREG(__BIT((x)+5), 1) 71 #define PCIM_INTx_ENAB(x) SETREG(__BIT((x)+5), 0) 72 73 #define PCIE_CORE_BASE 0x800000 74 #define PCIE_RC_NORMAL_BASE (PCIE_CORE_BASE + 0x00000) 75 76 #define PCIE_LM_BASE 0x900000 77 #define PCIE_LM_CORE_CTRL (PCIE_LM_BASE + 0x00) 78 #define PCIE_CORE_PL_CONF_SPEED_5G 0x00000008 79 #define PCIE_CORE_PL_CONF_SPEED_MASK 0x00000018 80 #define PCIE_CORE_PL_CONF_LANE_MASK 0x00000006 81 #define PCIE_CORE_PL_CONF_LANE_SHIFT 1 82 #define PCIE_LM_PLC1 (PCIE_LM_BASE + 0x04) 83 #define PCIE_LM_PLC1_FTS_MASK __BITS(23, 8) 84 #define PCIE_LM_VENDOR_ID (PCIE_LM_BASE + 0x44) 85 #define PCIE_LM_LINKWIDTH (PCIE_LM_BASE + 0x50) 86 #define PCIE_LM_LANEMAP (PCIE_LM_BASE + 0x200) 87 #define PCIE_LM_DEBUG_MUX_CONTROL (PCIE_LM_BASE + 0x208) 88 #define PCIE_LM_RCBAR (PCIE_LM_BASE + 0x300) 89 #define PCIE_LM_RCBARPME __BIT(17) 90 #define PCIE_LM_RCBARPMS __BIT(18) 91 #define PCIE_LM_RCBARPIE __BIT(19) 92 #define PCIE_LM_RCBARPIS __BIT(20) 93 94 #define PCIE_RC_BASE 0xa00000 95 #define PCIE_RC_CONFIG_DCSR (PCIE_RC_BASE + 0x0c0 + PCIE_DCSR) 96 #define PCIE_RC_PCIE_LCAP (PCIE_RC_BASE + 0x0c0 + PCIE_LCAP) 97 #define PCIE_RC_CONFIG_LCSR (PCIE_RC_BASE + 0x0c0 + PCIE_LCSR) 98 #define PCIE_RC_CONFIG_THP_CAP (PCIE_RC_BASE + 0x274) 99 #define PCIE_RC_CONFIG_THP_CAP_NEXT_MASK __BITS(31, 20) 100 101 102 #define PCIE_ATR_BASE 0xc00000 103 #define PCIE_ATR_OB_ADDR0(i) (PCIE_ATR_BASE + 0x000 + (i) * 0x20) 104 #define PCIE_ATR_OB_ADDR1(i) (PCIE_ATR_BASE + 0x004 + (i) * 0x20) 105 #define PCIE_ATR_OB_DESC0(i) (PCIE_ATR_BASE + 0x008 + (i) * 0x20) 106 #define PCIE_ATR_OB_DESC1(i) (PCIE_ATR_BASE + 0x00c + (i) * 0x20) 107 #define PCIE_ATR_IB_ADDR0(i) (PCIE_ATR_BASE + 0x800 + (i) * 0x8) 108 #define PCIE_ATR_IB_ADDR1(i) (PCIE_ATR_BASE + 0x804 + (i) * 0x8) 109 #define PCIE_ATR_HDR_MEM 0x2 110 #define PCIE_ATR_HDR_IO 0x6 111 #define PCIE_ATR_HDR_CFG_TYPE0 0xa 112 #define PCIE_ATR_HDR_CFG_TYPE1 0xb 113 #define PCIE_ATR_HDR_RID __BIT(23) 114 115 /* AXI region */ 116 #define PCIE_ATR_OB_REGION0_SIZE (32 * 1024 * 1024) 117 #define PCIE_ATR_OB_REGION_SIZE (1 * 1024 * 1024) 118 119 #define HREAD4(sc, reg) \ 120 bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg)) 121 #define HWRITE4(sc, reg, val) \ 122 bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val)) 123 #define AXIPEEK4(sc, reg, valp) \ 124 bus_space_peek_4((sc)->sc_iot, (sc)->sc_axi_ioh, (reg), (valp)) 125 #define AXIPOKE4(sc, reg, val) \ 126 bus_space_poke_4((sc)->sc_iot, (sc)->sc_axi_ioh, (reg), (val)) 127 128 struct rkpcie_softc { 129 struct pcihost_softc sc_phsc; 130 bus_space_tag_t sc_iot; 131 bus_space_handle_t sc_ioh; 132 bus_space_handle_t sc_axi_ioh; 133 bus_addr_t sc_axi_addr; 134 bus_addr_t sc_apb_addr; 135 bus_size_t sc_axi_size; 136 bus_size_t sc_apb_size; 137 }; 138 139 static int rkpcie_match(device_t, cfdata_t, void *); 140 static void rkpcie_attach(device_t, device_t, void *); 141 142 CFATTACH_DECL_NEW(rkpcie, sizeof(struct rkpcie_softc), 143 rkpcie_match, rkpcie_attach, NULL, NULL); 144 145 static int 146 rkpcie_match(device_t parent, cfdata_t cf, void *aux) 147 { 148 const char * const compatible[] = { 149 "rockchip,rk3399-pcie", 150 NULL 151 }; 152 struct fdt_attach_args *faa = aux; 153 154 return of_match_compatible(faa->faa_phandle, compatible); 155 } 156 157 static void rkpcie_atr_init(struct rkpcie_softc *); 158 159 static int rkpcie_bus_maxdevs(void *, int); 160 static pcitag_t rkpcie_make_tag(void *, int, int, int); 161 static void rkpcie_decompose_tag(void *, pcitag_t, int *, int *, int *); 162 static pcireg_t rkpcie_conf_read(void *, pcitag_t, int); 163 static void rkpcie_conf_write(void *, pcitag_t, int, pcireg_t); 164 static int rkpcie_conf_hook(void *, int, int, int, pcireg_t); 165 166 static struct fdtbus_interrupt_controller_func rkpcie_intrfuncs; 167 168 static inline void 169 clock_enable_all(int phandle) 170 { 171 for (u_int i = 0; i < 4; i++) { 172 struct clk * clk = fdtbus_clock_get_index(phandle, i); 173 if (clk == NULL) 174 continue; 175 if (clk_enable(clk) != 0) 176 continue; 177 } 178 } 179 180 static void 181 reset_assert(int phandle, const char *name) 182 { 183 struct fdtbus_reset *rst; 184 185 rst = fdtbus_reset_get(phandle, name); 186 fdtbus_reset_assert(rst); 187 fdtbus_reset_put(rst); 188 } 189 190 static void 191 reset_deassert(int phandle, const char *name) 192 { 193 struct fdtbus_reset *rst; 194 195 rst = fdtbus_reset_get(phandle, name); 196 fdtbus_reset_deassert(rst); 197 fdtbus_reset_put(rst); 198 } 199 200 static void 201 rkpcie_attach(device_t parent, device_t self, void *aux) 202 { 203 struct rkpcie_softc *sc = device_private(self); 204 struct pcihost_softc * const phsc = &sc->sc_phsc; 205 struct fdt_attach_args *faa = aux; 206 struct fdtbus_gpio_pin *ep_gpio; 207 u_int max_link_speed, num_lanes; 208 struct fdtbus_phy *phy[4]; 209 const u_int *bus_range; 210 uint32_t status; 211 int timo, len; 212 213 phsc->sc_dev = self; 214 phsc->sc_bst = faa->faa_bst; 215 phsc->sc_dmat = faa->faa_dmat; 216 sc->sc_iot = phsc->sc_bst; 217 phsc->sc_phandle = faa->faa_phandle; 218 const int phandle = phsc->sc_phandle; 219 220 if (fdtbus_get_reg_byname(faa->faa_phandle, "axi-base", &sc->sc_axi_addr, &sc->sc_axi_size) != 0) { 221 aprint_error(": couldn't get axi registers\n"); 222 return; 223 } 224 if (fdtbus_get_reg_byname(faa->faa_phandle, "apb-base", &sc->sc_apb_addr, &sc->sc_apb_size) != 0) { 225 aprint_error(": couldn't get apb registers\n"); 226 sc->sc_axi_size = 0; 227 return; 228 } 229 230 const int mapflags = _ARM_BUS_SPACE_MAP_STRONGLY_ORDERED; 231 if (bus_space_map(sc->sc_iot, sc->sc_apb_addr, sc->sc_apb_size, mapflags, &sc->sc_ioh) != 0 || 232 bus_space_map(sc->sc_iot, sc->sc_axi_addr, sc->sc_axi_size, mapflags, &sc->sc_axi_ioh) != 0) { 233 printf(": can't map registers\n"); 234 sc->sc_axi_size = 0; 235 sc->sc_apb_size = 0; 236 return; 237 } 238 239 aprint_naive("\n"); 240 aprint_normal(": RK3399 PCIe\n"); 241 242 struct fdtbus_regulator *regulator; 243 regulator = fdtbus_regulator_acquire(phandle, "vpcie3v3-supply"); 244 if (regulator != NULL) { 245 fdtbus_regulator_enable(regulator); 246 fdtbus_regulator_release(regulator); 247 } 248 249 fdtbus_clock_assign(phandle); 250 clock_enable_all(phandle); 251 252 ep_gpio = fdtbus_gpio_acquire(phandle, "ep-gpios", GPIO_PIN_OUTPUT); 253 254 if (of_getprop_uint32(phandle, "max-link-speed", &max_link_speed) != 0) 255 max_link_speed = 2; 256 if (of_getprop_uint32(phandle, "num-lanes", &num_lanes) != 0) 257 num_lanes = 1; 258 259 again: 260 fdtbus_gpio_write(ep_gpio, 0); 261 262 reset_assert(phandle, "aclk"); 263 reset_assert(phandle, "pclk"); 264 reset_assert(phandle, "pm"); 265 266 memset(phy, 0, sizeof(phy)); 267 phy[0] = fdtbus_phy_get(phandle, "pcie-phy-0"); 268 if (phy[0] == NULL) { 269 phy[0] = fdtbus_phy_get(phandle, "pcie-phy"); 270 } else { 271 phy[1] = fdtbus_phy_get(phandle, "pcie-phy-1"); 272 phy[2] = fdtbus_phy_get(phandle, "pcie-phy-2"); 273 phy[3] = fdtbus_phy_get(phandle, "pcie-phy-3"); 274 } 275 276 reset_assert(phandle, "core"); 277 reset_assert(phandle, "mgmt"); 278 reset_assert(phandle, "mgmt-sticky"); 279 reset_assert(phandle, "pipe"); 280 281 delay(1000); /* TPERST. use 1ms */ 282 283 reset_deassert(phandle, "pm"); 284 reset_deassert(phandle, "aclk"); 285 reset_deassert(phandle, "pclk"); 286 287 if (max_link_speed == 1) 288 HWRITE4(sc, PCIE_CLIENT_BASIC_STRAP_CONF, PCBSC_PGS_GEN1); 289 else 290 HWRITE4(sc, PCIE_CLIENT_BASIC_STRAP_CONF, PCBSC_PGS_GEN2); 291 292 /* Switch into Root Complex mode. */ 293 HWRITE4(sc, PCIE_CLIENT_BASIC_STRAP_CONF, 294 PCBSC_MS_ROOTPORT | PCBSC_CONF_EN | PCBSC_LC(num_lanes)); 295 296 if (phy[3] && fdtbus_phy_enable(phy[3], true) != 0) { 297 aprint_error(": couldn't enable phy3\n"); 298 } 299 if (phy[2] && fdtbus_phy_enable(phy[2], true) != 0) { 300 aprint_error(": couldn't enable phy2\n"); 301 } 302 if (phy[1] && fdtbus_phy_enable(phy[1], true) != 0) { 303 aprint_error(": couldn't enable phy1\n"); 304 } 305 if (phy[0] && fdtbus_phy_enable(phy[0], true) != 0) { 306 aprint_error(": couldn't enable phy0\n"); 307 } 308 309 reset_deassert(phandle, "mgmt-sticky"); 310 reset_deassert(phandle, "core"); 311 reset_deassert(phandle, "mgmt"); 312 reset_deassert(phandle, "pipe"); 313 314 fdtbus_gpio_write(ep_gpio, 1); 315 delay(20000); /* 20 ms according to PCI-e BS "Conventional Reset" */ 316 317 /* Start link training. */ 318 HWRITE4(sc, PCIE_CLIENT_BASIC_STRAP_CONF, PCBSC_LINK_TRAIN_EN); 319 320 for (timo = 500; timo > 0; timo--) { 321 status = HREAD4(sc, PCIE_CLIENT_BASIC_STATUS1); 322 if (PCBS1_LINK_ST(status) == PCBS1_LS_DL_DONE) 323 break; 324 delay(1000); 325 } 326 if (timo == 0) { 327 device_printf(self, "link training timeout (link_st %u)\n", 328 PCBS1_LINK_ST(status)); 329 if (max_link_speed > 1) { 330 --max_link_speed; 331 goto again; 332 } 333 return; 334 } 335 336 if (max_link_speed == 2) { 337 HWRITE4(sc, PCIE_RC_CONFIG_LCSR, HREAD4(sc, PCIE_RC_CONFIG_LCSR) | PCIE_LCSR_RETRAIN); 338 for (timo = 500; timo > 0; timo--) { 339 status = HREAD4(sc, PCIE_LM_CORE_CTRL); 340 if ((status & PCIE_CORE_PL_CONF_SPEED_MASK) == PCIE_CORE_PL_CONF_SPEED_5G) 341 break; 342 delay(1000); 343 } 344 if (timo == 0) { 345 device_printf(self, "Gen2 link training timeout\n"); 346 --max_link_speed; 347 goto again; 348 } 349 } 350 delay(80000); /* wait 100 ms before CSR access. already waited 20. */ 351 352 fdtbus_gpio_release(ep_gpio); 353 354 HWRITE4(sc, PCIE_RC_BASE + PCI_CLASS_REG, 355 PCI_CLASS_BRIDGE << PCI_CLASS_SHIFT | 356 PCI_SUBCLASS_BRIDGE_PCI << PCI_SUBCLASS_SHIFT); 357 358 /* Initialize Root Complex registers. */ 359 HWRITE4(sc, PCIE_LM_VENDOR_ID, PCI_VENDOR_ROCKCHIP); 360 HWRITE4(sc, PCIE_RC_BASE + PCI_CLASS_REG, 361 PCI_CLASS_BRIDGE << PCI_CLASS_SHIFT | 362 PCI_SUBCLASS_BRIDGE_PCI << PCI_SUBCLASS_SHIFT); 363 HWRITE4(sc, PCIE_LM_RCBAR, PCIE_LM_RCBARPIE | PCIE_LM_RCBARPIS); 364 365 /* remove L1 substate cap */ 366 status = HREAD4(sc, PCIE_RC_CONFIG_THP_CAP); 367 status &= ~PCIE_RC_CONFIG_THP_CAP_NEXT_MASK; 368 HWRITE4(sc, PCIE_RC_CONFIG_THP_CAP, status); 369 370 if (of_hasprop(phandle, "aspm-no-l0s")) { 371 status = HREAD4(sc, PCIE_RC_PCIE_LCAP); 372 status &= ~__SHIFTIN(1, PCIE_LCAP_ASPM); 373 HWRITE4(sc, PCIE_RC_PCIE_LCAP, status); 374 } 375 376 /* Default bus ranges */ 377 sc->sc_phsc.sc_bus_min = 0; 378 sc->sc_phsc.sc_bus_max = 31; 379 380 /* Override bus range from DT */ 381 bus_range = fdtbus_get_prop(phandle, "bus-range", &len); 382 if (len == 8) { 383 sc->sc_phsc.sc_bus_min = be32dec(&bus_range[0]); 384 sc->sc_phsc.sc_bus_max = be32dec(&bus_range[1]); 385 } 386 387 if (sc->sc_phsc.sc_bus_min != 0) { 388 aprint_error_dev(self, "bus-range doesn't start at 0\n"); 389 return; 390 } 391 392 /* Configure Address Translation. */ 393 rkpcie_atr_init(sc); 394 395 fdtbus_register_interrupt_controller(self, OF_child(sc->sc_phsc.sc_phandle), 396 &rkpcie_intrfuncs); 397 398 sc->sc_phsc.sc_type = PCIHOST_ECAM; 399 sc->sc_phsc.sc_pci_flags |= PCI_FLAGS_MSI_OKAY; 400 sc->sc_phsc.sc_pci_flags |= PCI_FLAGS_MSIX_OKAY; 401 pcihost_init(&sc->sc_phsc.sc_pc, sc); 402 sc->sc_phsc.sc_pc.pc_bus_maxdevs = rkpcie_bus_maxdevs; 403 sc->sc_phsc.sc_pc.pc_make_tag = rkpcie_make_tag; 404 sc->sc_phsc.sc_pc.pc_decompose_tag = rkpcie_decompose_tag; 405 sc->sc_phsc.sc_pc.pc_conf_read = rkpcie_conf_read; 406 sc->sc_phsc.sc_pc.pc_conf_write = rkpcie_conf_write; 407 sc->sc_phsc.sc_pc.pc_conf_hook = rkpcie_conf_hook; 408 pcihost_init2(&sc->sc_phsc); 409 } 410 411 static void 412 rkpcie_atr_init(struct rkpcie_softc *sc) 413 { 414 const u_int *ranges; 415 bus_addr_t aaddr; 416 bus_addr_t addr; 417 bus_size_t size, resid, offset; 418 uint32_t type; 419 int region, i, ranges_len; 420 421 /* Use region 0 to map PCI configuration space */ 422 HWRITE4(sc, PCIE_ATR_OB_ADDR0(0), 25 - 1); 423 HWRITE4(sc, PCIE_ATR_OB_ADDR1(0), 0); 424 HWRITE4(sc, PCIE_ATR_OB_DESC0(0), PCIE_ATR_HDR_CFG_TYPE0 | PCIE_ATR_HDR_RID); 425 HWRITE4(sc, PCIE_ATR_OB_DESC1(0), 0); 426 427 ranges = fdtbus_get_prop(sc->sc_phsc.sc_phandle, "ranges", &ranges_len); 428 if (ranges == NULL) 429 goto fail; 430 const int ranges_cells = ranges_len / 4; 431 432 for (i = 0; i < ranges_cells; i += 7) { 433 /* Handle IO and MMIO. */ 434 switch (be32toh(ranges[i]) & 0x03000000) { 435 case 0x01000000: 436 type = PCIE_ATR_HDR_IO; 437 break; 438 case 0x02000000: 439 case 0x03000000: 440 type = PCIE_ATR_HDR_MEM; 441 break; 442 default: 443 continue; 444 } 445 446 addr = ((uint64_t)be32toh(ranges[i + 1]) << 32) + be32toh(ranges[i + 2]); 447 aaddr = ((uint64_t)be32toh(ranges[i + 3]) << 32) + be32toh(ranges[i + 4]); 448 size = be32toh(ranges[i + 6]); 449 450 /* Only support mappings aligned on a region boundary. */ 451 if (addr & (PCIE_ATR_OB_REGION_SIZE - 1)) 452 goto fail; 453 if (aaddr & (PCIE_ATR_OB_REGION_SIZE - 1)) 454 goto fail; 455 if (size & (PCIE_ATR_OB_REGION_SIZE - 1)) 456 goto fail; 457 458 /* Mappings should lie in AXI region. */ 459 if (aaddr < sc->sc_axi_addr) 460 goto fail; 461 if (aaddr + size > sc->sc_axi_addr + 64*1024*1024) 462 goto fail; 463 464 offset = addr - sc->sc_axi_addr - PCIE_ATR_OB_REGION0_SIZE; 465 region = 1 + (offset / PCIE_ATR_OB_REGION_SIZE); 466 resid = size; 467 while (resid > 0) { 468 HWRITE4(sc, PCIE_ATR_OB_ADDR0(region), 32 - 1); 469 HWRITE4(sc, PCIE_ATR_OB_ADDR1(region), 0); 470 HWRITE4(sc, PCIE_ATR_OB_DESC0(region), type | PCIE_ATR_HDR_RID); 471 HWRITE4(sc, PCIE_ATR_OB_DESC1(region), 0); 472 473 addr += PCIE_ATR_OB_REGION_SIZE; 474 resid -= PCIE_ATR_OB_REGION_SIZE; 475 region++; 476 } 477 } 478 479 /* Passthrought inbound translations unmodified. */ 480 HWRITE4(sc, PCIE_ATR_IB_ADDR0(2), 32 - 1); 481 HWRITE4(sc, PCIE_ATR_IB_ADDR1(2), 0); 482 483 return; 484 485 fail: 486 device_printf(sc->sc_phsc.sc_dev, "can't map ranges\n"); 487 } 488 489 int 490 rkpcie_bus_maxdevs(void *v, int bus) 491 { 492 struct rkpcie_softc *rksc = v; 493 struct pcihost_softc *sc = &rksc->sc_phsc; 494 495 if (bus == sc->sc_bus_min || bus == sc->sc_bus_min + 1) 496 return 1; 497 return 32; 498 } 499 500 pcitag_t 501 rkpcie_make_tag(void *v, int bus, int device, int function) 502 { 503 /* Return ECAM address. */ 504 return ((bus << 20) | (device << 15) | (function << 12)); 505 } 506 507 void 508 rkpcie_decompose_tag(void *v, pcitag_t tag, int *bp, int *dp, int *fp) 509 { 510 if (bp != NULL) 511 *bp = (tag >> 20) & 0xff; 512 if (dp != NULL) 513 *dp = (tag >> 15) & 0x1f; 514 if (fp != NULL) 515 *fp = (tag >> 12) & 0x7; 516 } 517 518 /* Only one device on root port and the first subordinate port. */ 519 static bool 520 rkpcie_conf_ok(int bus, int dev, int fn, int bus_min) 521 { 522 if (dev != 0 && (bus == bus_min || bus == bus_min + 1)) 523 return false; 524 return true; 525 } 526 527 pcireg_t 528 rkpcie_conf_read(void *v, pcitag_t tag, int offset) 529 { 530 struct rkpcie_softc *sc = v; 531 struct pcihost_softc *phsc = &sc->sc_phsc; 532 int bus, dev, fn; 533 u_int reg; 534 535 KASSERT(offset >= 0); 536 KASSERT(offset < PCI_EXTCONF_SIZE); 537 538 rkpcie_decompose_tag(sc, tag, &bus, &dev, &fn); 539 if (!rkpcie_conf_ok(bus, dev, fn, phsc->sc_bus_min)) 540 return 0xffffffff; 541 reg = (bus << 20) | (dev << 15) | (fn << 12) | offset; 542 543 if (bus == phsc->sc_bus_min) 544 return HREAD4(sc, PCIE_RC_NORMAL_BASE + reg); 545 else { 546 uint32_t val; 547 if (AXIPEEK4(sc, reg, &val) != 0) 548 return 0xffffffff; 549 return val; 550 } 551 } 552 553 void 554 rkpcie_conf_write(void *v, pcitag_t tag, int offset, pcireg_t data) 555 { 556 struct rkpcie_softc *sc = v; 557 struct pcihost_softc *phsc = &sc->sc_phsc; 558 int bus, dev, fn; 559 u_int reg; 560 561 KASSERT(offset >= 0); 562 KASSERT(offset < PCI_EXTCONF_SIZE); 563 564 rkpcie_decompose_tag(sc, tag, &bus, &dev, &fn); 565 if (!rkpcie_conf_ok(bus, dev, fn, phsc->sc_bus_min)) 566 return; 567 reg = (bus << 20) | (dev << 15) | (fn << 12) | offset; 568 569 if (bus == phsc->sc_bus_min) 570 HWRITE4(sc, PCIE_RC_NORMAL_BASE + reg, data); 571 else 572 AXIPOKE4(sc, reg, data); 573 } 574 575 static int 576 rkpcie_conf_hook(void *v, int b, int d, int f, pcireg_t id) 577 { 578 return (PCI_CONF_DEFAULT & ~PCI_CONF_ENABLE_BM) | PCI_CONF_MAP_ROM; 579 } 580 581 /* INTx interrupt controller */ 582 static void * 583 rkpcie_intx_establish(device_t dev, u_int *specifier, int ipl, int flags, 584 int (*func)(void *), void *arg) 585 { 586 struct rkpcie_softc *sc = device_private(dev); 587 void *cookie; 588 589 #if notyet 590 const u_int pin = be32toh(specifier[0]); 591 #endif 592 593 /* Unmask legacy interrupts. */ 594 HWRITE4(sc, PCIE_CLIENT_INT_MASK, 595 PCIM_INTx_ENAB(0) | PCIM_INTx_ENAB(1) | 596 PCIM_INTx_ENAB(2) | PCIM_INTx_ENAB(3)); 597 598 cookie = fdtbus_intr_establish_byname(sc->sc_phsc.sc_phandle, "legacy", ipl, flags, func, arg); 599 600 return cookie; 601 } 602 603 static void 604 rkpcie_intx_disestablish(device_t dev, void *ih) 605 { 606 struct rkpcie_softc *sc = device_private(dev); 607 device_printf(dev, "%s\n", __func__); 608 fdtbus_intr_disestablish(sc->sc_phsc.sc_phandle, ih); 609 } 610 611 static bool 612 rkpcie_intx_intrstr(device_t dev, u_int *specifier, char *buf, size_t buflen) 613 { 614 struct rkpcie_softc *sc = device_private(dev); 615 616 fdtbus_intr_str(sc->sc_phsc.sc_phandle, 1, buf, buflen); 617 618 return true; 619 } 620 621 static struct fdtbus_interrupt_controller_func rkpcie_intrfuncs = { 622 .establish = rkpcie_intx_establish, 623 .disestablish = rkpcie_intx_disestablish, 624 .intrstr = rkpcie_intx_intrstr, 625 }; 626
Indexes created Thu Oct 02 10:09:58 GMT 2025