rk3399_pcie.c revision 1.15
1 /* $NetBSD: rk3399_pcie.c,v 1.15 2021/01/27 03:10:19 thorpej Exp $ */ 2 /* 3 * Copyright (c) 2018 Mark Kettenis <kettenis (at) openbsd.org> 4 * 5 * Permission to use, copy, modify, and distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 */ 17 18 #include <sys/cdefs.h> 19 20 __KERNEL_RCSID(1, "$NetBSD: rk3399_pcie.c,v 1.15 2021/01/27 03:10:19 thorpej Exp $"); 21 22 #include <sys/param.h> 23 #include <sys/systm.h> 24 #include <sys/bitops.h> 25 #include <sys/device.h> 26 #include <sys/kmem.h> 27 28 #include <machine/intr.h> 29 #include <sys/bus.h> 30 #include <dev/fdt/fdtvar.h> 31 #include <dev/fdt/syscon.h> 32 #include <arm/cpufunc.h> 33 34 #include <dev/pci/pcidevs.h> 35 #include <dev/pci/pcireg.h> 36 #include <dev/pci/pcivar.h> 37 #include <dev/pci/pciconf.h> 38 39 #include <arm/fdt/pcihost_fdtvar.h> 40 #include <sys/gpio.h> 41 42 #define SETREG(m, v) ((m)<<16|__SHIFTIN((v), (m))) 43 #define GETREG(m, v) (__SHIFTOUT((v), (m))) 44 45 /* APB region */ 46 #define PCIE_CLIENT_BASE 0x000000 47 #define PCIE_CLIENT_BASIC_STRAP_CONF 0x0000 48 #define PCBSC_PCIE_GEN_SEL __BIT(7) 49 #define PCBSC_PGS_GEN1 SETREG(PCBSC_PCIE_GEN_SEL, 0) 50 #define PCBSC_PGS_GEN2 SETREG(PCBSC_PCIE_GEN_SEL, 1) 51 #define PCBSC_MODE_SELECT __BIT(6) 52 #define PCBSC_MS_ENDPOINT SETREG(PCBSC_MODE_SELECT, 0) 53 #define PCBSC_MS_ROOTPORT SETREG(PCBSC_MODE_SELECT, 1) 54 #define PCBSC_LANE_COUNT __BITS(5,4) 55 #define PCBSC_LC(x) SETREG(PCBSC_LANE_COUNT, ilog2(x)) /* valid for x1,2,4 */ 56 #define PCBSC_ARI_EN SETREG(__BIT(3), 1) /* Alternate Routing ID Enable */ 57 #define PCBSC_SR_IOV_EN SETREG(__BIT(2), 1) 58 #define PCBSC_LINK_TRAIN_EN SETREG(__BIT(1), 1) 59 #define PCBSC_CONF_EN SETREG(__BIT(0), 1) /* Config enable */ 60 #define PCIE_CLIENT_DEBUG_OUT_0 0x003c 61 #define PCIE_CLIENT_DEBUG_OUT_1 0x0040 62 #define PCIE_CLIENT_BASIC_STATUS0 0x0044 63 #define PCIE_CLIENT_BASIC_STATUS1 0x0048 64 #define PCBS1_LINK_ST(x) (u_int)__SHIFTOUT((x), __BITS(21,20)) 65 #define PCBS1_LS_NO_RECV 0 /* no receivers */ 66 #define PCBS1_LS_TRAINING 1 /* link training */ 67 #define PCBS1_LS_DL_INIT 2 /* link up, DL init progressing */ 68 #define PCBS1_LS_DL_DONE 3 /* link up, DL init complete */ 69 #define PCIE_CLIENT_INT_MASK 0x004c 70 #define PCIM_INTx_MASK(x) SETREG(__BIT((x)+5), 1) 71 #define PCIM_INTx_ENAB(x) SETREG(__BIT((x)+5), 0) 72 73 #define PCIE_CORE_BASE 0x800000 74 #define PCIE_RC_NORMAL_BASE (PCIE_CORE_BASE + 0x00000) 75 76 #define PCIE_LM_BASE 0x900000 77 #define PCIE_LM_CORE_CTRL (PCIE_LM_BASE + 0x00) 78 #define PCIE_CORE_PL_CONF_SPEED_5G 0x00000008 79 #define PCIE_CORE_PL_CONF_SPEED_MASK 0x00000018 80 #define PCIE_CORE_PL_CONF_LANE_MASK 0x00000006 81 #define PCIE_CORE_PL_CONF_LANE_SHIFT 1 82 #define PCIE_LM_PLC1 (PCIE_LM_BASE + 0x04) 83 #define PCIE_LM_PLC1_FTS_MASK __BITS(23, 8) 84 #define PCIE_LM_VENDOR_ID (PCIE_LM_BASE + 0x44) 85 #define PCIE_LM_LINKWIDTH (PCIE_LM_BASE + 0x50) 86 #define PCIE_LM_LANEMAP (PCIE_LM_BASE + 0x200) 87 #define PCIE_LM_DEBUG_MUX_CONTROL (PCIE_LM_BASE + 0x208) 88 #define PCIE_LM_RCBAR (PCIE_LM_BASE + 0x300) 89 #define PCIE_LM_RCBARPME __BIT(17) 90 #define PCIE_LM_RCBARPMS __BIT(18) 91 #define PCIE_LM_RCBARPIE __BIT(19) 92 #define PCIE_LM_RCBARPIS __BIT(20) 93 94 #define PCIE_RC_BASE 0xa00000 95 #define PCIE_RC_CONFIG_DCSR (PCIE_RC_BASE + 0x0c0 + PCIE_DCSR) 96 #define PCIE_RC_PCIE_LCAP (PCIE_RC_BASE + 0x0c0 + PCIE_LCAP) 97 #define PCIE_RC_CONFIG_LCSR (PCIE_RC_BASE + 0x0c0 + PCIE_LCSR) 98 #define PCIE_RC_CONFIG_THP_CAP (PCIE_RC_BASE + 0x274) 99 #define PCIE_RC_CONFIG_THP_CAP_NEXT_MASK __BITS(31, 20) 100 101 102 #define PCIE_ATR_BASE 0xc00000 103 #define PCIE_ATR_OB_ADDR0(i) (PCIE_ATR_BASE + 0x000 + (i) * 0x20) 104 #define PCIE_ATR_OB_ADDR1(i) (PCIE_ATR_BASE + 0x004 + (i) * 0x20) 105 #define PCIE_ATR_OB_DESC0(i) (PCIE_ATR_BASE + 0x008 + (i) * 0x20) 106 #define PCIE_ATR_OB_DESC1(i) (PCIE_ATR_BASE + 0x00c + (i) * 0x20) 107 #define PCIE_ATR_IB_ADDR0(i) (PCIE_ATR_BASE + 0x800 + (i) * 0x8) 108 #define PCIE_ATR_IB_ADDR1(i) (PCIE_ATR_BASE + 0x804 + (i) * 0x8) 109 #define PCIE_ATR_HDR_MEM 0x2 110 #define PCIE_ATR_HDR_IO 0x6 111 #define PCIE_ATR_HDR_CFG_TYPE0 0xa 112 #define PCIE_ATR_HDR_CFG_TYPE1 0xb 113 #define PCIE_ATR_HDR_RID __BIT(23) 114 115 /* AXI region */ 116 #define PCIE_ATR_OB_REGION0_SIZE (32 * 1024 * 1024) 117 #define PCIE_ATR_OB_REGION_SIZE (1 * 1024 * 1024) 118 119 #define HREAD4(sc, reg) \ 120 bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg)) 121 #define HWRITE4(sc, reg, val) \ 122 bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val)) 123 #define AXIPEEK4(sc, reg, valp) \ 124 bus_space_peek_4((sc)->sc_iot, (sc)->sc_axi_ioh, (reg), (valp)) 125 #define AXIPOKE4(sc, reg, val) \ 126 bus_space_poke_4((sc)->sc_iot, (sc)->sc_axi_ioh, (reg), (val)) 127 128 struct rkpcie_softc { 129 struct pcihost_softc sc_phsc; 130 bus_space_tag_t sc_iot; 131 bus_space_handle_t sc_ioh; 132 bus_space_handle_t sc_axi_ioh; 133 bus_addr_t sc_axi_addr; 134 bus_addr_t sc_apb_addr; 135 bus_size_t sc_axi_size; 136 bus_size_t sc_apb_size; 137 kmutex_t sc_conf_lock; 138 }; 139 140 static int rkpcie_match(device_t, cfdata_t, void *); 141 static void rkpcie_attach(device_t, device_t, void *); 142 143 CFATTACH_DECL_NEW(rkpcie, sizeof(struct rkpcie_softc), 144 rkpcie_match, rkpcie_attach, NULL, NULL); 145 146 static const struct device_compatible_entry compat_data[] = { 147 { .compat = "rockchip,rk3399-pcie" }, 148 DEVICE_COMPAT_EOL 149 }; 150 151 static int 152 rkpcie_match(device_t parent, cfdata_t cf, void *aux) 153 { 154 struct fdt_attach_args *faa = aux; 155 156 return of_compatible_match(faa->faa_phandle, compat_data); 157 } 158 159 static void rkpcie_atr_init(struct rkpcie_softc *); 160 161 static int rkpcie_bus_maxdevs(void *, int); 162 static pcitag_t rkpcie_make_tag(void *, int, int, int); 163 static void rkpcie_decompose_tag(void *, pcitag_t, int *, int *, int *); 164 static pcireg_t rkpcie_conf_read(void *, pcitag_t, int); 165 static void rkpcie_conf_write(void *, pcitag_t, int, pcireg_t); 166 static int rkpcie_conf_hook(void *, int, int, int, pcireg_t); 167 168 static struct fdtbus_interrupt_controller_func rkpcie_intrfuncs; 169 170 static inline void 171 clock_enable_all(int phandle) 172 { 173 for (u_int i = 0; i < 4; i++) { 174 struct clk * clk = fdtbus_clock_get_index(phandle, i); 175 if (clk == NULL) 176 continue; 177 if (clk_enable(clk) != 0) 178 continue; 179 } 180 } 181 182 static void 183 reset_assert(int phandle, const char *name) 184 { 185 struct fdtbus_reset *rst; 186 187 rst = fdtbus_reset_get(phandle, name); 188 fdtbus_reset_assert(rst); 189 fdtbus_reset_put(rst); 190 } 191 192 static void 193 reset_deassert(int phandle, const char *name) 194 { 195 struct fdtbus_reset *rst; 196 197 rst = fdtbus_reset_get(phandle, name); 198 fdtbus_reset_deassert(rst); 199 fdtbus_reset_put(rst); 200 } 201 202 static void 203 rkpcie_attach(device_t parent, device_t self, void *aux) 204 { 205 struct rkpcie_softc *sc = device_private(self); 206 struct pcihost_softc * const phsc = &sc->sc_phsc; 207 struct fdt_attach_args *faa = aux; 208 struct fdtbus_gpio_pin *ep_gpio; 209 u_int max_link_speed, num_lanes; 210 struct fdtbus_phy *phy[4]; 211 const u_int *bus_range; 212 uint32_t status; 213 int timo, len; 214 215 phsc->sc_dev = self; 216 phsc->sc_bst = faa->faa_bst; 217 phsc->sc_dmat = faa->faa_dmat; 218 sc->sc_iot = phsc->sc_bst; 219 phsc->sc_phandle = faa->faa_phandle; 220 const int phandle = phsc->sc_phandle; 221 222 if (fdtbus_get_reg_byname(faa->faa_phandle, "axi-base", &sc->sc_axi_addr, &sc->sc_axi_size) != 0) { 223 aprint_error(": couldn't get axi registers\n"); 224 return; 225 } 226 if (fdtbus_get_reg_byname(faa->faa_phandle, "apb-base", &sc->sc_apb_addr, &sc->sc_apb_size) != 0) { 227 aprint_error(": couldn't get apb registers\n"); 228 sc->sc_axi_size = 0; 229 return; 230 } 231 232 const int mapflags = _ARM_BUS_SPACE_MAP_STRONGLY_ORDERED; 233 if (bus_space_map(sc->sc_iot, sc->sc_apb_addr, sc->sc_apb_size, mapflags, &sc->sc_ioh) != 0 || 234 bus_space_map(sc->sc_iot, sc->sc_axi_addr, sc->sc_axi_size, mapflags, &sc->sc_axi_ioh) != 0) { 235 printf(": can't map registers\n"); 236 sc->sc_axi_size = 0; 237 sc->sc_apb_size = 0; 238 return; 239 } 240 241 aprint_naive("\n"); 242 aprint_normal(": RK3399 PCIe\n"); 243 244 struct fdtbus_regulator *regulator; 245 regulator = fdtbus_regulator_acquire(phandle, "vpcie3v3-supply"); 246 if (regulator != NULL) { 247 fdtbus_regulator_enable(regulator); 248 fdtbus_regulator_release(regulator); 249 } 250 251 fdtbus_clock_assign(phandle); 252 clock_enable_all(phandle); 253 254 ep_gpio = fdtbus_gpio_acquire(phandle, "ep-gpios", GPIO_PIN_OUTPUT); 255 256 if (of_getprop_uint32(phandle, "max-link-speed", &max_link_speed) != 0) 257 max_link_speed = 2; 258 if (of_getprop_uint32(phandle, "num-lanes", &num_lanes) != 0) 259 num_lanes = 1; 260 261 again: 262 fdtbus_gpio_write(ep_gpio, 0); 263 264 reset_assert(phandle, "aclk"); 265 reset_assert(phandle, "pclk"); 266 reset_assert(phandle, "pm"); 267 268 memset(phy, 0, sizeof(phy)); 269 phy[0] = fdtbus_phy_get(phandle, "pcie-phy-0"); 270 if (phy[0] == NULL) { 271 phy[0] = fdtbus_phy_get(phandle, "pcie-phy"); 272 } else { 273 phy[1] = fdtbus_phy_get(phandle, "pcie-phy-1"); 274 phy[2] = fdtbus_phy_get(phandle, "pcie-phy-2"); 275 phy[3] = fdtbus_phy_get(phandle, "pcie-phy-3"); 276 } 277 278 reset_assert(phandle, "core"); 279 reset_assert(phandle, "mgmt"); 280 reset_assert(phandle, "mgmt-sticky"); 281 reset_assert(phandle, "pipe"); 282 283 delay(1000); /* TPERST. use 1ms */ 284 285 reset_deassert(phandle, "pm"); 286 reset_deassert(phandle, "aclk"); 287 reset_deassert(phandle, "pclk"); 288 289 if (max_link_speed == 1) 290 HWRITE4(sc, PCIE_CLIENT_BASIC_STRAP_CONF, PCBSC_PGS_GEN1); 291 else 292 HWRITE4(sc, PCIE_CLIENT_BASIC_STRAP_CONF, PCBSC_PGS_GEN2); 293 294 /* Switch into Root Complex mode. */ 295 HWRITE4(sc, PCIE_CLIENT_BASIC_STRAP_CONF, 296 PCBSC_MS_ROOTPORT | PCBSC_CONF_EN | PCBSC_LC(num_lanes)); 297 298 if (phy[3] && fdtbus_phy_enable(phy[3], true) != 0) { 299 aprint_error(": couldn't enable phy3\n"); 300 } 301 if (phy[2] && fdtbus_phy_enable(phy[2], true) != 0) { 302 aprint_error(": couldn't enable phy2\n"); 303 } 304 if (phy[1] && fdtbus_phy_enable(phy[1], true) != 0) { 305 aprint_error(": couldn't enable phy1\n"); 306 } 307 if (phy[0] && fdtbus_phy_enable(phy[0], true) != 0) { 308 aprint_error(": couldn't enable phy0\n"); 309 } 310 311 reset_deassert(phandle, "mgmt-sticky"); 312 reset_deassert(phandle, "core"); 313 reset_deassert(phandle, "mgmt"); 314 reset_deassert(phandle, "pipe"); 315 316 fdtbus_gpio_write(ep_gpio, 1); 317 delay(20000); /* 20 ms according to PCI-e BS "Conventional Reset" */ 318 319 /* Start link training. */ 320 HWRITE4(sc, PCIE_CLIENT_BASIC_STRAP_CONF, PCBSC_LINK_TRAIN_EN); 321 322 for (timo = 500; timo > 0; timo--) { 323 status = HREAD4(sc, PCIE_CLIENT_BASIC_STATUS1); 324 if (PCBS1_LINK_ST(status) == PCBS1_LS_DL_DONE) 325 break; 326 delay(1000); 327 } 328 if (timo == 0) { 329 device_printf(self, "link training timeout (link_st %u)\n", 330 PCBS1_LINK_ST(status)); 331 if (max_link_speed > 1) { 332 --max_link_speed; 333 goto again; 334 } 335 return; 336 } 337 338 if (max_link_speed == 2) { 339 HWRITE4(sc, PCIE_RC_CONFIG_LCSR, HREAD4(sc, PCIE_RC_CONFIG_LCSR) | PCIE_LCSR_RETRAIN); 340 for (timo = 500; timo > 0; timo--) { 341 status = HREAD4(sc, PCIE_LM_CORE_CTRL); 342 if ((status & PCIE_CORE_PL_CONF_SPEED_MASK) == PCIE_CORE_PL_CONF_SPEED_5G) 343 break; 344 delay(1000); 345 } 346 if (timo == 0) { 347 device_printf(self, "Gen2 link training timeout\n"); 348 --max_link_speed; 349 goto again; 350 } 351 } 352 delay(80000); /* wait 100 ms before CSR access. already waited 20. */ 353 354 fdtbus_gpio_release(ep_gpio); 355 356 HWRITE4(sc, PCIE_RC_BASE + PCI_CLASS_REG, 357 PCI_CLASS_BRIDGE << PCI_CLASS_SHIFT | 358 PCI_SUBCLASS_BRIDGE_PCI << PCI_SUBCLASS_SHIFT); 359 360 /* Initialize Root Complex registers. */ 361 HWRITE4(sc, PCIE_LM_VENDOR_ID, PCI_VENDOR_ROCKCHIP); 362 HWRITE4(sc, PCIE_RC_BASE + PCI_CLASS_REG, 363 PCI_CLASS_BRIDGE << PCI_CLASS_SHIFT | 364 PCI_SUBCLASS_BRIDGE_PCI << PCI_SUBCLASS_SHIFT); 365 HWRITE4(sc, PCIE_LM_RCBAR, PCIE_LM_RCBARPIE | PCIE_LM_RCBARPIS); 366 367 /* remove L1 substate cap */ 368 status = HREAD4(sc, PCIE_RC_CONFIG_THP_CAP); 369 status &= ~PCIE_RC_CONFIG_THP_CAP_NEXT_MASK; 370 HWRITE4(sc, PCIE_RC_CONFIG_THP_CAP, status); 371 372 if (of_hasprop(phandle, "aspm-no-l0s")) { 373 status = HREAD4(sc, PCIE_RC_PCIE_LCAP); 374 status &= ~__SHIFTIN(1, PCIE_LCAP_ASPM); 375 HWRITE4(sc, PCIE_RC_PCIE_LCAP, status); 376 } 377 378 /* Default bus ranges */ 379 sc->sc_phsc.sc_bus_min = 0; 380 sc->sc_phsc.sc_bus_max = 31; 381 382 /* Override bus range from DT */ 383 bus_range = fdtbus_get_prop(phandle, "bus-range", &len); 384 if (len == 8) { 385 sc->sc_phsc.sc_bus_min = be32dec(&bus_range[0]); 386 sc->sc_phsc.sc_bus_max = be32dec(&bus_range[1]); 387 } 388 389 if (sc->sc_phsc.sc_bus_min != 0) { 390 aprint_error_dev(self, "bus-range doesn't start at 0\n"); 391 return; 392 } 393 394 /* Configure Address Translation. */ 395 rkpcie_atr_init(sc); 396 397 fdtbus_register_interrupt_controller(self, OF_child(sc->sc_phsc.sc_phandle), 398 &rkpcie_intrfuncs); 399 400 sc->sc_phsc.sc_type = PCIHOST_ECAM; 401 sc->sc_phsc.sc_pci_flags |= PCI_FLAGS_MSI_OKAY; 402 sc->sc_phsc.sc_pci_flags |= PCI_FLAGS_MSIX_OKAY; 403 pcihost_init(&sc->sc_phsc.sc_pc, sc); 404 sc->sc_phsc.sc_pc.pc_bus_maxdevs = rkpcie_bus_maxdevs; 405 sc->sc_phsc.sc_pc.pc_make_tag = rkpcie_make_tag; 406 sc->sc_phsc.sc_pc.pc_decompose_tag = rkpcie_decompose_tag; 407 sc->sc_phsc.sc_pc.pc_conf_read = rkpcie_conf_read; 408 sc->sc_phsc.sc_pc.pc_conf_write = rkpcie_conf_write; 409 sc->sc_phsc.sc_pc.pc_conf_hook = rkpcie_conf_hook; 410 411 mutex_init(&sc->sc_conf_lock, MUTEX_DEFAULT, IPL_HIGH); 412 pcihost_init2(&sc->sc_phsc); 413 } 414 415 static void 416 rkpcie_atr_init(struct rkpcie_softc *sc) 417 { 418 const u_int *ranges; 419 bus_addr_t aaddr; 420 bus_addr_t addr; 421 bus_size_t size, resid, offset; 422 uint32_t type; 423 int region, i, ranges_len; 424 425 /* Use region 0 to map PCI configuration space */ 426 HWRITE4(sc, PCIE_ATR_OB_ADDR0(0), 20 - 1); 427 HWRITE4(sc, PCIE_ATR_OB_ADDR1(0), 0); 428 HWRITE4(sc, PCIE_ATR_OB_DESC0(0), PCIE_ATR_HDR_CFG_TYPE0 | PCIE_ATR_HDR_RID); 429 HWRITE4(sc, PCIE_ATR_OB_DESC1(0), 0); 430 431 ranges = fdtbus_get_prop(sc->sc_phsc.sc_phandle, "ranges", &ranges_len); 432 if (ranges == NULL) 433 goto fail; 434 const int ranges_cells = ranges_len / 4; 435 436 for (i = 0; i < ranges_cells; i += 7) { 437 /* Handle IO and MMIO. */ 438 switch (be32toh(ranges[i]) & 0x03000000) { 439 case 0x01000000: 440 type = PCIE_ATR_HDR_IO; 441 break; 442 case 0x02000000: 443 case 0x03000000: 444 type = PCIE_ATR_HDR_MEM; 445 break; 446 default: 447 continue; 448 } 449 450 addr = ((uint64_t)be32toh(ranges[i + 1]) << 32) + be32toh(ranges[i + 2]); 451 aaddr = ((uint64_t)be32toh(ranges[i + 3]) << 32) + be32toh(ranges[i + 4]); 452 size = be32toh(ranges[i + 6]); 453 454 /* Only support mappings aligned on a region boundary. */ 455 if (addr & (PCIE_ATR_OB_REGION_SIZE - 1)) 456 goto fail; 457 if (aaddr & (PCIE_ATR_OB_REGION_SIZE - 1)) 458 goto fail; 459 if (size & (PCIE_ATR_OB_REGION_SIZE - 1)) 460 goto fail; 461 462 /* Mappings should lie in AXI region. */ 463 if (aaddr < sc->sc_axi_addr) 464 goto fail; 465 if (aaddr + size > sc->sc_axi_addr + 64*1024*1024) 466 goto fail; 467 468 offset = addr - sc->sc_axi_addr - PCIE_ATR_OB_REGION0_SIZE; 469 region = 1 + (offset / PCIE_ATR_OB_REGION_SIZE); 470 resid = size; 471 while (resid > 0) { 472 HWRITE4(sc, PCIE_ATR_OB_ADDR0(region), 32 - 1); 473 HWRITE4(sc, PCIE_ATR_OB_ADDR1(region), 0); 474 HWRITE4(sc, PCIE_ATR_OB_DESC0(region), type | PCIE_ATR_HDR_RID); 475 HWRITE4(sc, PCIE_ATR_OB_DESC1(region), 0); 476 477 addr += PCIE_ATR_OB_REGION_SIZE; 478 resid -= PCIE_ATR_OB_REGION_SIZE; 479 region++; 480 } 481 } 482 483 /* Passthrought inbound translations unmodified. */ 484 HWRITE4(sc, PCIE_ATR_IB_ADDR0(2), 32 - 1); 485 HWRITE4(sc, PCIE_ATR_IB_ADDR1(2), 0); 486 487 return; 488 489 fail: 490 device_printf(sc->sc_phsc.sc_dev, "can't map ranges\n"); 491 } 492 493 int 494 rkpcie_bus_maxdevs(void *v, int bus) 495 { 496 struct rkpcie_softc *rksc = v; 497 struct pcihost_softc *sc = &rksc->sc_phsc; 498 499 if (bus == sc->sc_bus_min || bus == sc->sc_bus_min + 1) 500 return 1; 501 return 32; 502 } 503 504 pcitag_t 505 rkpcie_make_tag(void *v, int bus, int device, int function) 506 { 507 /* Return ECAM address. */ 508 return ((bus << 20) | (device << 15) | (function << 12)); 509 } 510 511 void 512 rkpcie_decompose_tag(void *v, pcitag_t tag, int *bp, int *dp, int *fp) 513 { 514 if (bp != NULL) 515 *bp = (tag >> 20) & 0xff; 516 if (dp != NULL) 517 *dp = (tag >> 15) & 0x1f; 518 if (fp != NULL) 519 *fp = (tag >> 12) & 0x7; 520 } 521 522 /* Only one device on root port and the first subordinate port. */ 523 static bool 524 rkpcie_conf_ok(int bus, int dev, int fn, int offset, struct rkpcie_softc *sc) 525 { 526 int bus_min = sc->sc_phsc.sc_bus_min; 527 528 if ((unsigned int)offset >= (1<<12)) 529 return false; 530 /* first two buses use type 0 cfg which doesn't use bus/device numbers */ 531 if (dev != 0 && (bus == bus_min || bus == bus_min + 1)) 532 return false; 533 return true; 534 } 535 536 pcireg_t 537 rkpcie_conf_read(void *v, pcitag_t tag, int offset) 538 { 539 struct rkpcie_softc *sc = v; 540 int bus_min = sc->sc_phsc.sc_bus_min; 541 int bus, dev, fn; 542 u_int reg; 543 int32_t val; 544 545 KASSERT(offset >= 0); 546 KASSERT(offset < PCI_EXTCONF_SIZE); 547 548 rkpcie_decompose_tag(sc, tag, &bus, &dev, &fn); 549 if (!rkpcie_conf_ok(bus, dev, fn, offset, sc)) 550 return 0xffffffff; 551 reg = (dev << 15) | (fn << 12) | offset; 552 553 if (bus == bus_min) 554 val = HREAD4(sc, PCIE_RC_NORMAL_BASE + reg); 555 else { 556 mutex_spin_enter(&sc->sc_conf_lock); 557 HWRITE4(sc, PCIE_ATR_OB_ADDR0(0), 558 (bus << 20) | (20 - 1)); 559 HWRITE4(sc, PCIE_ATR_OB_DESC0(0), 560 PCIE_ATR_HDR_RID | ((bus == bus_min + 1) 561 ? PCIE_ATR_HDR_CFG_TYPE0 : PCIE_ATR_HDR_CFG_TYPE1)); 562 bus_space_barrier(sc->sc_iot, sc->sc_ioh, 0, sc->sc_apb_size, 563 BUS_SPACE_BARRIER_READ); 564 if (AXIPEEK4(sc, reg, &val) != 0) 565 val = 0xffffffff; 566 bus_space_barrier(sc->sc_iot, sc->sc_axi_ioh, 567 0, sc->sc_axi_size, 568 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 569 mutex_spin_exit(&sc->sc_conf_lock); 570 } 571 return val; 572 } 573 574 void 575 rkpcie_conf_write(void *v, pcitag_t tag, int offset, pcireg_t data) 576 { 577 struct rkpcie_softc *sc = v; 578 int bus_min = sc->sc_phsc.sc_bus_min; 579 int bus, dev, fn; 580 u_int reg; 581 582 KASSERT(offset >= 0); 583 KASSERT(offset < PCI_EXTCONF_SIZE); 584 585 rkpcie_decompose_tag(sc, tag, &bus, &dev, &fn); 586 if (!rkpcie_conf_ok(bus, dev, fn, offset, sc)) 587 return; 588 reg = (dev << 15) | (fn << 12) | offset; 589 590 if (bus == bus_min) 591 HWRITE4(sc, PCIE_RC_NORMAL_BASE + reg, data); 592 else { 593 mutex_spin_enter(&sc->sc_conf_lock); 594 HWRITE4(sc, PCIE_ATR_OB_ADDR0(0), 595 (bus << 20) | (20 - 1)); 596 HWRITE4(sc, PCIE_ATR_OB_DESC0(0), 597 PCIE_ATR_HDR_RID | ((bus == bus_min + 1) 598 ? PCIE_ATR_HDR_CFG_TYPE0 : PCIE_ATR_HDR_CFG_TYPE1)); 599 bus_space_barrier(sc->sc_iot, sc->sc_ioh, 0, sc->sc_apb_size, 600 BUS_SPACE_BARRIER_WRITE); 601 AXIPOKE4(sc, reg, data); 602 bus_space_barrier(sc->sc_iot, sc->sc_axi_ioh, 603 0, sc->sc_axi_size, 604 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 605 mutex_spin_exit(&sc->sc_conf_lock); 606 } 607 } 608 609 static int 610 rkpcie_conf_hook(void *v, int b, int d, int f, pcireg_t id) 611 { 612 return (PCI_CONF_DEFAULT & ~PCI_CONF_ENABLE_BM) | PCI_CONF_MAP_ROM; 613 } 614 615 /* INTx interrupt controller */ 616 static void * 617 rkpcie_intx_establish(device_t dev, u_int *specifier, int ipl, int flags, 618 int (*func)(void *), void *arg, const char *xname) 619 { 620 struct rkpcie_softc *sc = device_private(dev); 621 void *cookie; 622 623 #if notyet 624 const u_int pin = be32toh(specifier[0]); 625 #endif 626 627 /* Unmask legacy interrupts. */ 628 HWRITE4(sc, PCIE_CLIENT_INT_MASK, 629 PCIM_INTx_ENAB(0) | PCIM_INTx_ENAB(1) | 630 PCIM_INTx_ENAB(2) | PCIM_INTx_ENAB(3)); 631 632 cookie = fdtbus_intr_establish_byname(sc->sc_phsc.sc_phandle, 633 "legacy", ipl, flags, func, arg, xname); 634 635 return cookie; 636 } 637 638 static void 639 rkpcie_intx_disestablish(device_t dev, void *ih) 640 { 641 struct rkpcie_softc *sc = device_private(dev); 642 device_printf(dev, "%s\n", __func__); 643 fdtbus_intr_disestablish(sc->sc_phsc.sc_phandle, ih); 644 } 645 646 static bool 647 rkpcie_intx_intrstr(device_t dev, u_int *specifier, char *buf, size_t buflen) 648 { 649 struct rkpcie_softc *sc = device_private(dev); 650 651 fdtbus_intr_str(sc->sc_phsc.sc_phandle, 1, buf, buflen); 652 653 return true; 654 } 655 656 static struct fdtbus_interrupt_controller_func rkpcie_intrfuncs = { 657 .establish = rkpcie_intx_establish, 658 .disestablish = rkpcie_intx_disestablish, 659 .intrstr = rkpcie_intx_intrstr, 660 }; 661
Indexes created Thu Oct 02 10:09:58 GMT 2025