rk3399_pcie.c revision 1.17
1 /* $NetBSD: rk3399_pcie.c,v 1.17 2021/09/06 14:03:17 jmcneill Exp $ */ 2 /* 3 * Copyright (c) 2018 Mark Kettenis <kettenis (at) openbsd.org> 4 * 5 * Permission to use, copy, modify, and distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 */ 17 18 #include <sys/cdefs.h> 19 20 __KERNEL_RCSID(1, "$NetBSD: rk3399_pcie.c,v 1.17 2021/09/06 14:03:17 jmcneill Exp $"); 21 22 #include <sys/param.h> 23 #include <sys/systm.h> 24 #include <sys/bitops.h> 25 #include <sys/device.h> 26 #include <sys/kmem.h> 27 28 #include <machine/intr.h> 29 #include <sys/bus.h> 30 #include <dev/fdt/fdtvar.h> 31 #include <dev/fdt/syscon.h> 32 #include <arm/cpufunc.h> 33 34 #include <dev/pci/pcidevs.h> 35 #include <dev/pci/pcireg.h> 36 #include <dev/pci/pcivar.h> 37 #include <dev/pci/pciconf.h> 38 39 #include <arm/fdt/pcihost_fdtvar.h> 40 #include <sys/gpio.h> 41 42 #define SETREG(m, v) ((m)<<16|__SHIFTIN((v), (m))) 43 #define GETREG(m, v) (__SHIFTOUT((v), (m))) 44 45 /* APB region */ 46 #define PCIE_CLIENT_BASE 0x000000 47 #define PCIE_CLIENT_BASIC_STRAP_CONF 0x0000 48 #define PCBSC_PCIE_GEN_SEL __BIT(7) 49 #define PCBSC_PGS_GEN1 SETREG(PCBSC_PCIE_GEN_SEL, 0) 50 #define PCBSC_PGS_GEN2 SETREG(PCBSC_PCIE_GEN_SEL, 1) 51 #define PCBSC_MODE_SELECT __BIT(6) 52 #define PCBSC_MS_ENDPOINT SETREG(PCBSC_MODE_SELECT, 0) 53 #define PCBSC_MS_ROOTPORT SETREG(PCBSC_MODE_SELECT, 1) 54 #define PCBSC_LANE_COUNT __BITS(5,4) 55 #define PCBSC_LC(x) SETREG(PCBSC_LANE_COUNT, ilog2(x)) /* valid for x1,2,4 */ 56 #define PCBSC_ARI_EN SETREG(__BIT(3), 1) /* Alternate Routing ID Enable */ 57 #define PCBSC_SR_IOV_EN SETREG(__BIT(2), 1) 58 #define PCBSC_LINK_TRAIN_EN SETREG(__BIT(1), 1) 59 #define PCBSC_CONF_EN SETREG(__BIT(0), 1) /* Config enable */ 60 #define PCIE_CLIENT_DEBUG_OUT_0 0x003c 61 #define PCIE_CLIENT_DEBUG_OUT_1 0x0040 62 #define PCIE_CLIENT_BASIC_STATUS0 0x0044 63 #define PCIE_CLIENT_BASIC_STATUS1 0x0048 64 #define PCBS1_LINK_ST(x) (u_int)__SHIFTOUT((x), __BITS(21,20)) 65 #define PCBS1_LS_NO_RECV 0 /* no receivers */ 66 #define PCBS1_LS_TRAINING 1 /* link training */ 67 #define PCBS1_LS_DL_INIT 2 /* link up, DL init progressing */ 68 #define PCBS1_LS_DL_DONE 3 /* link up, DL init complete */ 69 #define PCIE_CLIENT_INT_MASK 0x004c 70 #define PCIM_INTx_MASK(x) SETREG(__BIT((x)+5), 1) 71 #define PCIM_INTx_ENAB(x) SETREG(__BIT((x)+5), 0) 72 73 #define PCIE_CORE_BASE 0x800000 74 #define PCIE_RC_NORMAL_BASE (PCIE_CORE_BASE + 0x00000) 75 76 #define PCIE_LM_BASE 0x900000 77 #define PCIE_LM_CORE_CTRL (PCIE_LM_BASE + 0x00) 78 #define PCIE_CORE_PL_CONF_SPEED_5G 0x00000008 79 #define PCIE_CORE_PL_CONF_SPEED_MASK 0x00000018 80 #define PCIE_CORE_PL_CONF_LANE_MASK 0x00000006 81 #define PCIE_CORE_PL_CONF_LANE_SHIFT 1 82 #define PCIE_LM_PLC1 (PCIE_LM_BASE + 0x04) 83 #define PCIE_LM_PLC1_FTS_MASK __BITS(23, 8) 84 #define PCIE_LM_VENDOR_ID (PCIE_LM_BASE + 0x44) 85 #define PCIE_LM_LINKWIDTH (PCIE_LM_BASE + 0x50) 86 #define PCIE_LM_LANEMAP (PCIE_LM_BASE + 0x200) 87 #define PCIE_LM_DEBUG_MUX_CONTROL (PCIE_LM_BASE + 0x208) 88 #define PCIE_LM_RCBAR (PCIE_LM_BASE + 0x300) 89 #define PCIE_LM_RCBARPME __BIT(17) 90 #define PCIE_LM_RCBARPMS __BIT(18) 91 #define PCIE_LM_RCBARPIE __BIT(19) 92 #define PCIE_LM_RCBARPIS __BIT(20) 93 94 #define PCIE_RC_BASE 0xa00000 95 #define PCIE_RC_CONFIG_DCSR (PCIE_RC_BASE + 0x0c0 + PCIE_DCSR) 96 #define PCIE_RC_PCIE_LCAP (PCIE_RC_BASE + 0x0c0 + PCIE_LCAP) 97 #define PCIE_RC_CONFIG_LCSR (PCIE_RC_BASE + 0x0c0 + PCIE_LCSR) 98 #define PCIE_RC_CONFIG_THP_CAP (PCIE_RC_BASE + 0x274) 99 #define PCIE_RC_CONFIG_THP_CAP_NEXT_MASK __BITS(31, 20) 100 101 102 #define PCIE_ATR_BASE 0xc00000 103 #define PCIE_ATR_OB_ADDR0(i) (PCIE_ATR_BASE + 0x000 + (i) * 0x20) 104 #define PCIE_ATR_OB_ADDR1(i) (PCIE_ATR_BASE + 0x004 + (i) * 0x20) 105 #define PCIE_ATR_OB_DESC0(i) (PCIE_ATR_BASE + 0x008 + (i) * 0x20) 106 #define PCIE_ATR_OB_DESC1(i) (PCIE_ATR_BASE + 0x00c + (i) * 0x20) 107 #define PCIE_ATR_IB_ADDR0(i) (PCIE_ATR_BASE + 0x800 + (i) * 0x8) 108 #define PCIE_ATR_IB_ADDR1(i) (PCIE_ATR_BASE + 0x804 + (i) * 0x8) 109 #define PCIE_ATR_HDR_MEM 0x2 110 #define PCIE_ATR_HDR_IO 0x6 111 #define PCIE_ATR_HDR_CFG_TYPE0 0xa 112 #define PCIE_ATR_HDR_CFG_TYPE1 0xb 113 #define PCIE_ATR_HDR_RID __BIT(23) 114 115 /* AXI region */ 116 #define PCIE_ATR_OB_REGION0_SIZE (32 * 1024 * 1024) 117 #define PCIE_ATR_OB_REGION_SIZE (1 * 1024 * 1024) 118 119 #define HREAD4(sc, reg) \ 120 bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg)) 121 #define HWRITE4(sc, reg, val) \ 122 bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val)) 123 #define AXIPEEK4(sc, reg, valp) \ 124 bus_space_peek_4((sc)->sc_iot, (sc)->sc_axi_ioh, (reg), (valp)) 125 #define AXIPOKE4(sc, reg, val) \ 126 bus_space_poke_4((sc)->sc_iot, (sc)->sc_axi_ioh, (reg), (val)) 127 128 struct rkpcie_softc { 129 struct pcihost_softc sc_phsc; 130 bus_space_tag_t sc_iot; 131 bus_space_handle_t sc_ioh; 132 bus_space_handle_t sc_axi_ioh; 133 bus_addr_t sc_axi_addr; 134 bus_addr_t sc_apb_addr; 135 bus_size_t sc_axi_size; 136 bus_size_t sc_apb_size; 137 kmutex_t sc_conf_lock; 138 }; 139 140 static int rkpcie_match(device_t, cfdata_t, void *); 141 static void rkpcie_attach(device_t, device_t, void *); 142 143 CFATTACH_DECL_NEW(rkpcie, sizeof(struct rkpcie_softc), 144 rkpcie_match, rkpcie_attach, NULL, NULL); 145 146 static const struct device_compatible_entry compat_data[] = { 147 { .compat = "rockchip,rk3399-pcie" }, 148 DEVICE_COMPAT_EOL 149 }; 150 151 static int 152 rkpcie_match(device_t parent, cfdata_t cf, void *aux) 153 { 154 struct fdt_attach_args *faa = aux; 155 156 return of_compatible_match(faa->faa_phandle, compat_data); 157 } 158 159 static void rkpcie_atr_init(struct rkpcie_softc *); 160 161 static int rkpcie_bus_maxdevs(void *, int); 162 static pcitag_t rkpcie_make_tag(void *, int, int, int); 163 static void rkpcie_decompose_tag(void *, pcitag_t, int *, int *, int *); 164 static pcireg_t rkpcie_conf_read(void *, pcitag_t, int); 165 static void rkpcie_conf_write(void *, pcitag_t, int, pcireg_t); 166 static int rkpcie_conf_hook(void *, int, int, int, pcireg_t); 167 168 static struct fdtbus_interrupt_controller_func rkpcie_intrfuncs; 169 170 static inline void 171 clock_enable_all(int phandle) 172 { 173 for (u_int i = 0; i < 4; i++) { 174 struct clk * clk = fdtbus_clock_get_index(phandle, i); 175 if (clk == NULL) 176 continue; 177 if (clk_enable(clk) != 0) 178 continue; 179 } 180 } 181 182 static void 183 reset_assert(int phandle, const char *name) 184 { 185 struct fdtbus_reset *rst; 186 187 rst = fdtbus_reset_get(phandle, name); 188 fdtbus_reset_assert(rst); 189 fdtbus_reset_put(rst); 190 } 191 192 static void 193 reset_deassert(int phandle, const char *name) 194 { 195 struct fdtbus_reset *rst; 196 197 rst = fdtbus_reset_get(phandle, name); 198 fdtbus_reset_deassert(rst); 199 fdtbus_reset_put(rst); 200 } 201 202 static void 203 rkpcie_attach(device_t parent, device_t self, void *aux) 204 { 205 struct rkpcie_softc *sc = device_private(self); 206 struct pcihost_softc * const phsc = &sc->sc_phsc; 207 struct fdt_attach_args *faa = aux; 208 struct fdtbus_gpio_pin *ep_gpio; 209 u_int max_link_speed, num_lanes, bus_scan_delay_ms; 210 struct fdtbus_phy *phy[4]; 211 const u_int *bus_range; 212 uint32_t status; 213 uint32_t delayed_ms = 0; 214 int timo, len; 215 216 phsc->sc_dev = self; 217 phsc->sc_bst = faa->faa_bst; 218 phsc->sc_pci_bst = faa->faa_bst; 219 phsc->sc_dmat = faa->faa_dmat; 220 sc->sc_iot = phsc->sc_bst; 221 phsc->sc_phandle = faa->faa_phandle; 222 const int phandle = phsc->sc_phandle; 223 224 if (fdtbus_get_reg_byname(faa->faa_phandle, "axi-base", &sc->sc_axi_addr, &sc->sc_axi_size) != 0) { 225 aprint_error(": couldn't get axi registers\n"); 226 return; 227 } 228 if (fdtbus_get_reg_byname(faa->faa_phandle, "apb-base", &sc->sc_apb_addr, &sc->sc_apb_size) != 0) { 229 aprint_error(": couldn't get apb registers\n"); 230 sc->sc_axi_size = 0; 231 return; 232 } 233 234 const int mapflags = _ARM_BUS_SPACE_MAP_STRONGLY_ORDERED; 235 if (bus_space_map(sc->sc_iot, sc->sc_apb_addr, sc->sc_apb_size, mapflags, &sc->sc_ioh) != 0 || 236 bus_space_map(sc->sc_iot, sc->sc_axi_addr, sc->sc_axi_size, mapflags, &sc->sc_axi_ioh) != 0) { 237 printf(": can't map registers\n"); 238 sc->sc_axi_size = 0; 239 sc->sc_apb_size = 0; 240 return; 241 } 242 243 aprint_naive("\n"); 244 aprint_normal(": RK3399 PCIe\n"); 245 246 struct fdtbus_regulator *regulator; 247 regulator = fdtbus_regulator_acquire(phandle, "vpcie3v3-supply"); 248 if (regulator != NULL) { 249 fdtbus_regulator_enable(regulator); 250 fdtbus_regulator_release(regulator); 251 } 252 253 fdtbus_clock_assign(phandle); 254 clock_enable_all(phandle); 255 256 ep_gpio = fdtbus_gpio_acquire(phandle, "ep-gpios", GPIO_PIN_OUTPUT); 257 258 if (of_getprop_uint32(phandle, "max-link-speed", &max_link_speed) != 0) 259 max_link_speed = 2; 260 if (of_getprop_uint32(phandle, "num-lanes", &num_lanes) != 0) 261 num_lanes = 1; 262 263 /* 264 * If the DT has a "bus-scan-delay-ms" property, delay attaching the 265 * PCI bus this many microseconds. 266 */ 267 if (of_getprop_uint32(phandle, "bus-scan-delay-ms", 268 &bus_scan_delay_ms) != 0) 269 bus_scan_delay_ms = 0; 270 271 again: 272 fdtbus_gpio_write(ep_gpio, 0); 273 274 reset_assert(phandle, "aclk"); 275 reset_assert(phandle, "pclk"); 276 reset_assert(phandle, "pm"); 277 278 memset(phy, 0, sizeof(phy)); 279 phy[0] = fdtbus_phy_get(phandle, "pcie-phy-0"); 280 if (phy[0] == NULL) { 281 phy[0] = fdtbus_phy_get(phandle, "pcie-phy"); 282 } else { 283 phy[1] = fdtbus_phy_get(phandle, "pcie-phy-1"); 284 phy[2] = fdtbus_phy_get(phandle, "pcie-phy-2"); 285 phy[3] = fdtbus_phy_get(phandle, "pcie-phy-3"); 286 } 287 288 reset_assert(phandle, "core"); 289 reset_assert(phandle, "mgmt"); 290 reset_assert(phandle, "mgmt-sticky"); 291 reset_assert(phandle, "pipe"); 292 293 delay(1000); /* TPERST. use 1ms */ 294 delayed_ms += 1; 295 296 reset_deassert(phandle, "pm"); 297 reset_deassert(phandle, "aclk"); 298 reset_deassert(phandle, "pclk"); 299 300 if (max_link_speed == 1) 301 HWRITE4(sc, PCIE_CLIENT_BASIC_STRAP_CONF, PCBSC_PGS_GEN1); 302 else 303 HWRITE4(sc, PCIE_CLIENT_BASIC_STRAP_CONF, PCBSC_PGS_GEN2); 304 305 /* Switch into Root Complex mode. */ 306 HWRITE4(sc, PCIE_CLIENT_BASIC_STRAP_CONF, 307 PCBSC_MS_ROOTPORT | PCBSC_CONF_EN | PCBSC_LC(num_lanes)); 308 309 if (phy[3] && fdtbus_phy_enable(phy[3], true) != 0) { 310 aprint_error(": couldn't enable phy3\n"); 311 } 312 if (phy[2] && fdtbus_phy_enable(phy[2], true) != 0) { 313 aprint_error(": couldn't enable phy2\n"); 314 } 315 if (phy[1] && fdtbus_phy_enable(phy[1], true) != 0) { 316 aprint_error(": couldn't enable phy1\n"); 317 } 318 if (phy[0] && fdtbus_phy_enable(phy[0], true) != 0) { 319 aprint_error(": couldn't enable phy0\n"); 320 } 321 322 reset_deassert(phandle, "mgmt-sticky"); 323 reset_deassert(phandle, "core"); 324 reset_deassert(phandle, "mgmt"); 325 reset_deassert(phandle, "pipe"); 326 327 fdtbus_gpio_write(ep_gpio, 1); 328 delay(20000); /* 20 ms according to PCI-e BS "Conventional Reset" */ 329 delayed_ms += 20; 330 331 /* Start link training. */ 332 HWRITE4(sc, PCIE_CLIENT_BASIC_STRAP_CONF, PCBSC_LINK_TRAIN_EN); 333 334 for (timo = 500; timo > 0; timo--) { 335 status = HREAD4(sc, PCIE_CLIENT_BASIC_STATUS1); 336 if (PCBS1_LINK_ST(status) == PCBS1_LS_DL_DONE) 337 break; 338 delay(1000); 339 delayed_ms += 1; 340 } 341 if (timo == 0) { 342 device_printf(self, "link training timeout (link_st %u)\n", 343 PCBS1_LINK_ST(status)); 344 if (max_link_speed > 1) { 345 --max_link_speed; 346 goto again; 347 } 348 return; 349 } 350 351 if (max_link_speed == 2) { 352 HWRITE4(sc, PCIE_RC_CONFIG_LCSR, HREAD4(sc, PCIE_RC_CONFIG_LCSR) | PCIE_LCSR_RETRAIN); 353 for (timo = 500; timo > 0; timo--) { 354 status = HREAD4(sc, PCIE_LM_CORE_CTRL); 355 if ((status & PCIE_CORE_PL_CONF_SPEED_MASK) == PCIE_CORE_PL_CONF_SPEED_5G) 356 break; 357 delay(1000); 358 delayed_ms += 1; 359 } 360 if (timo == 0) { 361 device_printf(self, "Gen2 link training timeout\n"); 362 --max_link_speed; 363 goto again; 364 } 365 } 366 delay(80000); /* wait 100 ms before CSR access. already waited 20. */ 367 delayed_ms += 80; 368 369 fdtbus_gpio_release(ep_gpio); 370 371 HWRITE4(sc, PCIE_RC_BASE + PCI_CLASS_REG, 372 PCI_CLASS_BRIDGE << PCI_CLASS_SHIFT | 373 PCI_SUBCLASS_BRIDGE_PCI << PCI_SUBCLASS_SHIFT); 374 375 /* Initialize Root Complex registers. */ 376 HWRITE4(sc, PCIE_LM_VENDOR_ID, PCI_VENDOR_ROCKCHIP); 377 HWRITE4(sc, PCIE_RC_BASE + PCI_CLASS_REG, 378 PCI_CLASS_BRIDGE << PCI_CLASS_SHIFT | 379 PCI_SUBCLASS_BRIDGE_PCI << PCI_SUBCLASS_SHIFT); 380 HWRITE4(sc, PCIE_LM_RCBAR, PCIE_LM_RCBARPIE | PCIE_LM_RCBARPIS); 381 382 /* remove L1 substate cap */ 383 status = HREAD4(sc, PCIE_RC_CONFIG_THP_CAP); 384 status &= ~PCIE_RC_CONFIG_THP_CAP_NEXT_MASK; 385 HWRITE4(sc, PCIE_RC_CONFIG_THP_CAP, status); 386 387 if (of_hasprop(phandle, "aspm-no-l0s")) { 388 status = HREAD4(sc, PCIE_RC_PCIE_LCAP); 389 status &= ~__SHIFTIN(1, PCIE_LCAP_ASPM); 390 HWRITE4(sc, PCIE_RC_PCIE_LCAP, status); 391 } 392 393 /* Default bus ranges */ 394 sc->sc_phsc.sc_bus_min = 0; 395 sc->sc_phsc.sc_bus_max = 31; 396 397 /* Override bus range from DT */ 398 bus_range = fdtbus_get_prop(phandle, "bus-range", &len); 399 if (len == 8) { 400 sc->sc_phsc.sc_bus_min = be32dec(&bus_range[0]); 401 sc->sc_phsc.sc_bus_max = be32dec(&bus_range[1]); 402 } 403 404 if (sc->sc_phsc.sc_bus_min != 0) { 405 aprint_error_dev(self, "bus-range doesn't start at 0\n"); 406 return; 407 } 408 409 /* Configure Address Translation. */ 410 rkpcie_atr_init(sc); 411 412 fdtbus_register_interrupt_controller(self, OF_child(sc->sc_phsc.sc_phandle), 413 &rkpcie_intrfuncs); 414 415 sc->sc_phsc.sc_type = PCIHOST_ECAM; 416 sc->sc_phsc.sc_pci_flags |= PCI_FLAGS_MSI_OKAY; 417 sc->sc_phsc.sc_pci_flags |= PCI_FLAGS_MSIX_OKAY; 418 pcihost_init(&sc->sc_phsc.sc_pc, sc); 419 sc->sc_phsc.sc_pc.pc_bus_maxdevs = rkpcie_bus_maxdevs; 420 sc->sc_phsc.sc_pc.pc_make_tag = rkpcie_make_tag; 421 sc->sc_phsc.sc_pc.pc_decompose_tag = rkpcie_decompose_tag; 422 sc->sc_phsc.sc_pc.pc_conf_read = rkpcie_conf_read; 423 sc->sc_phsc.sc_pc.pc_conf_write = rkpcie_conf_write; 424 sc->sc_phsc.sc_pc.pc_conf_hook = rkpcie_conf_hook; 425 426 if (bus_scan_delay_ms > delayed_ms) { 427 uint32_t ms = bus_scan_delay_ms - delayed_ms; 428 429 aprint_verbose_dev(phsc->sc_dev, 430 "waiting %u extra ms for reset (already waited %u)\n", 431 ms, delayed_ms); 432 delay(ms * 1000); 433 } 434 435 mutex_init(&sc->sc_conf_lock, MUTEX_DEFAULT, IPL_HIGH); 436 pcihost_init2(&sc->sc_phsc); 437 } 438 439 static void 440 rkpcie_atr_init(struct rkpcie_softc *sc) 441 { 442 const u_int *ranges; 443 bus_addr_t aaddr; 444 bus_addr_t addr; 445 bus_size_t size, resid, offset; 446 uint32_t type; 447 int region, i, ranges_len; 448 449 /* Use region 0 to map PCI configuration space */ 450 HWRITE4(sc, PCIE_ATR_OB_ADDR0(0), 20 - 1); 451 HWRITE4(sc, PCIE_ATR_OB_ADDR1(0), 0); 452 HWRITE4(sc, PCIE_ATR_OB_DESC0(0), PCIE_ATR_HDR_CFG_TYPE0 | PCIE_ATR_HDR_RID); 453 HWRITE4(sc, PCIE_ATR_OB_DESC1(0), 0); 454 455 ranges = fdtbus_get_prop(sc->sc_phsc.sc_phandle, "ranges", &ranges_len); 456 if (ranges == NULL) 457 goto fail; 458 const int ranges_cells = ranges_len / 4; 459 460 for (i = 0; i < ranges_cells; i += 7) { 461 /* Handle IO and MMIO. */ 462 switch (be32toh(ranges[i]) & 0x03000000) { 463 case 0x01000000: 464 type = PCIE_ATR_HDR_IO; 465 break; 466 case 0x02000000: 467 case 0x03000000: 468 type = PCIE_ATR_HDR_MEM; 469 break; 470 default: 471 continue; 472 } 473 474 addr = ((uint64_t)be32toh(ranges[i + 1]) << 32) + be32toh(ranges[i + 2]); 475 aaddr = ((uint64_t)be32toh(ranges[i + 3]) << 32) + be32toh(ranges[i + 4]); 476 size = be32toh(ranges[i + 6]); 477 478 /* Only support mappings aligned on a region boundary. */ 479 if (addr & (PCIE_ATR_OB_REGION_SIZE - 1)) 480 goto fail; 481 if (aaddr & (PCIE_ATR_OB_REGION_SIZE - 1)) 482 goto fail; 483 if (size & (PCIE_ATR_OB_REGION_SIZE - 1)) 484 goto fail; 485 486 /* Mappings should lie in AXI region. */ 487 if (aaddr < sc->sc_axi_addr) 488 goto fail; 489 if (aaddr + size > sc->sc_axi_addr + 64*1024*1024) 490 goto fail; 491 492 offset = addr - sc->sc_axi_addr - PCIE_ATR_OB_REGION0_SIZE; 493 region = 1 + (offset / PCIE_ATR_OB_REGION_SIZE); 494 resid = size; 495 while (resid > 0) { 496 HWRITE4(sc, PCIE_ATR_OB_ADDR0(region), 32 - 1); 497 HWRITE4(sc, PCIE_ATR_OB_ADDR1(region), 0); 498 HWRITE4(sc, PCIE_ATR_OB_DESC0(region), type | PCIE_ATR_HDR_RID); 499 HWRITE4(sc, PCIE_ATR_OB_DESC1(region), 0); 500 501 addr += PCIE_ATR_OB_REGION_SIZE; 502 resid -= PCIE_ATR_OB_REGION_SIZE; 503 region++; 504 } 505 } 506 507 /* Passthrought inbound translations unmodified. */ 508 HWRITE4(sc, PCIE_ATR_IB_ADDR0(2), 32 - 1); 509 HWRITE4(sc, PCIE_ATR_IB_ADDR1(2), 0); 510 511 return; 512 513 fail: 514 device_printf(sc->sc_phsc.sc_dev, "can't map ranges\n"); 515 } 516 517 int 518 rkpcie_bus_maxdevs(void *v, int bus) 519 { 520 struct rkpcie_softc *rksc = v; 521 struct pcihost_softc *sc = &rksc->sc_phsc; 522 523 if (bus == sc->sc_bus_min || bus == sc->sc_bus_min + 1) 524 return 1; 525 return 32; 526 } 527 528 pcitag_t 529 rkpcie_make_tag(void *v, int bus, int device, int function) 530 { 531 /* Return ECAM address. */ 532 return ((bus << 20) | (device << 15) | (function << 12)); 533 } 534 535 void 536 rkpcie_decompose_tag(void *v, pcitag_t tag, int *bp, int *dp, int *fp) 537 { 538 if (bp != NULL) 539 *bp = (tag >> 20) & 0xff; 540 if (dp != NULL) 541 *dp = (tag >> 15) & 0x1f; 542 if (fp != NULL) 543 *fp = (tag >> 12) & 0x7; 544 } 545 546 /* Only one device on root port and the first subordinate port. */ 547 static bool 548 rkpcie_conf_ok(int bus, int dev, int fn, int offset, struct rkpcie_softc *sc) 549 { 550 int bus_min = sc->sc_phsc.sc_bus_min; 551 552 if ((unsigned int)offset >= (1<<12)) 553 return false; 554 /* first two buses use type 0 cfg which doesn't use bus/device numbers */ 555 if (dev != 0 && (bus == bus_min || bus == bus_min + 1)) 556 return false; 557 return true; 558 } 559 560 pcireg_t 561 rkpcie_conf_read(void *v, pcitag_t tag, int offset) 562 { 563 struct rkpcie_softc *sc = v; 564 int bus_min = sc->sc_phsc.sc_bus_min; 565 int bus, dev, fn; 566 u_int reg; 567 int32_t val; 568 569 KASSERT(offset >= 0); 570 KASSERT(offset < PCI_EXTCONF_SIZE); 571 572 rkpcie_decompose_tag(sc, tag, &bus, &dev, &fn); 573 if (!rkpcie_conf_ok(bus, dev, fn, offset, sc)) 574 return 0xffffffff; 575 reg = (dev << 15) | (fn << 12) | offset; 576 577 if (bus == bus_min) 578 val = HREAD4(sc, PCIE_RC_NORMAL_BASE + reg); 579 else { 580 mutex_spin_enter(&sc->sc_conf_lock); 581 HWRITE4(sc, PCIE_ATR_OB_ADDR0(0), 582 (bus << 20) | (20 - 1)); 583 HWRITE4(sc, PCIE_ATR_OB_DESC0(0), 584 PCIE_ATR_HDR_RID | ((bus == bus_min + 1) 585 ? PCIE_ATR_HDR_CFG_TYPE0 : PCIE_ATR_HDR_CFG_TYPE1)); 586 bus_space_barrier(sc->sc_iot, sc->sc_ioh, 0, sc->sc_apb_size, 587 BUS_SPACE_BARRIER_READ); 588 if (AXIPEEK4(sc, reg, &val) != 0) 589 val = 0xffffffff; 590 bus_space_barrier(sc->sc_iot, sc->sc_axi_ioh, 591 0, sc->sc_axi_size, 592 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 593 mutex_spin_exit(&sc->sc_conf_lock); 594 } 595 return val; 596 } 597 598 void 599 rkpcie_conf_write(void *v, pcitag_t tag, int offset, pcireg_t data) 600 { 601 struct rkpcie_softc *sc = v; 602 int bus_min = sc->sc_phsc.sc_bus_min; 603 int bus, dev, fn; 604 u_int reg; 605 606 KASSERT(offset >= 0); 607 KASSERT(offset < PCI_EXTCONF_SIZE); 608 609 rkpcie_decompose_tag(sc, tag, &bus, &dev, &fn); 610 if (!rkpcie_conf_ok(bus, dev, fn, offset, sc)) 611 return; 612 reg = (dev << 15) | (fn << 12) | offset; 613 614 if (bus == bus_min) 615 HWRITE4(sc, PCIE_RC_NORMAL_BASE + reg, data); 616 else { 617 mutex_spin_enter(&sc->sc_conf_lock); 618 HWRITE4(sc, PCIE_ATR_OB_ADDR0(0), 619 (bus << 20) | (20 - 1)); 620 HWRITE4(sc, PCIE_ATR_OB_DESC0(0), 621 PCIE_ATR_HDR_RID | ((bus == bus_min + 1) 622 ? PCIE_ATR_HDR_CFG_TYPE0 : PCIE_ATR_HDR_CFG_TYPE1)); 623 bus_space_barrier(sc->sc_iot, sc->sc_ioh, 0, sc->sc_apb_size, 624 BUS_SPACE_BARRIER_WRITE); 625 AXIPOKE4(sc, reg, data); 626 bus_space_barrier(sc->sc_iot, sc->sc_axi_ioh, 627 0, sc->sc_axi_size, 628 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 629 mutex_spin_exit(&sc->sc_conf_lock); 630 } 631 } 632 633 static int 634 rkpcie_conf_hook(void *v, int b, int d, int f, pcireg_t id) 635 { 636 return (PCI_CONF_DEFAULT & ~PCI_CONF_ENABLE_BM) | PCI_CONF_MAP_ROM; 637 } 638 639 /* INTx interrupt controller */ 640 static void * 641 rkpcie_intx_establish(device_t dev, u_int *specifier, int ipl, int flags, 642 int (*func)(void *), void *arg, const char *xname) 643 { 644 struct rkpcie_softc *sc = device_private(dev); 645 void *cookie; 646 647 #if notyet 648 const u_int pin = be32toh(specifier[0]); 649 #endif 650 651 /* Unmask legacy interrupts. */ 652 HWRITE4(sc, PCIE_CLIENT_INT_MASK, 653 PCIM_INTx_ENAB(0) | PCIM_INTx_ENAB(1) | 654 PCIM_INTx_ENAB(2) | PCIM_INTx_ENAB(3)); 655 656 cookie = fdtbus_intr_establish_byname(sc->sc_phsc.sc_phandle, 657 "legacy", ipl, flags, func, arg, xname); 658 659 return cookie; 660 } 661 662 static void 663 rkpcie_intx_disestablish(device_t dev, void *ih) 664 { 665 struct rkpcie_softc *sc = device_private(dev); 666 device_printf(dev, "%s\n", __func__); 667 fdtbus_intr_disestablish(sc->sc_phsc.sc_phandle, ih); 668 } 669 670 static bool 671 rkpcie_intx_intrstr(device_t dev, u_int *specifier, char *buf, size_t buflen) 672 { 673 struct rkpcie_softc *sc = device_private(dev); 674 675 fdtbus_intr_str(sc->sc_phsc.sc_phandle, 1, buf, buflen); 676 677 return true; 678 } 679 680 static struct fdtbus_interrupt_controller_func rkpcie_intrfuncs = { 681 .establish = rkpcie_intx_establish, 682 .disestablish = rkpcie_intx_disestablish, 683 .intrstr = rkpcie_intx_intrstr, 684 }; 685
Indexes created Thu Oct 02 10:09:58 GMT 2025