rk3399_pcie.c revision 1.3
1 /* $NetBSD: rk3399_pcie.c,v 1.3 2019/06/12 22:44:53 jmcneill Exp $ */ 2 /* 3 * Copyright (c) 2018 Mark Kettenis <kettenis (at) openbsd.org> 4 * 5 * Permission to use, copy, modify, and distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 */ 17 18 #include <sys/cdefs.h> 19 20 __KERNEL_RCSID(1, "$NetBSD: rk3399_pcie.c,v 1.3 2019/06/12 22:44:53 jmcneill Exp $"); 21 22 #include <sys/param.h> 23 #include <sys/systm.h> 24 #include <sys/bitops.h> 25 #include <sys/device.h> 26 #include <sys/extent.h> 27 #include <sys/kmem.h> 28 29 #include <machine/intr.h> 30 #include <sys/bus.h> 31 #include <dev/fdt/fdtvar.h> 32 #include <dev/fdt/syscon.h> 33 #include <arm/cpufunc.h> 34 35 #include <dev/pci/pcidevs.h> 36 #include <dev/pci/pcireg.h> 37 #include <dev/pci/pcivar.h> 38 #include <dev/pci/pciconf.h> 39 40 #include <arm/fdt/pcihost_fdtvar.h> 41 #include <sys/gpio.h> 42 43 #define SETREG(m, v) ((m)<<16|__SHIFTIN((v), (m))) 44 #define GETREG(m, v) (__SHIFTOUT((v), (m))) 45 46 /* APB region */ 47 #define PCIE_CLIENT_BASE 0x000000 48 #define PCIE_CLIENT_BASIC_STRAP_CONF 0x0000 49 #define PCBSC_PCIE_GEN_SEL __BIT(7) 50 #define PCBSC_PGS_GEN1 SETREG(PCBSC_PCIE_GEN_SEL, 0) 51 #define PCBSC_PGS_GEN2 SETREG(PCBSC_PCIE_GEN_SEL, 1) 52 #define PCBSC_MODE_SELECT __BIT(6) 53 #define PCBSC_MS_ENDPOINT SETREG(PCBSC_MODE_SELECT, 0) 54 #define PCBSC_MS_ROOTPORT SETREG(PCBSC_MODE_SELECT, 1) 55 #define PCBSC_LANE_COUNT __BITS(5,4) 56 #define PCBSC_LC(x) SETREG(PCBSC_LANE_COUNT, ilog2(x)) /* valid for x1,2,4 */ 57 #define PCBSC_ARI_EN SETREG(__BIT(3), 1) /* Alternate Routing ID Enable */ 58 #define PCBSC_SR_IOV_EN SETREG(__BIT(2), 1) 59 #define PCBSC_LINK_TRAIN_EN SETREG(__BIT(1), 1) 60 #define PCBSC_CONF_EN SETREG(__BIT(0), 1) /* Config enable */ 61 #define PCIE_CLIENT_DEBUG_OUT_0 0x003c 62 #define PCIE_CLIENT_DEBUG_OUT_1 0x0040 63 #define PCIE_CLIENT_BASIC_STATUS0 0x0044 64 #define PCIE_CLIENT_BASIC_STATUS1 0x0048 65 #define PCBS1_LINK_ST(x) (u_int)__SHIFTOUT((x), __BITS(21,20)) 66 #define PCBS1_LS_NO_RECV 0 /* no receivers */ 67 #define PCBS1_LS_TRAINING 1 /* link training */ 68 #define PCBS1_LS_DL_INIT 2 /* link up, DL init progressing */ 69 #define PCBS1_LS_DL_DONE 3 /* link up, DL init complete */ 70 #define PCIE_CLIENT_INT_MASK 0x004c 71 #define PCIM_INTx_MASK(x) SETREG(__BIT((x)+5), 1) 72 #define PCIM_INTx_ENAB(x) SETREG(__BIT((x)+5), 0) 73 74 #define PCIE_CORE_BASE 0x800000 75 #define PCIE_RC_NORMAL_BASE (PCIE_CORE_BASE + 0x00000) 76 77 #define PCIE_LM_BASE 0x900000 78 #define PCIE_LM_CORE_CTRL (PCIE_LM_BASE + 0x00) 79 #define PCIE_CORE_PL_CONF_SPEED_5G 0x00000008 80 #define PCIE_CORE_PL_CONF_SPEED_MASK 0x00000018 81 #define PCIE_CORE_PL_CONF_LANE_MASK 0x00000006 82 #define PCIE_CORE_PL_CONF_LANE_SHIFT 1 83 #define PCIE_LM_PLC1 (PCIE_LM_BASE + 0x04) 84 #define PCIE_LM_PLC1_FTS_MASK __BITS(23, 8) 85 #define PCIE_LM_VENDOR_ID (PCIE_LM_BASE + 0x44) 86 #define PCIE_LM_LINKWIDTH (PCIE_LM_BASE + 0x50) 87 #define PCIE_LM_LANEMAP (PCIE_LM_BASE + 0x200) 88 #define PCIE_LM_DEBUG_MUX_CONTROL (PCIE_LM_BASE + 0x208) 89 #define PCIE_LM_RCBAR (PCIE_LM_BASE + 0x300) 90 #define PCIE_LM_RCBARPME __BIT(17) 91 #define PCIE_LM_RCBARPMS __BIT(18) 92 #define PCIE_LM_RCBARPIE __BIT(19) 93 #define PCIE_LM_RCBARPIS __BIT(20) 94 95 #define PCIE_RC_BASE 0xa00000 96 #define PCIE_RC_CONFIG_DCSR (PCIE_RC_BASE + 0x0c0 + PCIE_DCSR) 97 #define PCIE_RC_PCIE_LCAP (PCIE_RC_BASE + 0x0c0 + PCIE_LCAP) 98 #define PCIE_RC_CONFIG_LCSR (PCIE_RC_BASE + 0x0c0 + PCIE_LCSR) 99 #define PCIE_RC_CONFIG_THP_CAP (PCIE_RC_BASE + 0x274) 100 #define PCIE_RC_CONFIG_THP_CAP_NEXT_MASK __BITS(31, 20) 101 102 103 #define PCIE_ATR_BASE 0xc00000 104 #define PCIE_ATR_OB_ADDR0(i) (PCIE_ATR_BASE + 0x000 + (i) * 0x20) 105 #define PCIE_ATR_OB_ADDR1(i) (PCIE_ATR_BASE + 0x004 + (i) * 0x20) 106 #define PCIE_ATR_OB_DESC0(i) (PCIE_ATR_BASE + 0x008 + (i) * 0x20) 107 #define PCIE_ATR_OB_DESC1(i) (PCIE_ATR_BASE + 0x00c + (i) * 0x20) 108 #define PCIE_ATR_IB_ADDR0(i) (PCIE_ATR_BASE + 0x800 + (i) * 0x8) 109 #define PCIE_ATR_IB_ADDR1(i) (PCIE_ATR_BASE + 0x804 + (i) * 0x8) 110 #define PCIE_ATR_HDR_MEM 0x2 111 #define PCIE_ATR_HDR_IO 0x6 112 #define PCIE_ATR_HDR_CFG_TYPE0 0xa 113 #define PCIE_ATR_HDR_CFG_TYPE1 0xb 114 #define PCIE_ATR_HDR_RID __BIT(23) 115 116 /* AXI region */ 117 #define PCIE_ATR_OB_REGION0_SIZE (32 * 1024 * 1024) 118 #define PCIE_ATR_OB_REGION_SIZE (1 * 1024 * 1024) 119 120 #define HREAD4(sc, reg) \ 121 (bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg))) 122 #define HWRITE4(sc, reg, val) \ 123 bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val)) 124 125 struct rkpcie_softc { 126 struct pcihost_softc sc_phsc; 127 bus_space_tag_t sc_iot; 128 bus_space_handle_t sc_ioh; 129 bus_space_handle_t sc_axi_ioh; 130 bus_addr_t sc_axi_addr; 131 bus_addr_t sc_apb_addr; 132 bus_size_t sc_axi_size; 133 bus_size_t sc_apb_size; 134 }; 135 136 static int rkpcie_match(device_t, cfdata_t, void *); 137 static void rkpcie_attach(device_t, device_t, void *); 138 139 CFATTACH_DECL_NEW(rkpcie, sizeof(struct rkpcie_softc), 140 rkpcie_match, rkpcie_attach, NULL, NULL); 141 142 static int 143 rkpcie_match(device_t parent, cfdata_t cf, void *aux) 144 { 145 const char * const compatible[] = { 146 "rockchip,rk3399-pcie", 147 NULL 148 }; 149 struct fdt_attach_args *faa = aux; 150 151 return of_match_compatible(faa->faa_phandle, compatible); 152 } 153 154 static void rkpcie_atr_init(struct rkpcie_softc *); 155 156 static int rkpcie_bus_maxdevs(void *, int); 157 static pcitag_t rkpcie_make_tag(void *, int, int, int); 158 static void rkpcie_decompose_tag(void *, pcitag_t, int *, int *, int *); 159 static pcireg_t rkpcie_conf_read(void *, pcitag_t, int); 160 static void rkpcie_conf_write(void *, pcitag_t, int, pcireg_t); 161 static int rkpcie_conf_hook(void *, int, int, int, pcireg_t); 162 163 static struct fdtbus_interrupt_controller_func rkpcie_intrfuncs; 164 165 static inline void 166 clock_enable_all(int phandle) 167 { 168 for (u_int i = 0; i < 4; i++) { 169 struct clk * clk = fdtbus_clock_get_index(phandle, i); 170 if (clk == NULL) 171 continue; 172 if (clk_enable(clk) != 0) 173 continue; 174 } 175 } 176 177 static inline void 178 clock_enable(int phandle, const char *name) 179 { 180 struct clk * clk = fdtbus_clock_get(phandle, name); 181 if (clk == NULL) 182 return; 183 if (clk_enable(clk) != 0) 184 return; 185 } 186 187 static void 188 reset_assert(int phandle, const char *name) 189 { 190 struct fdtbus_reset *rst; 191 192 rst = fdtbus_reset_get(phandle, name); 193 fdtbus_reset_assert(rst); 194 fdtbus_reset_put(rst); 195 } 196 197 static void 198 reset_deassert(int phandle, const char *name) 199 { 200 struct fdtbus_reset *rst; 201 202 rst = fdtbus_reset_get(phandle, name); 203 fdtbus_reset_deassert(rst); 204 fdtbus_reset_put(rst); 205 } 206 207 static void 208 rkpcie_attach(device_t parent, device_t self, void *aux) 209 { 210 struct rkpcie_softc *sc = device_private(self); 211 struct pcihost_softc * const phsc = &sc->sc_phsc; 212 struct fdt_attach_args *faa = aux; 213 //struct pcibus_attach_args pba; 214 struct fdtbus_gpio_pin *ep_gpio; 215 const u_int *bus_range; 216 int len; 217 uint32_t status; 218 bool retry = false; 219 int timo; 220 221 phsc->sc_dev = self; 222 phsc->sc_bst = faa->faa_bst; 223 phsc->sc_dmat = faa->faa_dmat; 224 sc->sc_iot = phsc->sc_bst; 225 phsc->sc_phandle = faa->faa_phandle; 226 const int phandle = phsc->sc_phandle; 227 228 if (fdtbus_get_reg_byname(faa->faa_phandle, "axi-base", &sc->sc_axi_addr, &sc->sc_axi_size) != 0) { 229 aprint_error(": couldn't get axi registers\n"); 230 return; 231 } 232 if (fdtbus_get_reg_byname(faa->faa_phandle, "apb-base", &sc->sc_apb_addr, &sc->sc_apb_size) != 0) { 233 aprint_error(": couldn't get apb registers\n"); 234 sc->sc_axi_size = 0; 235 return; 236 } 237 238 if (bus_space_map(sc->sc_iot, sc->sc_apb_addr, sc->sc_apb_size, 0, &sc->sc_ioh) != 0 || 239 bus_space_map(sc->sc_iot, sc->sc_axi_addr, sc->sc_axi_size, 0, &sc->sc_axi_ioh) != 0) { 240 printf(": can't map registers\n"); 241 sc->sc_axi_size = 0; 242 sc->sc_apb_size = 0; 243 return; 244 } 245 246 aprint_naive("\n"); 247 aprint_normal(": RK3399 PCIe\n"); 248 249 struct fdtbus_regulator *regulator; 250 regulator = fdtbus_regulator_acquire(phandle, "vpcie3v3-supply"); 251 fdtbus_regulator_enable(regulator); 252 fdtbus_regulator_release(regulator); 253 254 fdtbus_clock_assign(phandle); 255 clock_enable_all(phandle); 256 257 ep_gpio = fdtbus_gpio_acquire(phandle, "ep-gpios", GPIO_PIN_OUTPUT); 258 //retry = true; 259 again: 260 fdtbus_gpio_write(ep_gpio, 0); 261 262 reset_assert(phandle, "aclk"); 263 reset_assert(phandle, "pclk"); 264 reset_assert(phandle, "pm"); 265 266 //device_printf(self, "%s phy0\n", __func__); 267 struct fdtbus_phy *phy[4]; 268 memset(phy, 0, sizeof(phy)); 269 phy[0] = fdtbus_phy_get(phandle, "pcie-phy-0"); 270 //device_printf(self, "%s phy1 %p\n", __func__, phy[0]); 271 if (phy[0] == NULL) { 272 phy[0] = fdtbus_phy_get(phandle, "pcie-phy"); 273 device_printf(self, "%s phy2 %p\n", __func__, phy); 274 } else { 275 /* XXX */ 276 phy[1] = fdtbus_phy_get(phandle, "pcie-phy-1"); 277 phy[2] = fdtbus_phy_get(phandle, "pcie-phy-2"); 278 phy[3] = fdtbus_phy_get(phandle, "pcie-phy-3"); 279 } 280 281 reset_assert(phandle, "core"); 282 reset_assert(phandle, "mgmt"); 283 reset_assert(phandle, "mgmt-sticky"); 284 reset_assert(phandle, "pipe"); 285 286 delay(10); 287 288 reset_deassert(phandle, "pm"); 289 reset_deassert(phandle, "aclk"); 290 reset_deassert(phandle, "pclk"); 291 292 if (retry) 293 HWRITE4(sc, PCIE_CLIENT_BASIC_STRAP_CONF, PCBSC_PGS_GEN1); 294 else 295 HWRITE4(sc, PCIE_CLIENT_BASIC_STRAP_CONF, PCBSC_PGS_GEN2); 296 297 /* Switch into Root Complex mode. */ 298 HWRITE4(sc, PCIE_CLIENT_BASIC_STRAP_CONF, 299 PCBSC_MS_ROOTPORT | PCBSC_CONF_EN | PCBSC_LC(4)); 300 //printf("%s PCBSC %x\n", __func__, HREAD4(sc, PCIE_CLIENT_BASIC_STRAP_CONF)); 301 302 if (phy[3] && fdtbus_phy_enable(phy[3], true) != 0) { 303 aprint_error(": couldn't enable phy3\n"); 304 } 305 if (phy[2] && fdtbus_phy_enable(phy[2], true) != 0) { 306 aprint_error(": couldn't enable phy2\n"); 307 } 308 if (phy[1] && fdtbus_phy_enable(phy[1], true) != 0) { 309 aprint_error(": couldn't enable phy1\n"); 310 } 311 if (phy[0] && fdtbus_phy_enable(phy[0], true) != 0) { 312 aprint_error(": couldn't enable phy0\n"); 313 } 314 315 reset_deassert(phandle, "mgmt-sticky"); 316 reset_deassert(phandle, "core"); 317 reset_deassert(phandle, "mgmt"); 318 reset_deassert(phandle, "pipe"); 319 320 /* FTS count */ 321 HWRITE4(sc, PCIE_LM_PLC1, HREAD4(sc, PCIE_LM_PLC1) | PCIE_LM_PLC1_FTS_MASK); 322 323 /* XXX Advertise power limits? */ 324 325 /* common clock */ 326 HWRITE4(sc, PCIE_RC_CONFIG_LCSR, HREAD4(sc, PCIE_RC_CONFIG_LCSR) | PCIE_LCSR_COMCLKCFG); 327 /* 128 RCB */ 328 HWRITE4(sc, PCIE_RC_CONFIG_LCSR, HREAD4(sc, PCIE_RC_CONFIG_LCSR) | PCIE_LCSR_RCB); 329 330 /* Start link training. */ 331 HWRITE4(sc, PCIE_CLIENT_BASIC_STRAP_CONF, PCBSC_LINK_TRAIN_EN); 332 333 fdtbus_gpio_write(ep_gpio, 1); 334 335 for (timo = 500; timo > 0; timo--) { 336 status = HREAD4(sc, PCIE_CLIENT_BASIC_STATUS1); 337 if (PCBS1_LINK_ST(status) == PCBS1_LS_DL_DONE) 338 break; 339 delay(1000); 340 } 341 if (timo == 0) { 342 device_printf(self, "link training timeout (link_st %u)\n", 343 PCBS1_LINK_ST(status)); 344 if (!retry) { 345 retry = true; 346 goto again; 347 } 348 return; 349 } 350 351 if (!retry) { 352 HWRITE4(sc, PCIE_RC_CONFIG_LCSR, HREAD4(sc, PCIE_RC_CONFIG_LCSR) | PCIE_LCSR_RETRAIN); 353 for (timo = 500; timo > 0; timo--) { 354 status = HREAD4(sc, PCIE_LM_CORE_CTRL); 355 if ((status & PCIE_CORE_PL_CONF_SPEED_MASK) == PCIE_CORE_PL_CONF_SPEED_5G) 356 break; 357 delay(1000); 358 } 359 if (timo == 0) { 360 device_printf(self, "Gen2 link training timeout\n"); 361 retry = true; 362 goto again; 363 } 364 } 365 366 #if 0 367 printf("%s CBS0 %x\n", __func__, HREAD4(sc, PCIE_CLIENT_BASIC_STATUS1)); 368 HWRITE4(sc, PCIE_LM_DEBUG_MUX_CONTROL, (HREAD4(sc, PCIE_LM_DEBUG_MUX_CONTROL) & ~0xf) | 0); 369 printf("%s CDO0 %x\n", __func__, HREAD4(sc, PCIE_CLIENT_DEBUG_OUT_0)); 370 HWRITE4(sc, PCIE_LM_DEBUG_MUX_CONTROL, (HREAD4(sc, PCIE_LM_DEBUG_MUX_CONTROL) & ~0xf) | 1); 371 printf("%s CDO0 %x\n", __func__, HREAD4(sc, PCIE_CLIENT_DEBUG_OUT_0)); 372 HWRITE4(sc, PCIE_LM_DEBUG_MUX_CONTROL, (HREAD4(sc, PCIE_LM_DEBUG_MUX_CONTROL) & ~0xf) | 4); 373 printf("%s CDO0 %x\n", __func__, HREAD4(sc, PCIE_CLIENT_DEBUG_OUT_0)); 374 HWRITE4(sc, PCIE_LM_DEBUG_MUX_CONTROL, (HREAD4(sc, PCIE_LM_DEBUG_MUX_CONTROL) & ~0xf) | 5); 375 printf("%s CDO0 %x\n", __func__, HREAD4(sc, PCIE_CLIENT_DEBUG_OUT_0)); 376 printf("%s LINKWIDTH %x\n", __func__, HREAD4(sc, PCIE_LM_LINKWIDTH)); 377 //HWRITE4(sc, PCIE_LM_LINKWIDTH, 0x1000f); 378 //printf("%s LINKWIDTH %x\n", __func__, HREAD4(sc, PCIE_LM_LINKWIDTH)); 379 printf("%s LANEMAP %x\n", __func__, HREAD4(sc, PCIE_LM_LANEMAP)); 380 #endif 381 382 fdtbus_gpio_release(ep_gpio); 383 384 HWRITE4(sc, PCIE_RC_BASE + PCI_CLASS_REG, 385 PCI_CLASS_BRIDGE << PCI_CLASS_SHIFT | 386 PCI_SUBCLASS_BRIDGE_PCI << PCI_SUBCLASS_SHIFT); 387 388 /* Initialize Root Complex registers. */ 389 HWRITE4(sc, PCIE_LM_VENDOR_ID, PCI_VENDOR_ROCKCHIP); 390 HWRITE4(sc, PCIE_RC_BASE + PCI_CLASS_REG, 391 PCI_CLASS_BRIDGE << PCI_CLASS_SHIFT | 392 PCI_SUBCLASS_BRIDGE_PCI << PCI_SUBCLASS_SHIFT); 393 HWRITE4(sc, PCIE_LM_RCBAR, PCIE_LM_RCBARPIE | PCIE_LM_RCBARPIS | PCIE_LM_RCBARPME | PCIE_LM_RCBARPMS); 394 395 /* remove L1 substate cap */ 396 status = HREAD4(sc, PCIE_RC_CONFIG_THP_CAP); 397 status &= ~PCIE_RC_CONFIG_THP_CAP_NEXT_MASK; 398 HWRITE4(sc, PCIE_RC_CONFIG_THP_CAP, status); 399 400 if (OF_getproplen(phandle, "aspm-no-l0s") == 0) { 401 status = HREAD4(sc, PCIE_RC_PCIE_LCAP); 402 status &= ~__SHIFTIN(1, PCIE_LCAP_ASPM); 403 HWRITE4(sc, PCIE_RC_PCIE_LCAP, status); 404 } 405 406 status = HREAD4(sc, PCIE_RC_CONFIG_DCSR); 407 status &= ~PCIE_DCSR_MAX_PAYLOAD; 408 status |= __SHIFTIN(1, PCIE_DCSR_MAX_PAYLOAD); 409 HWRITE4(sc, PCIE_RC_CONFIG_DCSR, status); 410 411 /* Default bus ranges */ 412 sc->sc_phsc.sc_bus_min = 0; 413 sc->sc_phsc.sc_bus_max = 31; 414 415 /* Override bus range from DT */ 416 bus_range = fdtbus_get_prop(phandle, "bus-range", &len); 417 if (len == 8) { 418 sc->sc_phsc.sc_bus_min = be32dec(&bus_range[0]); 419 sc->sc_phsc.sc_bus_max = be32dec(&bus_range[1]); 420 } 421 422 if (sc->sc_phsc.sc_bus_min != 0) { 423 aprint_error_dev(self, "bus-range doesn't start at 0\n"); 424 return; 425 } 426 427 /* Configure Address Translation. */ 428 rkpcie_atr_init(sc); 429 430 fdtbus_register_interrupt_controller(self, OF_child(sc->sc_phsc.sc_phandle), 431 &rkpcie_intrfuncs); 432 433 sc->sc_phsc.sc_type = PCIHOST_ECAM; 434 #if notyet 435 sc->sc_phsc.sc_pci_flags |= PCI_FLAGS_MSI_OKAY; 436 #endif 437 pcihost_init(&sc->sc_phsc.sc_pc, sc); 438 sc->sc_phsc.sc_pc.pc_bus_maxdevs = rkpcie_bus_maxdevs; 439 sc->sc_phsc.sc_pc.pc_make_tag = rkpcie_make_tag; 440 sc->sc_phsc.sc_pc.pc_decompose_tag = rkpcie_decompose_tag; 441 sc->sc_phsc.sc_pc.pc_conf_read = rkpcie_conf_read; 442 sc->sc_phsc.sc_pc.pc_conf_write = rkpcie_conf_write; 443 sc->sc_phsc.sc_pc.pc_conf_hook = rkpcie_conf_hook; 444 pcihost_init2(&sc->sc_phsc); 445 } 446 447 static void 448 rkpcie_atr_init(struct rkpcie_softc *sc) 449 { 450 const u_int *ranges; 451 bus_addr_t aaddr; 452 bus_addr_t addr; 453 bus_size_t size, offset; 454 uint32_t type; 455 int region, i, ranges_len; 456 457 /* Use region 0 to map PCI configuration space */ 458 HWRITE4(sc, PCIE_ATR_OB_ADDR0(0), 25 - 1); 459 HWRITE4(sc, PCIE_ATR_OB_ADDR1(0), 0); 460 HWRITE4(sc, PCIE_ATR_OB_DESC0(0), 461 PCIE_ATR_HDR_CFG_TYPE0 | PCIE_ATR_HDR_RID); 462 HWRITE4(sc, PCIE_ATR_OB_DESC1(0), 0); 463 464 ranges = fdtbus_get_prop(sc->sc_phsc.sc_phandle, "ranges", &ranges_len); 465 if (ranges == NULL) 466 goto fail; 467 const int ranges_cells = ranges_len / 4; 468 469 for (i = 0; i < ranges_cells; i += 7) { 470 /* Handle IO and MMIO. */ 471 switch (be32toh(ranges[i]) & 0x03000000) { 472 case 0x01000000: 473 type = PCIE_ATR_HDR_IO; 474 break; 475 case 0x02000000: 476 case 0x03000000: 477 type = PCIE_ATR_HDR_MEM; 478 break; 479 default: 480 continue; 481 } 482 483 addr = ((uint64_t)be32toh(ranges[i + 1]) << 32) + be32toh(ranges[i + 2]); 484 aaddr = ((uint64_t)be32toh(ranges[i + 3]) << 32) + be32toh(ranges[i + 4]); 485 size = (uint64_t)be32toh(ranges[i + 5]) << 32 | be32toh(ranges[i + 6]); 486 487 /* Only support mappings aligned on a region boundary. */ 488 if (addr & (PCIE_ATR_OB_REGION_SIZE - 1)) 489 goto fail; 490 if (aaddr & (PCIE_ATR_OB_REGION_SIZE - 1)) 491 goto fail; 492 if (size & (PCIE_ATR_OB_REGION_SIZE - 1)) 493 goto fail; 494 495 /* Mappings should lie in AXI region. */ 496 if (aaddr < sc->sc_axi_addr) 497 goto fail; 498 if (aaddr + size > sc->sc_axi_addr + 64*1024*1024) 499 goto fail; 500 501 offset = addr - sc->sc_axi_addr - PCIE_ATR_OB_REGION0_SIZE; 502 region = 1 + (offset / PCIE_ATR_OB_REGION_SIZE); 503 while (size > 0) { 504 HWRITE4(sc, PCIE_ATR_OB_ADDR0(region), 32 - 1); 505 HWRITE4(sc, PCIE_ATR_OB_ADDR1(region), 0); 506 HWRITE4(sc, PCIE_ATR_OB_DESC0(region), 507 type | PCIE_ATR_HDR_RID); 508 HWRITE4(sc, PCIE_ATR_OB_DESC1(region), 0); 509 510 addr += PCIE_ATR_OB_REGION_SIZE; 511 size -= PCIE_ATR_OB_REGION_SIZE; 512 region++; 513 } 514 } 515 516 /* Passthrought inbound translations unmodified. */ 517 HWRITE4(sc, PCIE_ATR_IB_ADDR0(2), 32 - 1); 518 HWRITE4(sc, PCIE_ATR_IB_ADDR1(2), 0); 519 520 return; 521 522 fail: 523 device_printf(sc->sc_phsc.sc_dev, "can't map ranges\n"); 524 } 525 526 int 527 rkpcie_bus_maxdevs(void *v, int bus) 528 { 529 struct rkpcie_softc *rksc = v; 530 struct pcihost_softc *sc = &rksc->sc_phsc; 531 532 if (bus == sc->sc_bus_min || bus == sc->sc_bus_min + 1) 533 return 1; 534 return 32; 535 } 536 537 pcitag_t 538 rkpcie_make_tag(void *v, int bus, int device, int function) 539 { 540 /* Return ECAM address. */ 541 return ((bus << 20) | (device << 15) | (function << 12)); 542 } 543 544 void 545 rkpcie_decompose_tag(void *v, pcitag_t tag, int *bp, int *dp, int *fp) 546 { 547 if (bp != NULL) 548 *bp = (tag >> 20) & 0xff; 549 if (dp != NULL) 550 *dp = (tag >> 15) & 0x1f; 551 if (fp != NULL) 552 *fp = (tag >> 12) & 0x7; 553 } 554 555 pcireg_t 556 rkpcie_conf_read(void *v, pcitag_t tag, int offset) 557 { 558 struct rkpcie_softc *sc = v; 559 struct pcihost_softc *phsc = &sc->sc_phsc; 560 int bus, dev, fn; 561 u_int reg; 562 563 KASSERT(offset >= 0); 564 KASSERT(offset < PCI_EXTCONF_SIZE); 565 566 rkpcie_decompose_tag(sc, tag, &bus, &dev, &fn); 567 reg = (bus << 20) | (dev << 15) | (fn << 12) | offset; 568 569 if (bus == phsc->sc_bus_min) { 570 KASSERT(dev == 0); 571 return HREAD4(sc, PCIE_RC_NORMAL_BASE + reg); 572 } 573 if (bus == phsc->sc_bus_min + 1) { 574 KASSERT(dev == 0); 575 return bus_space_read_4(sc->sc_iot, sc->sc_axi_ioh, reg); 576 } 577 578 return 0xffffffff; 579 } 580 581 void 582 rkpcie_conf_write(void *v, pcitag_t tag, int offset, pcireg_t data) 583 { 584 struct rkpcie_softc *sc = v; 585 struct pcihost_softc *phsc = &sc->sc_phsc; 586 int bus, dev, fn; 587 u_int reg; 588 589 KASSERT(offset >= 0); 590 KASSERT(offset < PCI_EXTCONF_SIZE); 591 592 rkpcie_decompose_tag(sc, tag, &bus, &dev, &fn); 593 reg = (bus << 20) | (dev << 15) | (fn << 12) | offset; 594 595 if (bus == phsc->sc_bus_min) { 596 KASSERT(dev == 0); 597 HWRITE4(sc, PCIE_RC_NORMAL_BASE + reg, data); 598 return; 599 } 600 if (bus == phsc->sc_bus_min + 1) { 601 KASSERT(dev == 0); 602 bus_space_write_4(sc->sc_iot, sc->sc_axi_ioh, reg, data); 603 return; 604 } 605 } 606 607 static int 608 rkpcie_conf_hook(void *v, int b, int d, int f, pcireg_t id) 609 { 610 return (PCI_CONF_DEFAULT & ~PCI_CONF_ENABLE_BM) | PCI_CONF_MAP_ROM; 611 } 612 613 /* INTx interrupt controller */ 614 static void * 615 rkpcie_intx_establish(device_t dev, u_int *specifier, int ipl, int flags, 616 int (*func)(void *), void *arg) 617 { 618 struct rkpcie_softc *sc = device_private(dev); 619 void *cookie; 620 621 const u_int pin = be32toh(specifier[0]); 622 device_printf(sc->sc_phsc.sc_dev, "%s pin %u\n", __func__, pin); 623 624 /* Unmask legacy interrupts. */ 625 HWRITE4(sc, PCIE_CLIENT_INT_MASK, 626 PCIM_INTx_ENAB(0) | PCIM_INTx_ENAB(1) | 627 PCIM_INTx_ENAB(2) | PCIM_INTx_ENAB(3)); 628 629 cookie = fdtbus_intr_establish_byname(sc->sc_phsc.sc_phandle, "legacy", ipl, flags, func, arg); 630 631 return cookie; 632 } 633 634 static void 635 rkpcie_intx_disestablish(device_t dev, void *ih) 636 { 637 struct rkpcie_softc *sc = device_private(dev); 638 device_printf(dev, "%s\n", __func__); 639 fdtbus_intr_disestablish(sc->sc_phsc.sc_phandle, ih); 640 } 641 642 static bool 643 rkpcie_intx_intrstr(device_t dev, u_int *specifier, char *buf, size_t buflen) 644 { 645 struct rkpcie_softc *sc = device_private(dev); 646 647 fdtbus_intr_str(sc->sc_phsc.sc_phandle, 1, buf, buflen); 648 649 return true; 650 } 651 652 static struct fdtbus_interrupt_controller_func rkpcie_intrfuncs = { 653 .establish = rkpcie_intx_establish, 654 .disestablish = rkpcie_intx_disestablish, 655 .intrstr = rkpcie_intx_intrstr, 656 }; 657
Indexes created Thu Oct 02 10:09:58 GMT 2025