rk3399_pcie.c revision 1.4
1 /* $NetBSD: rk3399_pcie.c,v 1.4 2019/06/15 00:08:25 jmcneill Exp $ */ 2 /* 3 * Copyright (c) 2018 Mark Kettenis <kettenis (at) openbsd.org> 4 * 5 * Permission to use, copy, modify, and distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 */ 17 18 #include <sys/cdefs.h> 19 20 __KERNEL_RCSID(1, "$NetBSD: rk3399_pcie.c,v 1.4 2019/06/15 00:08:25 jmcneill Exp $"); 21 22 #include <sys/param.h> 23 #include <sys/systm.h> 24 #include <sys/bitops.h> 25 #include <sys/device.h> 26 #include <sys/extent.h> 27 #include <sys/kmem.h> 28 29 #include <machine/intr.h> 30 #include <sys/bus.h> 31 #include <dev/fdt/fdtvar.h> 32 #include <dev/fdt/syscon.h> 33 #include <arm/cpufunc.h> 34 35 #include <dev/pci/pcidevs.h> 36 #include <dev/pci/pcireg.h> 37 #include <dev/pci/pcivar.h> 38 #include <dev/pci/pciconf.h> 39 40 #include <arm/fdt/pcihost_fdtvar.h> 41 #include <sys/gpio.h> 42 43 #define SETREG(m, v) ((m)<<16|__SHIFTIN((v), (m))) 44 #define GETREG(m, v) (__SHIFTOUT((v), (m))) 45 46 /* APB region */ 47 #define PCIE_CLIENT_BASE 0x000000 48 #define PCIE_CLIENT_BASIC_STRAP_CONF 0x0000 49 #define PCBSC_PCIE_GEN_SEL __BIT(7) 50 #define PCBSC_PGS_GEN1 SETREG(PCBSC_PCIE_GEN_SEL, 0) 51 #define PCBSC_PGS_GEN2 SETREG(PCBSC_PCIE_GEN_SEL, 1) 52 #define PCBSC_MODE_SELECT __BIT(6) 53 #define PCBSC_MS_ENDPOINT SETREG(PCBSC_MODE_SELECT, 0) 54 #define PCBSC_MS_ROOTPORT SETREG(PCBSC_MODE_SELECT, 1) 55 #define PCBSC_LANE_COUNT __BITS(5,4) 56 #define PCBSC_LC(x) SETREG(PCBSC_LANE_COUNT, ilog2(x)) /* valid for x1,2,4 */ 57 #define PCBSC_ARI_EN SETREG(__BIT(3), 1) /* Alternate Routing ID Enable */ 58 #define PCBSC_SR_IOV_EN SETREG(__BIT(2), 1) 59 #define PCBSC_LINK_TRAIN_EN SETREG(__BIT(1), 1) 60 #define PCBSC_CONF_EN SETREG(__BIT(0), 1) /* Config enable */ 61 #define PCIE_CLIENT_DEBUG_OUT_0 0x003c 62 #define PCIE_CLIENT_DEBUG_OUT_1 0x0040 63 #define PCIE_CLIENT_BASIC_STATUS0 0x0044 64 #define PCIE_CLIENT_BASIC_STATUS1 0x0048 65 #define PCBS1_LINK_ST(x) (u_int)__SHIFTOUT((x), __BITS(21,20)) 66 #define PCBS1_LS_NO_RECV 0 /* no receivers */ 67 #define PCBS1_LS_TRAINING 1 /* link training */ 68 #define PCBS1_LS_DL_INIT 2 /* link up, DL init progressing */ 69 #define PCBS1_LS_DL_DONE 3 /* link up, DL init complete */ 70 #define PCIE_CLIENT_INT_MASK 0x004c 71 #define PCIM_INTx_MASK(x) SETREG(__BIT((x)+5), 1) 72 #define PCIM_INTx_ENAB(x) SETREG(__BIT((x)+5), 0) 73 74 #define PCIE_CORE_BASE 0x800000 75 #define PCIE_RC_NORMAL_BASE (PCIE_CORE_BASE + 0x00000) 76 77 #define PCIE_LM_BASE 0x900000 78 #define PCIE_LM_CORE_CTRL (PCIE_LM_BASE + 0x00) 79 #define PCIE_CORE_PL_CONF_SPEED_5G 0x00000008 80 #define PCIE_CORE_PL_CONF_SPEED_MASK 0x00000018 81 #define PCIE_CORE_PL_CONF_LANE_MASK 0x00000006 82 #define PCIE_CORE_PL_CONF_LANE_SHIFT 1 83 #define PCIE_LM_PLC1 (PCIE_LM_BASE + 0x04) 84 #define PCIE_LM_PLC1_FTS_MASK __BITS(23, 8) 85 #define PCIE_LM_VENDOR_ID (PCIE_LM_BASE + 0x44) 86 #define PCIE_LM_LINKWIDTH (PCIE_LM_BASE + 0x50) 87 #define PCIE_LM_LANEMAP (PCIE_LM_BASE + 0x200) 88 #define PCIE_LM_DEBUG_MUX_CONTROL (PCIE_LM_BASE + 0x208) 89 #define PCIE_LM_RCBAR (PCIE_LM_BASE + 0x300) 90 #define PCIE_LM_RCBARPME __BIT(17) 91 #define PCIE_LM_RCBARPMS __BIT(18) 92 #define PCIE_LM_RCBARPIE __BIT(19) 93 #define PCIE_LM_RCBARPIS __BIT(20) 94 95 #define PCIE_RC_BASE 0xa00000 96 #define PCIE_RC_CONFIG_DCSR (PCIE_RC_BASE + 0x0c0 + PCIE_DCSR) 97 #define PCIE_RC_PCIE_LCAP (PCIE_RC_BASE + 0x0c0 + PCIE_LCAP) 98 #define PCIE_RC_CONFIG_LCSR (PCIE_RC_BASE + 0x0c0 + PCIE_LCSR) 99 #define PCIE_RC_CONFIG_THP_CAP (PCIE_RC_BASE + 0x274) 100 #define PCIE_RC_CONFIG_THP_CAP_NEXT_MASK __BITS(31, 20) 101 102 103 #define PCIE_ATR_BASE 0xc00000 104 #define PCIE_ATR_OB_ADDR0(i) (PCIE_ATR_BASE + 0x000 + (i) * 0x20) 105 #define PCIE_ATR_OB_ADDR1(i) (PCIE_ATR_BASE + 0x004 + (i) * 0x20) 106 #define PCIE_ATR_OB_DESC0(i) (PCIE_ATR_BASE + 0x008 + (i) * 0x20) 107 #define PCIE_ATR_OB_DESC1(i) (PCIE_ATR_BASE + 0x00c + (i) * 0x20) 108 #define PCIE_ATR_IB_ADDR0(i) (PCIE_ATR_BASE + 0x800 + (i) * 0x8) 109 #define PCIE_ATR_IB_ADDR1(i) (PCIE_ATR_BASE + 0x804 + (i) * 0x8) 110 #define PCIE_ATR_HDR_MEM 0x2 111 #define PCIE_ATR_HDR_IO 0x6 112 #define PCIE_ATR_HDR_CFG_TYPE0 0xa 113 #define PCIE_ATR_HDR_CFG_TYPE1 0xb 114 #define PCIE_ATR_HDR_RID __BIT(23) 115 116 /* AXI region */ 117 #define PCIE_ATR_OB_REGION0_SIZE (32 * 1024 * 1024) 118 #define PCIE_ATR_OB_REGION_SIZE (1 * 1024 * 1024) 119 120 #define HREAD4(sc, reg) \ 121 (bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg))) 122 #define HWRITE4(sc, reg, val) \ 123 bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val)) 124 125 struct rkpcie_softc { 126 struct pcihost_softc sc_phsc; 127 bus_space_tag_t sc_iot; 128 bus_space_handle_t sc_ioh; 129 bus_space_handle_t sc_axi_ioh; 130 bus_addr_t sc_axi_addr; 131 bus_addr_t sc_apb_addr; 132 bus_size_t sc_axi_size; 133 bus_size_t sc_apb_size; 134 }; 135 136 static int rkpcie_match(device_t, cfdata_t, void *); 137 static void rkpcie_attach(device_t, device_t, void *); 138 139 CFATTACH_DECL_NEW(rkpcie, sizeof(struct rkpcie_softc), 140 rkpcie_match, rkpcie_attach, NULL, NULL); 141 142 static int 143 rkpcie_match(device_t parent, cfdata_t cf, void *aux) 144 { 145 const char * const compatible[] = { 146 "rockchip,rk3399-pcie", 147 NULL 148 }; 149 struct fdt_attach_args *faa = aux; 150 151 return of_match_compatible(faa->faa_phandle, compatible); 152 } 153 154 static void rkpcie_atr_init(struct rkpcie_softc *); 155 156 static int rkpcie_bus_maxdevs(void *, int); 157 static pcitag_t rkpcie_make_tag(void *, int, int, int); 158 static void rkpcie_decompose_tag(void *, pcitag_t, int *, int *, int *); 159 static pcireg_t rkpcie_conf_read(void *, pcitag_t, int); 160 static void rkpcie_conf_write(void *, pcitag_t, int, pcireg_t); 161 static int rkpcie_conf_hook(void *, int, int, int, pcireg_t); 162 163 static struct fdtbus_interrupt_controller_func rkpcie_intrfuncs; 164 165 static inline void 166 clock_enable_all(int phandle) 167 { 168 for (u_int i = 0; i < 4; i++) { 169 struct clk * clk = fdtbus_clock_get_index(phandle, i); 170 if (clk == NULL) 171 continue; 172 if (clk_enable(clk) != 0) 173 continue; 174 } 175 } 176 177 static void 178 reset_assert(int phandle, const char *name) 179 { 180 struct fdtbus_reset *rst; 181 182 rst = fdtbus_reset_get(phandle, name); 183 fdtbus_reset_assert(rst); 184 fdtbus_reset_put(rst); 185 } 186 187 static void 188 reset_deassert(int phandle, const char *name) 189 { 190 struct fdtbus_reset *rst; 191 192 rst = fdtbus_reset_get(phandle, name); 193 fdtbus_reset_deassert(rst); 194 fdtbus_reset_put(rst); 195 } 196 197 static void 198 rkpcie_attach(device_t parent, device_t self, void *aux) 199 { 200 struct rkpcie_softc *sc = device_private(self); 201 struct pcihost_softc * const phsc = &sc->sc_phsc; 202 struct fdt_attach_args *faa = aux; 203 struct fdtbus_gpio_pin *ep_gpio; 204 u_int max_link_speed, num_lanes; 205 struct fdtbus_phy *phy[4]; 206 const u_int *bus_range; 207 uint32_t status; 208 int timo, len; 209 210 phsc->sc_dev = self; 211 phsc->sc_bst = faa->faa_bst; 212 phsc->sc_dmat = faa->faa_dmat; 213 sc->sc_iot = phsc->sc_bst; 214 phsc->sc_phandle = faa->faa_phandle; 215 const int phandle = phsc->sc_phandle; 216 217 if (fdtbus_get_reg_byname(faa->faa_phandle, "axi-base", &sc->sc_axi_addr, &sc->sc_axi_size) != 0) { 218 aprint_error(": couldn't get axi registers\n"); 219 return; 220 } 221 if (fdtbus_get_reg_byname(faa->faa_phandle, "apb-base", &sc->sc_apb_addr, &sc->sc_apb_size) != 0) { 222 aprint_error(": couldn't get apb registers\n"); 223 sc->sc_axi_size = 0; 224 return; 225 } 226 227 if (bus_space_map(sc->sc_iot, sc->sc_apb_addr, sc->sc_apb_size, 0, &sc->sc_ioh) != 0 || 228 bus_space_map(sc->sc_iot, sc->sc_axi_addr, sc->sc_axi_size, 0, &sc->sc_axi_ioh) != 0) { 229 printf(": can't map registers\n"); 230 sc->sc_axi_size = 0; 231 sc->sc_apb_size = 0; 232 return; 233 } 234 235 aprint_naive("\n"); 236 aprint_normal(": RK3399 PCIe\n"); 237 238 struct fdtbus_regulator *regulator; 239 regulator = fdtbus_regulator_acquire(phandle, "vpcie3v3-supply"); 240 fdtbus_regulator_enable(regulator); 241 fdtbus_regulator_release(regulator); 242 243 fdtbus_clock_assign(phandle); 244 clock_enable_all(phandle); 245 246 ep_gpio = fdtbus_gpio_acquire(phandle, "ep-gpios", GPIO_PIN_OUTPUT); 247 248 if (of_getprop_uint32(phandle, "max-link-speed", &max_link_speed) != 0) 249 max_link_speed = 2; 250 if (of_getprop_uint32(phandle, "num-lanes", &num_lanes) != 0) 251 num_lanes = 1; 252 253 again: 254 fdtbus_gpio_write(ep_gpio, 0); 255 256 reset_assert(phandle, "aclk"); 257 reset_assert(phandle, "pclk"); 258 reset_assert(phandle, "pm"); 259 260 memset(phy, 0, sizeof(phy)); 261 phy[0] = fdtbus_phy_get(phandle, "pcie-phy-0"); 262 if (phy[0] == NULL) { 263 phy[0] = fdtbus_phy_get(phandle, "pcie-phy"); 264 } else { 265 phy[1] = fdtbus_phy_get(phandle, "pcie-phy-1"); 266 phy[2] = fdtbus_phy_get(phandle, "pcie-phy-2"); 267 phy[3] = fdtbus_phy_get(phandle, "pcie-phy-3"); 268 } 269 270 reset_assert(phandle, "core"); 271 reset_assert(phandle, "mgmt"); 272 reset_assert(phandle, "mgmt-sticky"); 273 reset_assert(phandle, "pipe"); 274 275 delay(10); 276 277 reset_deassert(phandle, "pm"); 278 reset_deassert(phandle, "aclk"); 279 reset_deassert(phandle, "pclk"); 280 281 if (max_link_speed == 1) 282 HWRITE4(sc, PCIE_CLIENT_BASIC_STRAP_CONF, PCBSC_PGS_GEN1); 283 else 284 HWRITE4(sc, PCIE_CLIENT_BASIC_STRAP_CONF, PCBSC_PGS_GEN2); 285 286 /* Switch into Root Complex mode. */ 287 HWRITE4(sc, PCIE_CLIENT_BASIC_STRAP_CONF, 288 PCBSC_MS_ROOTPORT | PCBSC_CONF_EN | PCBSC_LC(num_lanes)); 289 290 if (phy[3] && fdtbus_phy_enable(phy[3], true) != 0) { 291 aprint_error(": couldn't enable phy3\n"); 292 } 293 if (phy[2] && fdtbus_phy_enable(phy[2], true) != 0) { 294 aprint_error(": couldn't enable phy2\n"); 295 } 296 if (phy[1] && fdtbus_phy_enable(phy[1], true) != 0) { 297 aprint_error(": couldn't enable phy1\n"); 298 } 299 if (phy[0] && fdtbus_phy_enable(phy[0], true) != 0) { 300 aprint_error(": couldn't enable phy0\n"); 301 } 302 303 reset_deassert(phandle, "mgmt-sticky"); 304 reset_deassert(phandle, "core"); 305 reset_deassert(phandle, "mgmt"); 306 reset_deassert(phandle, "pipe"); 307 308 /* Start link training. */ 309 HWRITE4(sc, PCIE_CLIENT_BASIC_STRAP_CONF, PCBSC_LINK_TRAIN_EN); 310 311 fdtbus_gpio_write(ep_gpio, 1); 312 313 for (timo = 500; timo > 0; timo--) { 314 status = HREAD4(sc, PCIE_CLIENT_BASIC_STATUS1); 315 if (PCBS1_LINK_ST(status) == PCBS1_LS_DL_DONE) 316 break; 317 delay(1000); 318 } 319 if (timo == 0) { 320 device_printf(self, "link training timeout (link_st %u)\n", 321 PCBS1_LINK_ST(status)); 322 if (max_link_speed > 1) { 323 --max_link_speed; 324 goto again; 325 } 326 return; 327 } 328 329 if (max_link_speed == 2) { 330 HWRITE4(sc, PCIE_RC_CONFIG_LCSR, HREAD4(sc, PCIE_RC_CONFIG_LCSR) | PCIE_LCSR_RETRAIN); 331 for (timo = 500; timo > 0; timo--) { 332 status = HREAD4(sc, PCIE_LM_CORE_CTRL); 333 if ((status & PCIE_CORE_PL_CONF_SPEED_MASK) == PCIE_CORE_PL_CONF_SPEED_5G) 334 break; 335 delay(1000); 336 } 337 if (timo == 0) { 338 device_printf(self, "Gen2 link training timeout\n"); 339 --max_link_speed; 340 goto again; 341 } 342 } 343 344 fdtbus_gpio_release(ep_gpio); 345 346 HWRITE4(sc, PCIE_RC_BASE + PCI_CLASS_REG, 347 PCI_CLASS_BRIDGE << PCI_CLASS_SHIFT | 348 PCI_SUBCLASS_BRIDGE_PCI << PCI_SUBCLASS_SHIFT); 349 350 /* Initialize Root Complex registers. */ 351 HWRITE4(sc, PCIE_LM_VENDOR_ID, PCI_VENDOR_ROCKCHIP); 352 HWRITE4(sc, PCIE_RC_BASE + PCI_CLASS_REG, 353 PCI_CLASS_BRIDGE << PCI_CLASS_SHIFT | 354 PCI_SUBCLASS_BRIDGE_PCI << PCI_SUBCLASS_SHIFT); 355 HWRITE4(sc, PCIE_LM_RCBAR, PCIE_LM_RCBARPIE | PCIE_LM_RCBARPIS); 356 357 /* remove L1 substate cap */ 358 status = HREAD4(sc, PCIE_RC_CONFIG_THP_CAP); 359 status &= ~PCIE_RC_CONFIG_THP_CAP_NEXT_MASK; 360 HWRITE4(sc, PCIE_RC_CONFIG_THP_CAP, status); 361 362 if (of_hasprop(phandle, "aspm-no-l0s")) { 363 status = HREAD4(sc, PCIE_RC_PCIE_LCAP); 364 status &= ~__SHIFTIN(1, PCIE_LCAP_ASPM); 365 HWRITE4(sc, PCIE_RC_PCIE_LCAP, status); 366 } 367 368 /* Default bus ranges */ 369 sc->sc_phsc.sc_bus_min = 0; 370 sc->sc_phsc.sc_bus_max = 31; 371 372 /* Override bus range from DT */ 373 bus_range = fdtbus_get_prop(phandle, "bus-range", &len); 374 if (len == 8) { 375 sc->sc_phsc.sc_bus_min = be32dec(&bus_range[0]); 376 sc->sc_phsc.sc_bus_max = be32dec(&bus_range[1]); 377 } 378 379 if (sc->sc_phsc.sc_bus_min != 0) { 380 aprint_error_dev(self, "bus-range doesn't start at 0\n"); 381 return; 382 } 383 384 /* Configure Address Translation. */ 385 rkpcie_atr_init(sc); 386 387 fdtbus_register_interrupt_controller(self, OF_child(sc->sc_phsc.sc_phandle), 388 &rkpcie_intrfuncs); 389 390 sc->sc_phsc.sc_type = PCIHOST_ECAM; 391 #if notyet 392 sc->sc_phsc.sc_pci_flags |= PCI_FLAGS_MSI_OKAY; 393 #endif 394 pcihost_init(&sc->sc_phsc.sc_pc, sc); 395 sc->sc_phsc.sc_pc.pc_bus_maxdevs = rkpcie_bus_maxdevs; 396 sc->sc_phsc.sc_pc.pc_make_tag = rkpcie_make_tag; 397 sc->sc_phsc.sc_pc.pc_decompose_tag = rkpcie_decompose_tag; 398 sc->sc_phsc.sc_pc.pc_conf_read = rkpcie_conf_read; 399 sc->sc_phsc.sc_pc.pc_conf_write = rkpcie_conf_write; 400 sc->sc_phsc.sc_pc.pc_conf_hook = rkpcie_conf_hook; 401 pcihost_init2(&sc->sc_phsc); 402 } 403 404 static void 405 rkpcie_atr_init(struct rkpcie_softc *sc) 406 { 407 const u_int *ranges; 408 bus_addr_t aaddr; 409 bus_addr_t addr; 410 bus_size_t size, resid, offset; 411 uint32_t type; 412 int region, i, ranges_len; 413 414 /* Use region 0 to map PCI configuration space */ 415 HWRITE4(sc, PCIE_ATR_OB_ADDR0(0), 25 - 1); 416 HWRITE4(sc, PCIE_ATR_OB_ADDR1(0), 0); 417 HWRITE4(sc, PCIE_ATR_OB_DESC0(0), PCIE_ATR_HDR_CFG_TYPE0 | PCIE_ATR_HDR_RID); 418 HWRITE4(sc, PCIE_ATR_OB_DESC1(0), 0); 419 420 ranges = fdtbus_get_prop(sc->sc_phsc.sc_phandle, "ranges", &ranges_len); 421 if (ranges == NULL) 422 goto fail; 423 const int ranges_cells = ranges_len / 4; 424 425 for (i = 0; i < ranges_cells; i += 7) { 426 /* Handle IO and MMIO. */ 427 switch (be32toh(ranges[i]) & 0x03000000) { 428 case 0x01000000: 429 type = PCIE_ATR_HDR_IO; 430 break; 431 case 0x02000000: 432 case 0x03000000: 433 type = PCIE_ATR_HDR_MEM; 434 break; 435 default: 436 continue; 437 } 438 439 addr = ((uint64_t)be32toh(ranges[i + 1]) << 32) + be32toh(ranges[i + 2]); 440 aaddr = ((uint64_t)be32toh(ranges[i + 3]) << 32) + be32toh(ranges[i + 4]); 441 size = be32toh(ranges[i + 6]); 442 443 /* Only support mappings aligned on a region boundary. */ 444 if (addr & (PCIE_ATR_OB_REGION_SIZE - 1)) 445 goto fail; 446 if (aaddr & (PCIE_ATR_OB_REGION_SIZE - 1)) 447 goto fail; 448 if (size & (PCIE_ATR_OB_REGION_SIZE - 1)) 449 goto fail; 450 451 /* Mappings should lie in AXI region. */ 452 if (aaddr < sc->sc_axi_addr) 453 goto fail; 454 if (aaddr + size > sc->sc_axi_addr + 64*1024*1024) 455 goto fail; 456 457 offset = addr - sc->sc_axi_addr - PCIE_ATR_OB_REGION0_SIZE; 458 region = 1 + (offset / PCIE_ATR_OB_REGION_SIZE); 459 resid = size; 460 while (resid > 0) { 461 HWRITE4(sc, PCIE_ATR_OB_ADDR0(region), 32 - 1); 462 HWRITE4(sc, PCIE_ATR_OB_ADDR1(region), 0); 463 HWRITE4(sc, PCIE_ATR_OB_DESC0(region), type | PCIE_ATR_HDR_RID); 464 HWRITE4(sc, PCIE_ATR_OB_DESC1(region), 0); 465 466 addr += PCIE_ATR_OB_REGION_SIZE; 467 resid -= PCIE_ATR_OB_REGION_SIZE; 468 region++; 469 } 470 } 471 472 /* Passthrought inbound translations unmodified. */ 473 HWRITE4(sc, PCIE_ATR_IB_ADDR0(2), 32 - 1); 474 HWRITE4(sc, PCIE_ATR_IB_ADDR1(2), 0); 475 476 return; 477 478 fail: 479 device_printf(sc->sc_phsc.sc_dev, "can't map ranges\n"); 480 } 481 482 int 483 rkpcie_bus_maxdevs(void *v, int bus) 484 { 485 struct rkpcie_softc *rksc = v; 486 struct pcihost_softc *sc = &rksc->sc_phsc; 487 488 if (bus == sc->sc_bus_min || bus == sc->sc_bus_min + 1) 489 return 1; 490 return 32; 491 } 492 493 pcitag_t 494 rkpcie_make_tag(void *v, int bus, int device, int function) 495 { 496 /* Return ECAM address. */ 497 return ((bus << 20) | (device << 15) | (function << 12)); 498 } 499 500 void 501 rkpcie_decompose_tag(void *v, pcitag_t tag, int *bp, int *dp, int *fp) 502 { 503 if (bp != NULL) 504 *bp = (tag >> 20) & 0xff; 505 if (dp != NULL) 506 *dp = (tag >> 15) & 0x1f; 507 if (fp != NULL) 508 *fp = (tag >> 12) & 0x7; 509 } 510 511 pcireg_t 512 rkpcie_conf_read(void *v, pcitag_t tag, int offset) 513 { 514 struct rkpcie_softc *sc = v; 515 struct pcihost_softc *phsc = &sc->sc_phsc; 516 int bus, dev, fn; 517 u_int reg; 518 519 KASSERT(offset >= 0); 520 KASSERT(offset < PCI_EXTCONF_SIZE); 521 522 rkpcie_decompose_tag(sc, tag, &bus, &dev, &fn); 523 reg = (bus << 20) | (dev << 15) | (fn << 12) | offset; 524 525 if (bus == phsc->sc_bus_min) { 526 KASSERT(dev == 0); 527 return HREAD4(sc, PCIE_RC_NORMAL_BASE + reg); 528 } 529 if (bus == phsc->sc_bus_min + 1) { 530 KASSERT(dev == 0); 531 return bus_space_read_4(sc->sc_iot, sc->sc_axi_ioh, reg); 532 } 533 534 return 0xffffffff; 535 } 536 537 void 538 rkpcie_conf_write(void *v, pcitag_t tag, int offset, pcireg_t data) 539 { 540 struct rkpcie_softc *sc = v; 541 struct pcihost_softc *phsc = &sc->sc_phsc; 542 int bus, dev, fn; 543 u_int reg; 544 545 KASSERT(offset >= 0); 546 KASSERT(offset < PCI_EXTCONF_SIZE); 547 548 rkpcie_decompose_tag(sc, tag, &bus, &dev, &fn); 549 reg = (bus << 20) | (dev << 15) | (fn << 12) | offset; 550 551 if (bus == phsc->sc_bus_min) { 552 KASSERT(dev == 0); 553 HWRITE4(sc, PCIE_RC_NORMAL_BASE + reg, data); 554 return; 555 } 556 if (bus == phsc->sc_bus_min + 1) { 557 KASSERT(dev == 0); 558 bus_space_write_4(sc->sc_iot, sc->sc_axi_ioh, reg, data); 559 return; 560 } 561 } 562 563 static int 564 rkpcie_conf_hook(void *v, int b, int d, int f, pcireg_t id) 565 { 566 return (PCI_CONF_DEFAULT & ~PCI_CONF_ENABLE_BM) | PCI_CONF_MAP_ROM; 567 } 568 569 /* INTx interrupt controller */ 570 static void * 571 rkpcie_intx_establish(device_t dev, u_int *specifier, int ipl, int flags, 572 int (*func)(void *), void *arg) 573 { 574 struct rkpcie_softc *sc = device_private(dev); 575 void *cookie; 576 577 #if notyet 578 const u_int pin = be32toh(specifier[0]); 579 #endif 580 581 /* Unmask legacy interrupts. */ 582 HWRITE4(sc, PCIE_CLIENT_INT_MASK, 583 PCIM_INTx_ENAB(0) | PCIM_INTx_ENAB(1) | 584 PCIM_INTx_ENAB(2) | PCIM_INTx_ENAB(3)); 585 586 cookie = fdtbus_intr_establish_byname(sc->sc_phsc.sc_phandle, "legacy", ipl, flags, func, arg); 587 588 return cookie; 589 } 590 591 static void 592 rkpcie_intx_disestablish(device_t dev, void *ih) 593 { 594 struct rkpcie_softc *sc = device_private(dev); 595 device_printf(dev, "%s\n", __func__); 596 fdtbus_intr_disestablish(sc->sc_phsc.sc_phandle, ih); 597 } 598 599 static bool 600 rkpcie_intx_intrstr(device_t dev, u_int *specifier, char *buf, size_t buflen) 601 { 602 struct rkpcie_softc *sc = device_private(dev); 603 604 fdtbus_intr_str(sc->sc_phsc.sc_phandle, 1, buf, buflen); 605 606 return true; 607 } 608 609 static struct fdtbus_interrupt_controller_func rkpcie_intrfuncs = { 610 .establish = rkpcie_intx_establish, 611 .disestablish = rkpcie_intx_disestablish, 612 .intrstr = rkpcie_intx_intrstr, 613 }; 614
Indexes created Thu Oct 02 10:09:58 GMT 2025