rk3399_pcie.c revision 1.6
1 /* $NetBSD: rk3399_pcie.c,v 1.6 2019/06/23 16:15:43 jmcneill Exp $ */ 2 /* 3 * Copyright (c) 2018 Mark Kettenis <kettenis (at) openbsd.org> 4 * 5 * Permission to use, copy, modify, and distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 */ 17 18 #include <sys/cdefs.h> 19 20 __KERNEL_RCSID(1, "$NetBSD: rk3399_pcie.c,v 1.6 2019/06/23 16:15:43 jmcneill Exp $"); 21 22 #include <sys/param.h> 23 #include <sys/systm.h> 24 #include <sys/bitops.h> 25 #include <sys/device.h> 26 #include <sys/extent.h> 27 #include <sys/kmem.h> 28 29 #include <machine/intr.h> 30 #include <sys/bus.h> 31 #include <dev/fdt/fdtvar.h> 32 #include <dev/fdt/syscon.h> 33 #include <arm/cpufunc.h> 34 35 #include <dev/pci/pcidevs.h> 36 #include <dev/pci/pcireg.h> 37 #include <dev/pci/pcivar.h> 38 #include <dev/pci/pciconf.h> 39 40 #include <arm/fdt/pcihost_fdtvar.h> 41 #include <sys/gpio.h> 42 43 #define SETREG(m, v) ((m)<<16|__SHIFTIN((v), (m))) 44 #define GETREG(m, v) (__SHIFTOUT((v), (m))) 45 46 /* APB region */ 47 #define PCIE_CLIENT_BASE 0x000000 48 #define PCIE_CLIENT_BASIC_STRAP_CONF 0x0000 49 #define PCBSC_PCIE_GEN_SEL __BIT(7) 50 #define PCBSC_PGS_GEN1 SETREG(PCBSC_PCIE_GEN_SEL, 0) 51 #define PCBSC_PGS_GEN2 SETREG(PCBSC_PCIE_GEN_SEL, 1) 52 #define PCBSC_MODE_SELECT __BIT(6) 53 #define PCBSC_MS_ENDPOINT SETREG(PCBSC_MODE_SELECT, 0) 54 #define PCBSC_MS_ROOTPORT SETREG(PCBSC_MODE_SELECT, 1) 55 #define PCBSC_LANE_COUNT __BITS(5,4) 56 #define PCBSC_LC(x) SETREG(PCBSC_LANE_COUNT, ilog2(x)) /* valid for x1,2,4 */ 57 #define PCBSC_ARI_EN SETREG(__BIT(3), 1) /* Alternate Routing ID Enable */ 58 #define PCBSC_SR_IOV_EN SETREG(__BIT(2), 1) 59 #define PCBSC_LINK_TRAIN_EN SETREG(__BIT(1), 1) 60 #define PCBSC_CONF_EN SETREG(__BIT(0), 1) /* Config enable */ 61 #define PCIE_CLIENT_DEBUG_OUT_0 0x003c 62 #define PCIE_CLIENT_DEBUG_OUT_1 0x0040 63 #define PCIE_CLIENT_BASIC_STATUS0 0x0044 64 #define PCIE_CLIENT_BASIC_STATUS1 0x0048 65 #define PCBS1_LINK_ST(x) (u_int)__SHIFTOUT((x), __BITS(21,20)) 66 #define PCBS1_LS_NO_RECV 0 /* no receivers */ 67 #define PCBS1_LS_TRAINING 1 /* link training */ 68 #define PCBS1_LS_DL_INIT 2 /* link up, DL init progressing */ 69 #define PCBS1_LS_DL_DONE 3 /* link up, DL init complete */ 70 #define PCIE_CLIENT_INT_MASK 0x004c 71 #define PCIM_INTx_MASK(x) SETREG(__BIT((x)+5), 1) 72 #define PCIM_INTx_ENAB(x) SETREG(__BIT((x)+5), 0) 73 74 #define PCIE_CORE_BASE 0x800000 75 #define PCIE_RC_NORMAL_BASE (PCIE_CORE_BASE + 0x00000) 76 77 #define PCIE_LM_BASE 0x900000 78 #define PCIE_LM_CORE_CTRL (PCIE_LM_BASE + 0x00) 79 #define PCIE_CORE_PL_CONF_SPEED_5G 0x00000008 80 #define PCIE_CORE_PL_CONF_SPEED_MASK 0x00000018 81 #define PCIE_CORE_PL_CONF_LANE_MASK 0x00000006 82 #define PCIE_CORE_PL_CONF_LANE_SHIFT 1 83 #define PCIE_LM_PLC1 (PCIE_LM_BASE + 0x04) 84 #define PCIE_LM_PLC1_FTS_MASK __BITS(23, 8) 85 #define PCIE_LM_VENDOR_ID (PCIE_LM_BASE + 0x44) 86 #define PCIE_LM_LINKWIDTH (PCIE_LM_BASE + 0x50) 87 #define PCIE_LM_LANEMAP (PCIE_LM_BASE + 0x200) 88 #define PCIE_LM_DEBUG_MUX_CONTROL (PCIE_LM_BASE + 0x208) 89 #define PCIE_LM_RCBAR (PCIE_LM_BASE + 0x300) 90 #define PCIE_LM_RCBARPME __BIT(17) 91 #define PCIE_LM_RCBARPMS __BIT(18) 92 #define PCIE_LM_RCBARPIE __BIT(19) 93 #define PCIE_LM_RCBARPIS __BIT(20) 94 95 #define PCIE_RC_BASE 0xa00000 96 #define PCIE_RC_CONFIG_DCSR (PCIE_RC_BASE + 0x0c0 + PCIE_DCSR) 97 #define PCIE_RC_PCIE_LCAP (PCIE_RC_BASE + 0x0c0 + PCIE_LCAP) 98 #define PCIE_RC_CONFIG_LCSR (PCIE_RC_BASE + 0x0c0 + PCIE_LCSR) 99 #define PCIE_RC_CONFIG_THP_CAP (PCIE_RC_BASE + 0x274) 100 #define PCIE_RC_CONFIG_THP_CAP_NEXT_MASK __BITS(31, 20) 101 102 103 #define PCIE_ATR_BASE 0xc00000 104 #define PCIE_ATR_OB_ADDR0(i) (PCIE_ATR_BASE + 0x000 + (i) * 0x20) 105 #define PCIE_ATR_OB_ADDR1(i) (PCIE_ATR_BASE + 0x004 + (i) * 0x20) 106 #define PCIE_ATR_OB_DESC0(i) (PCIE_ATR_BASE + 0x008 + (i) * 0x20) 107 #define PCIE_ATR_OB_DESC1(i) (PCIE_ATR_BASE + 0x00c + (i) * 0x20) 108 #define PCIE_ATR_IB_ADDR0(i) (PCIE_ATR_BASE + 0x800 + (i) * 0x8) 109 #define PCIE_ATR_IB_ADDR1(i) (PCIE_ATR_BASE + 0x804 + (i) * 0x8) 110 #define PCIE_ATR_HDR_MEM 0x2 111 #define PCIE_ATR_HDR_IO 0x6 112 #define PCIE_ATR_HDR_CFG_TYPE0 0xa 113 #define PCIE_ATR_HDR_CFG_TYPE1 0xb 114 #define PCIE_ATR_HDR_RID __BIT(23) 115 116 /* AXI region */ 117 #define PCIE_ATR_OB_REGION0_SIZE (32 * 1024 * 1024) 118 #define PCIE_ATR_OB_REGION_SIZE (1 * 1024 * 1024) 119 120 #define HREAD4(sc, reg) \ 121 bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg)) 122 #define HWRITE4(sc, reg, val) \ 123 bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val)) 124 #define AXIREAD4(sc, reg) \ 125 bus_space_read_4((sc)->sc_iot, (sc)->sc_axi_ioh, (reg)) 126 #define AXIWRITE4(sc, reg, val) \ 127 bus_space_write_4((sc)->sc_iot, (sc)->sc_axi_ioh, (reg), (val)) 128 129 struct rkpcie_softc { 130 struct pcihost_softc sc_phsc; 131 bus_space_tag_t sc_iot; 132 bus_space_handle_t sc_ioh; 133 bus_space_handle_t sc_axi_ioh; 134 bus_addr_t sc_axi_addr; 135 bus_addr_t sc_apb_addr; 136 bus_size_t sc_axi_size; 137 bus_size_t sc_apb_size; 138 }; 139 140 static int rkpcie_match(device_t, cfdata_t, void *); 141 static void rkpcie_attach(device_t, device_t, void *); 142 143 CFATTACH_DECL_NEW(rkpcie, sizeof(struct rkpcie_softc), 144 rkpcie_match, rkpcie_attach, NULL, NULL); 145 146 static int 147 rkpcie_match(device_t parent, cfdata_t cf, void *aux) 148 { 149 const char * const compatible[] = { 150 "rockchip,rk3399-pcie", 151 NULL 152 }; 153 struct fdt_attach_args *faa = aux; 154 155 return of_match_compatible(faa->faa_phandle, compatible); 156 } 157 158 static void rkpcie_atr_init(struct rkpcie_softc *); 159 160 static int rkpcie_bus_maxdevs(void *, int); 161 static pcitag_t rkpcie_make_tag(void *, int, int, int); 162 static void rkpcie_decompose_tag(void *, pcitag_t, int *, int *, int *); 163 static pcireg_t rkpcie_conf_read(void *, pcitag_t, int); 164 static void rkpcie_conf_write(void *, pcitag_t, int, pcireg_t); 165 static int rkpcie_conf_hook(void *, int, int, int, pcireg_t); 166 167 static struct fdtbus_interrupt_controller_func rkpcie_intrfuncs; 168 169 static inline void 170 clock_enable_all(int phandle) 171 { 172 for (u_int i = 0; i < 4; i++) { 173 struct clk * clk = fdtbus_clock_get_index(phandle, i); 174 if (clk == NULL) 175 continue; 176 if (clk_enable(clk) != 0) 177 continue; 178 } 179 } 180 181 static void 182 reset_assert(int phandle, const char *name) 183 { 184 struct fdtbus_reset *rst; 185 186 rst = fdtbus_reset_get(phandle, name); 187 fdtbus_reset_assert(rst); 188 fdtbus_reset_put(rst); 189 } 190 191 static void 192 reset_deassert(int phandle, const char *name) 193 { 194 struct fdtbus_reset *rst; 195 196 rst = fdtbus_reset_get(phandle, name); 197 fdtbus_reset_deassert(rst); 198 fdtbus_reset_put(rst); 199 } 200 201 static void 202 rkpcie_attach(device_t parent, device_t self, void *aux) 203 { 204 struct rkpcie_softc *sc = device_private(self); 205 struct pcihost_softc * const phsc = &sc->sc_phsc; 206 struct fdt_attach_args *faa = aux; 207 struct fdtbus_gpio_pin *ep_gpio; 208 u_int max_link_speed, num_lanes; 209 struct fdtbus_phy *phy[4]; 210 const u_int *bus_range; 211 uint32_t status; 212 int timo, len; 213 214 phsc->sc_dev = self; 215 phsc->sc_bst = faa->faa_bst; 216 phsc->sc_dmat = faa->faa_dmat; 217 sc->sc_iot = phsc->sc_bst; 218 phsc->sc_phandle = faa->faa_phandle; 219 const int phandle = phsc->sc_phandle; 220 221 if (fdtbus_get_reg_byname(faa->faa_phandle, "axi-base", &sc->sc_axi_addr, &sc->sc_axi_size) != 0) { 222 aprint_error(": couldn't get axi registers\n"); 223 return; 224 } 225 if (fdtbus_get_reg_byname(faa->faa_phandle, "apb-base", &sc->sc_apb_addr, &sc->sc_apb_size) != 0) { 226 aprint_error(": couldn't get apb registers\n"); 227 sc->sc_axi_size = 0; 228 return; 229 } 230 231 if (bus_space_map(sc->sc_iot, sc->sc_apb_addr, sc->sc_apb_size, 0, &sc->sc_ioh) != 0 || 232 bus_space_map(sc->sc_iot, sc->sc_axi_addr, sc->sc_axi_size, 0, &sc->sc_axi_ioh) != 0) { 233 printf(": can't map registers\n"); 234 sc->sc_axi_size = 0; 235 sc->sc_apb_size = 0; 236 return; 237 } 238 239 aprint_naive("\n"); 240 aprint_normal(": RK3399 PCIe\n"); 241 242 struct fdtbus_regulator *regulator; 243 regulator = fdtbus_regulator_acquire(phandle, "vpcie3v3-supply"); 244 fdtbus_regulator_enable(regulator); 245 fdtbus_regulator_release(regulator); 246 247 fdtbus_clock_assign(phandle); 248 clock_enable_all(phandle); 249 250 ep_gpio = fdtbus_gpio_acquire(phandle, "ep-gpios", GPIO_PIN_OUTPUT); 251 252 if (of_getprop_uint32(phandle, "max-link-speed", &max_link_speed) != 0) 253 max_link_speed = 2; 254 if (of_getprop_uint32(phandle, "num-lanes", &num_lanes) != 0) 255 num_lanes = 1; 256 257 again: 258 fdtbus_gpio_write(ep_gpio, 0); 259 260 reset_assert(phandle, "aclk"); 261 reset_assert(phandle, "pclk"); 262 reset_assert(phandle, "pm"); 263 264 memset(phy, 0, sizeof(phy)); 265 phy[0] = fdtbus_phy_get(phandle, "pcie-phy-0"); 266 if (phy[0] == NULL) { 267 phy[0] = fdtbus_phy_get(phandle, "pcie-phy"); 268 } else { 269 phy[1] = fdtbus_phy_get(phandle, "pcie-phy-1"); 270 phy[2] = fdtbus_phy_get(phandle, "pcie-phy-2"); 271 phy[3] = fdtbus_phy_get(phandle, "pcie-phy-3"); 272 } 273 274 reset_assert(phandle, "core"); 275 reset_assert(phandle, "mgmt"); 276 reset_assert(phandle, "mgmt-sticky"); 277 reset_assert(phandle, "pipe"); 278 279 delay(10); 280 281 reset_deassert(phandle, "pm"); 282 reset_deassert(phandle, "aclk"); 283 reset_deassert(phandle, "pclk"); 284 285 if (max_link_speed == 1) 286 HWRITE4(sc, PCIE_CLIENT_BASIC_STRAP_CONF, PCBSC_PGS_GEN1); 287 else 288 HWRITE4(sc, PCIE_CLIENT_BASIC_STRAP_CONF, PCBSC_PGS_GEN2); 289 290 /* Switch into Root Complex mode. */ 291 HWRITE4(sc, PCIE_CLIENT_BASIC_STRAP_CONF, 292 PCBSC_MS_ROOTPORT | PCBSC_CONF_EN | PCBSC_LC(num_lanes)); 293 294 if (phy[3] && fdtbus_phy_enable(phy[3], true) != 0) { 295 aprint_error(": couldn't enable phy3\n"); 296 } 297 if (phy[2] && fdtbus_phy_enable(phy[2], true) != 0) { 298 aprint_error(": couldn't enable phy2\n"); 299 } 300 if (phy[1] && fdtbus_phy_enable(phy[1], true) != 0) { 301 aprint_error(": couldn't enable phy1\n"); 302 } 303 if (phy[0] && fdtbus_phy_enable(phy[0], true) != 0) { 304 aprint_error(": couldn't enable phy0\n"); 305 } 306 307 reset_deassert(phandle, "mgmt-sticky"); 308 reset_deassert(phandle, "core"); 309 reset_deassert(phandle, "mgmt"); 310 reset_deassert(phandle, "pipe"); 311 312 /* Start link training. */ 313 HWRITE4(sc, PCIE_CLIENT_BASIC_STRAP_CONF, PCBSC_LINK_TRAIN_EN); 314 315 fdtbus_gpio_write(ep_gpio, 1); 316 317 for (timo = 500; timo > 0; timo--) { 318 status = HREAD4(sc, PCIE_CLIENT_BASIC_STATUS1); 319 if (PCBS1_LINK_ST(status) == PCBS1_LS_DL_DONE) 320 break; 321 delay(1000); 322 } 323 if (timo == 0) { 324 device_printf(self, "link training timeout (link_st %u)\n", 325 PCBS1_LINK_ST(status)); 326 if (max_link_speed > 1) { 327 --max_link_speed; 328 goto again; 329 } 330 return; 331 } 332 333 if (max_link_speed == 2) { 334 HWRITE4(sc, PCIE_RC_CONFIG_LCSR, HREAD4(sc, PCIE_RC_CONFIG_LCSR) | PCIE_LCSR_RETRAIN); 335 for (timo = 500; timo > 0; timo--) { 336 status = HREAD4(sc, PCIE_LM_CORE_CTRL); 337 if ((status & PCIE_CORE_PL_CONF_SPEED_MASK) == PCIE_CORE_PL_CONF_SPEED_5G) 338 break; 339 delay(1000); 340 } 341 if (timo == 0) { 342 device_printf(self, "Gen2 link training timeout\n"); 343 --max_link_speed; 344 goto again; 345 } 346 } 347 348 fdtbus_gpio_release(ep_gpio); 349 350 HWRITE4(sc, PCIE_RC_BASE + PCI_CLASS_REG, 351 PCI_CLASS_BRIDGE << PCI_CLASS_SHIFT | 352 PCI_SUBCLASS_BRIDGE_PCI << PCI_SUBCLASS_SHIFT); 353 354 /* Initialize Root Complex registers. */ 355 HWRITE4(sc, PCIE_LM_VENDOR_ID, PCI_VENDOR_ROCKCHIP); 356 HWRITE4(sc, PCIE_RC_BASE + PCI_CLASS_REG, 357 PCI_CLASS_BRIDGE << PCI_CLASS_SHIFT | 358 PCI_SUBCLASS_BRIDGE_PCI << PCI_SUBCLASS_SHIFT); 359 HWRITE4(sc, PCIE_LM_RCBAR, PCIE_LM_RCBARPIE | PCIE_LM_RCBARPIS); 360 361 /* remove L1 substate cap */ 362 status = HREAD4(sc, PCIE_RC_CONFIG_THP_CAP); 363 status &= ~PCIE_RC_CONFIG_THP_CAP_NEXT_MASK; 364 HWRITE4(sc, PCIE_RC_CONFIG_THP_CAP, status); 365 366 if (of_hasprop(phandle, "aspm-no-l0s")) { 367 status = HREAD4(sc, PCIE_RC_PCIE_LCAP); 368 status &= ~__SHIFTIN(1, PCIE_LCAP_ASPM); 369 HWRITE4(sc, PCIE_RC_PCIE_LCAP, status); 370 } 371 372 /* Default bus ranges */ 373 sc->sc_phsc.sc_bus_min = 0; 374 sc->sc_phsc.sc_bus_max = 31; 375 376 /* Override bus range from DT */ 377 bus_range = fdtbus_get_prop(phandle, "bus-range", &len); 378 if (len == 8) { 379 sc->sc_phsc.sc_bus_min = be32dec(&bus_range[0]); 380 sc->sc_phsc.sc_bus_max = be32dec(&bus_range[1]); 381 } 382 383 if (sc->sc_phsc.sc_bus_min != 0) { 384 aprint_error_dev(self, "bus-range doesn't start at 0\n"); 385 return; 386 } 387 388 /* Configure Address Translation. */ 389 rkpcie_atr_init(sc); 390 391 fdtbus_register_interrupt_controller(self, OF_child(sc->sc_phsc.sc_phandle), 392 &rkpcie_intrfuncs); 393 394 sc->sc_phsc.sc_type = PCIHOST_ECAM; 395 sc->sc_phsc.sc_pci_flags |= PCI_FLAGS_MSI_OKAY; 396 sc->sc_phsc.sc_pci_flags |= PCI_FLAGS_MSIX_OKAY; 397 pcihost_init(&sc->sc_phsc.sc_pc, sc); 398 sc->sc_phsc.sc_pc.pc_bus_maxdevs = rkpcie_bus_maxdevs; 399 sc->sc_phsc.sc_pc.pc_make_tag = rkpcie_make_tag; 400 sc->sc_phsc.sc_pc.pc_decompose_tag = rkpcie_decompose_tag; 401 sc->sc_phsc.sc_pc.pc_conf_read = rkpcie_conf_read; 402 sc->sc_phsc.sc_pc.pc_conf_write = rkpcie_conf_write; 403 sc->sc_phsc.sc_pc.pc_conf_hook = rkpcie_conf_hook; 404 pcihost_init2(&sc->sc_phsc); 405 } 406 407 static void 408 rkpcie_atr_init(struct rkpcie_softc *sc) 409 { 410 const u_int *ranges; 411 bus_addr_t aaddr; 412 bus_addr_t addr; 413 bus_size_t size, resid, offset; 414 uint32_t type; 415 int region, i, ranges_len; 416 417 /* Use region 0 to map PCI configuration space */ 418 HWRITE4(sc, PCIE_ATR_OB_ADDR0(0), 25 - 1); 419 HWRITE4(sc, PCIE_ATR_OB_ADDR1(0), 0); 420 HWRITE4(sc, PCIE_ATR_OB_DESC0(0), PCIE_ATR_HDR_CFG_TYPE0 | PCIE_ATR_HDR_RID); 421 HWRITE4(sc, PCIE_ATR_OB_DESC1(0), 0); 422 423 ranges = fdtbus_get_prop(sc->sc_phsc.sc_phandle, "ranges", &ranges_len); 424 if (ranges == NULL) 425 goto fail; 426 const int ranges_cells = ranges_len / 4; 427 428 for (i = 0; i < ranges_cells; i += 7) { 429 /* Handle IO and MMIO. */ 430 switch (be32toh(ranges[i]) & 0x03000000) { 431 case 0x01000000: 432 type = PCIE_ATR_HDR_IO; 433 break; 434 case 0x02000000: 435 case 0x03000000: 436 type = PCIE_ATR_HDR_MEM; 437 break; 438 default: 439 continue; 440 } 441 442 addr = ((uint64_t)be32toh(ranges[i + 1]) << 32) + be32toh(ranges[i + 2]); 443 aaddr = ((uint64_t)be32toh(ranges[i + 3]) << 32) + be32toh(ranges[i + 4]); 444 size = be32toh(ranges[i + 6]); 445 446 /* Only support mappings aligned on a region boundary. */ 447 if (addr & (PCIE_ATR_OB_REGION_SIZE - 1)) 448 goto fail; 449 if (aaddr & (PCIE_ATR_OB_REGION_SIZE - 1)) 450 goto fail; 451 if (size & (PCIE_ATR_OB_REGION_SIZE - 1)) 452 goto fail; 453 454 /* Mappings should lie in AXI region. */ 455 if (aaddr < sc->sc_axi_addr) 456 goto fail; 457 if (aaddr + size > sc->sc_axi_addr + 64*1024*1024) 458 goto fail; 459 460 offset = addr - sc->sc_axi_addr - PCIE_ATR_OB_REGION0_SIZE; 461 region = 1 + (offset / PCIE_ATR_OB_REGION_SIZE); 462 resid = size; 463 while (resid > 0) { 464 HWRITE4(sc, PCIE_ATR_OB_ADDR0(region), 32 - 1); 465 HWRITE4(sc, PCIE_ATR_OB_ADDR1(region), 0); 466 HWRITE4(sc, PCIE_ATR_OB_DESC0(region), type | PCIE_ATR_HDR_RID); 467 HWRITE4(sc, PCIE_ATR_OB_DESC1(region), 0); 468 469 addr += PCIE_ATR_OB_REGION_SIZE; 470 resid -= PCIE_ATR_OB_REGION_SIZE; 471 region++; 472 } 473 } 474 475 /* Passthrought inbound translations unmodified. */ 476 HWRITE4(sc, PCIE_ATR_IB_ADDR0(2), 32 - 1); 477 HWRITE4(sc, PCIE_ATR_IB_ADDR1(2), 0); 478 479 return; 480 481 fail: 482 device_printf(sc->sc_phsc.sc_dev, "can't map ranges\n"); 483 } 484 485 int 486 rkpcie_bus_maxdevs(void *v, int bus) 487 { 488 struct rkpcie_softc *rksc = v; 489 struct pcihost_softc *sc = &rksc->sc_phsc; 490 491 if (bus == sc->sc_bus_min || bus == sc->sc_bus_min + 1) 492 return 1; 493 return 32; 494 } 495 496 pcitag_t 497 rkpcie_make_tag(void *v, int bus, int device, int function) 498 { 499 /* Return ECAM address. */ 500 return ((bus << 20) | (device << 15) | (function << 12)); 501 } 502 503 void 504 rkpcie_decompose_tag(void *v, pcitag_t tag, int *bp, int *dp, int *fp) 505 { 506 if (bp != NULL) 507 *bp = (tag >> 20) & 0xff; 508 if (dp != NULL) 509 *dp = (tag >> 15) & 0x1f; 510 if (fp != NULL) 511 *fp = (tag >> 12) & 0x7; 512 } 513 514 /* Only one device on root port and the first subordinate port. */ 515 static bool 516 rkpcie_conf_ok(int bus, int dev, int fn, int bus_min) 517 { 518 if (dev != 0 && (bus == bus_min || bus == bus_min + 1)) 519 return false; 520 return true; 521 } 522 523 pcireg_t 524 rkpcie_conf_read(void *v, pcitag_t tag, int offset) 525 { 526 struct rkpcie_softc *sc = v; 527 struct pcihost_softc *phsc = &sc->sc_phsc; 528 int bus, dev, fn; 529 u_int reg; 530 531 KASSERT(offset >= 0); 532 KASSERT(offset < PCI_EXTCONF_SIZE); 533 534 rkpcie_decompose_tag(sc, tag, &bus, &dev, &fn); 535 if (!rkpcie_conf_ok(bus, dev, fn, phsc->sc_bus_min)) 536 return 0xffffffff; 537 reg = (bus << 20) | (dev << 15) | (fn << 12) | offset; 538 539 if (bus == phsc->sc_bus_min) 540 return HREAD4(sc, PCIE_RC_NORMAL_BASE + reg); 541 else 542 return AXIREAD4(sc, reg); 543 } 544 545 void 546 rkpcie_conf_write(void *v, pcitag_t tag, int offset, pcireg_t data) 547 { 548 struct rkpcie_softc *sc = v; 549 struct pcihost_softc *phsc = &sc->sc_phsc; 550 int bus, dev, fn; 551 u_int reg; 552 553 KASSERT(offset >= 0); 554 KASSERT(offset < PCI_EXTCONF_SIZE); 555 556 rkpcie_decompose_tag(sc, tag, &bus, &dev, &fn); 557 if (!rkpcie_conf_ok(bus, dev, fn, phsc->sc_bus_min)) 558 return; 559 reg = (bus << 20) | (dev << 15) | (fn << 12) | offset; 560 561 if (bus == phsc->sc_bus_min) 562 HWRITE4(sc, PCIE_RC_NORMAL_BASE + reg, data); 563 else 564 AXIWRITE4(sc, reg, data); 565 } 566 567 static int 568 rkpcie_conf_hook(void *v, int b, int d, int f, pcireg_t id) 569 { 570 return (PCI_CONF_DEFAULT & ~PCI_CONF_ENABLE_BM) | PCI_CONF_MAP_ROM; 571 } 572 573 /* INTx interrupt controller */ 574 static void * 575 rkpcie_intx_establish(device_t dev, u_int *specifier, int ipl, int flags, 576 int (*func)(void *), void *arg) 577 { 578 struct rkpcie_softc *sc = device_private(dev); 579 void *cookie; 580 581 #if notyet 582 const u_int pin = be32toh(specifier[0]); 583 #endif 584 585 /* Unmask legacy interrupts. */ 586 HWRITE4(sc, PCIE_CLIENT_INT_MASK, 587 PCIM_INTx_ENAB(0) | PCIM_INTx_ENAB(1) | 588 PCIM_INTx_ENAB(2) | PCIM_INTx_ENAB(3)); 589 590 cookie = fdtbus_intr_establish_byname(sc->sc_phsc.sc_phandle, "legacy", ipl, flags, func, arg); 591 592 return cookie; 593 } 594 595 static void 596 rkpcie_intx_disestablish(device_t dev, void *ih) 597 { 598 struct rkpcie_softc *sc = device_private(dev); 599 device_printf(dev, "%s\n", __func__); 600 fdtbus_intr_disestablish(sc->sc_phsc.sc_phandle, ih); 601 } 602 603 static bool 604 rkpcie_intx_intrstr(device_t dev, u_int *specifier, char *buf, size_t buflen) 605 { 606 struct rkpcie_softc *sc = device_private(dev); 607 608 fdtbus_intr_str(sc->sc_phsc.sc_phandle, 1, buf, buflen); 609 610 return true; 611 } 612 613 static struct fdtbus_interrupt_controller_func rkpcie_intrfuncs = { 614 .establish = rkpcie_intx_establish, 615 .disestablish = rkpcie_intx_disestablish, 616 .intrstr = rkpcie_intx_intrstr, 617 }; 618
Indexes created Thu Oct 02 10:09:58 GMT 2025