1 1.3 msaitoh /* $NetBSD: rk3588_cru.c,v 1.3 2024/02/07 04:20:27 msaitoh Exp $ */ 2 1.1 ryo 3 1.1 ryo /*- 4 1.3 msaitoh * Copyright (c) 2022 Ryo Shimizu 5 1.1 ryo * All rights reserved. 6 1.1 ryo * 7 1.1 ryo * Redistribution and use in source and binary forms, with or without 8 1.1 ryo * modification, are permitted provided that the following conditions 9 1.1 ryo * are met: 10 1.1 ryo * 1. Redistributions of source code must retain the above copyright 11 1.1 ryo * notice, this list of conditions and the following disclaimer. 12 1.1 ryo * 2. Redistributions in binary form must reproduce the above copyright 13 1.1 ryo * notice, this list of conditions and the following disclaimer in the 14 1.1 ryo * documentation and/or other materials provided with the distribution. 15 1.1 ryo * 16 1.1 ryo * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS 17 1.1 ryo * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 18 1.1 ryo * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 1.1 ryo * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 20 1.1 ryo * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 21 1.1 ryo * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 22 1.1 ryo * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 1.1 ryo * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 24 1.1 ryo * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 25 1.1 ryo * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 1.1 ryo * POSSIBILITY OF SUCH DAMAGE. 27 1.1 ryo */ 28 1.1 ryo 29 1.1 ryo #include <sys/cdefs.h> 30 1.3 msaitoh __KERNEL_RCSID(0, "$NetBSD: rk3588_cru.c,v 1.3 2024/02/07 04:20:27 msaitoh Exp $"); 31 1.1 ryo 32 1.1 ryo #include <sys/param.h> 33 1.1 ryo #include <sys/device.h> 34 1.1 ryo 35 1.1 ryo #include <dev/fdt/fdtvar.h> 36 1.1 ryo 37 1.1 ryo #include <arm/rockchip/rk_cru.h> 38 1.1 ryo #include <arm/rockchip/rk3588_cru.h> 39 1.1 ryo 40 1.1 ryo #define PLL_CON(base, n) (0x0000 + (base) + (n) * 4) 41 1.1 ryo #define MODE_CON(base, n) (0x0280 + (base) + (n) * 4) 42 1.1 ryo #define CLKSEL_CON(base, n) (0x0300 + (base) + (n) * 4) 43 1.1 ryo #define CLKGATE_CON(base, n) (0x0800 + (base) + (n) * 4) 44 1.1 ryo #define SOFTRST_CON(base, n) (0x0a00 + (base) + (n) * 4) 45 1.1 ryo /* base of above *_CON() macro */ 46 1.1 ryo #define PHP 0x00008000 47 1.1 ryo #define PMU 0x00030000 48 1.1 ryo #define BIGCORE0 0x00050000 49 1.1 ryo #define BIGCORE1 0x00052000 50 1.1 ryo #define DSU 0x00058000 51 1.1 ryo 52 1.1 ryo #define RK3588_PHYREF_ALT_GATE 0x0c38 53 1.1 ryo 54 1.1 ryo static int rk3588_cru_match(device_t, cfdata_t, void *); 55 1.1 ryo static void rk3588_cru_attach(device_t, device_t, void *); 56 1.1 ryo 57 1.1 ryo static const struct device_compatible_entry compat_data[] = { 58 1.1 ryo { .compat = "rockchip,rk3588-cru" }, 59 1.1 ryo DEVICE_COMPAT_EOL 60 1.1 ryo }; 61 1.1 ryo 62 1.1 ryo CFATTACH_DECL_NEW(rk3588_cru, sizeof(struct rk_cru_softc), 63 1.1 ryo rk3588_cru_match, rk3588_cru_attach, NULL, NULL); 64 1.1 ryo 65 1.1 ryo #define RK3588_CLK_CORE_L_SEL_MASK __BITS(6,5) 66 1.1 ryo #define RK3588_CLK_DSU_SEL_DF_MASK __BIT(15) 67 1.1 ryo #define RK3588_CLK_DSU_DF_SRC_MASK __BITS(6,5) 68 1.1 ryo #define RK3588_CLK_DSU_DF_DIV_MASK __BITS(4,0) 69 1.1 ryo #define RK3588_ACLKM_DSU_DIV_MASK __BITS(5,1) 70 1.1 ryo #define RK3588_ACLKS_DSU_DIV_MASK __BITS(10,6) 71 1.1 ryo #define RK3588_ACLKMP_DSU_DIV_MASK __BITS(15,11) 72 1.1 ryo #define RK3588_PERIPH_DSU_DIV_MASK __BITS(4,0) 73 1.1 ryo #define RK3588_ATCLK_DSU_DIV_MASK __BITS(4,0) 74 1.1 ryo #define RK3588_GICCLK_DSU_DIV_MASK __BITS(9,5) 75 1.1 ryo 76 1.1 ryo #define RK3588_CORE_L_SEL_CORE(regoff, apllcore) \ 77 1.1 ryo { \ 78 1.1 ryo .reg = CLKSEL_CON(DSU, 6 + (regoff)), \ 79 1.1 ryo .mask = RK3588_CLK_CORE_L_SEL_MASK, \ 80 1.1 ryo .val = __SHIFTIN((apllcore), RK3588_CLK_CORE_L_SEL_MASK)\ 81 1.1 ryo } 82 1.1 ryo 83 1.1 ryo #define RK3588_CORE_L_SEL_DSU(seldsu, divdsu) \ 84 1.1 ryo { \ 85 1.1 ryo .reg = CLKSEL_CON(DSU, 0), \ 86 1.1 ryo .mask = \ 87 1.1 ryo RK3588_CLK_DSU_DF_SRC_MASK | \ 88 1.1 ryo RK3588_CLK_DSU_DF_DIV_MASK | \ 89 1.1 ryo RK3588_CLK_DSU_SEL_DF_MASK, \ 90 1.1 ryo .val = \ 91 1.1 ryo __SHIFTIN((seldsu), RK3588_CLK_DSU_DF_SRC_MASK) | \ 92 1.1 ryo __SHIFTIN((divdsu) - 1, RK3588_CLK_DSU_DF_DIV_MASK) |\ 93 1.1 ryo __SHIFTIN(0, RK3588_CLK_DSU_SEL_DF_MASK) \ 94 1.1 ryo } 95 1.1 ryo 96 1.1 ryo #define RK3588_CORE_L_SEL_ACLKS(aclkm, aclkmp, aclks) \ 97 1.1 ryo { \ 98 1.1 ryo .reg = CLKSEL_CON(DSU, 1), \ 99 1.1 ryo .mask = \ 100 1.1 ryo RK3588_ACLKM_DSU_DIV_MASK | \ 101 1.1 ryo RK3588_ACLKMP_DSU_DIV_MASK | \ 102 1.1 ryo RK3588_ACLKS_DSU_DIV_MASK, \ 103 1.1 ryo .val = \ 104 1.1 ryo __SHIFTIN((aclkm) - 1, RK3588_ACLKM_DSU_DIV_MASK) | \ 105 1.1 ryo __SHIFTIN((aclkmp) - 1, RK3588_ACLKMP_DSU_DIV_MASK)|\ 106 1.1 ryo __SHIFTIN((aclks) - 1, RK3588_ACLKS_DSU_DIV_MASK) \ 107 1.1 ryo } 108 1.1 ryo 109 1.1 ryo #define RK3588_CORE_L_SEL_PERI(periph) \ 110 1.1 ryo { \ 111 1.1 ryo .reg = CLKSEL_CON(DSU, 2), \ 112 1.1 ryo .mask = RK3588_PERIPH_DSU_DIV_MASK, \ 113 1.1 ryo .val = __SHIFTIN((periph) - 1, RK3588_PERIPH_DSU_DIV_MASK)\ 114 1.1 ryo } 115 1.1 ryo 116 1.1 ryo #define RK3588_CORE_L_SEL_GIC_ATCLK(gicclk, atclk) \ 117 1.1 ryo { \ 118 1.1 ryo .reg = CLKSEL_CON(DSU, 3), \ 119 1.1 ryo .mask = \ 120 1.1 ryo RK3588_GICCLK_DSU_DIV_MASK | \ 121 1.1 ryo RK3588_ATCLK_DSU_DIV_MASK, \ 122 1.1 ryo .val = \ 123 1.1 ryo __SHIFTIN((gicclk) - 1, RK3588_GICCLK_DSU_DIV_MASK) |\ 124 1.1 ryo __SHIFTIN((atclk) - 1, RK3588_ATCLK_DSU_DIV_MASK) \ 125 1.1 ryo } 126 1.1 ryo 127 1.1 ryo #define RK3588_ARMCLK_L_RATE(targetrate, apllcore, seldsu, divdsu, \ 128 1.1 ryo atclk, gicclk, aclkmp, aclkm, aclks, periph) \ 129 1.1 ryo { \ 130 1.1 ryo .rate = (targetrate), \ 131 1.1 ryo .divs = { \ 132 1.1 ryo RK3588_CORE_L_SEL_DSU((seldsu), (divdsu)), \ 133 1.1 ryo RK3588_CORE_L_SEL_ACLKS((aclkm), (aclkmp), (aclks)),\ 134 1.1 ryo RK3588_CORE_L_SEL_PERI((periph)), \ 135 1.1 ryo RK3588_CORE_L_SEL_GIC_ATCLK((gicclk), (atclk)), \ 136 1.1 ryo }, \ 137 1.1 ryo .pre_muxs = { \ 138 1.1 ryo RK3588_CORE_L_SEL_CORE(0, 0), \ 139 1.1 ryo RK3588_CORE_L_SEL_CORE(1, 0), \ 140 1.1 ryo RK3588_CORE_L_SEL_DSU(3, 2), \ 141 1.1 ryo }, \ 142 1.1 ryo .post_muxs = { \ 143 1.1 ryo RK3588_CORE_L_SEL_CORE(0, (apllcore)), \ 144 1.1 ryo RK3588_CORE_L_SEL_CORE(1, (apllcore)), \ 145 1.1 ryo RK3588_CORE_L_SEL_DSU((seldsu), (divdsu)) \ 146 1.1 ryo }, \ 147 1.1 ryo } 148 1.1 ryo 149 1.1 ryo static const struct rk_cru_cpu_rate armclk_l_rates[] = { 150 1.1 ryo RK3588_ARMCLK_L_RATE(2208000000, 1, 3, 1, 4, 4, 4, 4, 4, 4), 151 1.1 ryo RK3588_ARMCLK_L_RATE(2184000000, 1, 3, 1, 4, 4, 4, 4, 4, 4), 152 1.1 ryo RK3588_ARMCLK_L_RATE(2088000000, 1, 3, 1, 4, 4, 4, 4, 4, 4), 153 1.1 ryo RK3588_ARMCLK_L_RATE(2040000000, 1, 3, 1, 4, 4, 4, 4, 4, 4), 154 1.1 ryo RK3588_ARMCLK_L_RATE(2016000000, 1, 3, 1, 4, 4, 4, 4, 4, 4), 155 1.1 ryo RK3588_ARMCLK_L_RATE(1992000000, 1, 3, 1, 4, 4, 4, 4, 4, 4), 156 1.1 ryo RK3588_ARMCLK_L_RATE(1896000000, 1, 3, 1, 4, 4, 4, 4, 4, 4), 157 1.1 ryo RK3588_ARMCLK_L_RATE(1800000000, 1, 3, 1, 4, 4, 4, 4, 4, 4), 158 1.1 ryo RK3588_ARMCLK_L_RATE(1704000000, 0, 3, 1, 3, 3, 3, 3, 3, 3), 159 1.1 ryo RK3588_ARMCLK_L_RATE(1608000000, 0, 3, 1, 3, 3, 3, 2, 3, 3), 160 1.1 ryo RK3588_ARMCLK_L_RATE(1584000000, 0, 3, 1, 3, 3, 3, 2, 3, 3), 161 1.1 ryo RK3588_ARMCLK_L_RATE(1560000000, 0, 2, 2, 3, 3, 3, 2, 3, 3), 162 1.1 ryo RK3588_ARMCLK_L_RATE(1536000000, 0, 2, 2, 3, 3, 3, 2, 3, 3), 163 1.1 ryo RK3588_ARMCLK_L_RATE(1512000000, 0, 2, 2, 3, 3, 3, 2, 3, 3), 164 1.1 ryo RK3588_ARMCLK_L_RATE(1488000000, 0, 2, 2, 3, 3, 3, 2, 3, 3), 165 1.1 ryo RK3588_ARMCLK_L_RATE(1464000000, 0, 2, 2, 3, 3, 3, 2, 3, 3), 166 1.1 ryo RK3588_ARMCLK_L_RATE(1440000000, 0, 2, 2, 3, 3, 3, 2, 3, 3), 167 1.1 ryo RK3588_ARMCLK_L_RATE(1416000000, 0, 2, 2, 3, 3, 3, 2, 3, 3), 168 1.1 ryo RK3588_ARMCLK_L_RATE(1392000000, 0, 2, 2, 3, 3, 3, 2, 3, 3), 169 1.1 ryo RK3588_ARMCLK_L_RATE(1368000000, 0, 2, 2, 3, 3, 3, 2, 3, 3), 170 1.1 ryo RK3588_ARMCLK_L_RATE(1344000000, 0, 2, 2, 3, 3, 3, 2, 3, 3), 171 1.1 ryo RK3588_ARMCLK_L_RATE(1320000000, 0, 2, 2, 3, 3, 3, 2, 3, 3), 172 1.1 ryo RK3588_ARMCLK_L_RATE(1296000000, 0, 2, 2, 3, 3, 3, 2, 3, 3), 173 1.1 ryo RK3588_ARMCLK_L_RATE(1272000000, 0, 2, 2, 2, 2, 2, 2, 2, 2), 174 1.1 ryo RK3588_ARMCLK_L_RATE(1248000000, 0, 2, 2, 2, 2, 2, 2, 2, 2), 175 1.1 ryo RK3588_ARMCLK_L_RATE(1224000000, 0, 2, 2, 2, 2, 2, 2, 2, 2), 176 1.1 ryo RK3588_ARMCLK_L_RATE(1200000000, 0, 2, 2, 2, 2, 2, 2, 2, 2), 177 1.1 ryo RK3588_ARMCLK_L_RATE(1104000000, 0, 2, 2, 2, 2, 2, 2, 2, 2), 178 1.1 ryo RK3588_ARMCLK_L_RATE(1008000000, 0, 2, 2, 2, 2, 2, 2, 2, 2), 179 1.1 ryo RK3588_ARMCLK_L_RATE( 912000000, 0, 2, 2, 2, 2, 2, 1, 2, 2), 180 1.1 ryo RK3588_ARMCLK_L_RATE( 816000000, 0, 2, 2, 2, 2, 2, 1, 2, 2), 181 1.1 ryo RK3588_ARMCLK_L_RATE( 696000000, 0, 2, 2, 2, 2, 2, 1, 2, 2), 182 1.1 ryo RK3588_ARMCLK_L_RATE( 600000000, 0, 2, 1, 1, 1, 1, 1, 1, 1), 183 1.1 ryo RK3588_ARMCLK_L_RATE( 408000000, 0, 2, 1, 1, 1, 1, 1, 1, 1), 184 1.1 ryo RK3588_ARMCLK_L_RATE( 312000000, 0, 2, 1, 1, 1, 1, 1, 1, 1), 185 1.1 ryo RK3588_ARMCLK_L_RATE( 216000000, 0, 2, 1, 1, 1, 1, 1, 1, 1), 186 1.1 ryo RK3588_ARMCLK_L_RATE( 96000000, 0, 2, 1, 1, 1, 1, 1, 1, 1), 187 1.1 ryo }; 188 1.1 ryo 189 1.1 ryo #define RK3588_CLK_CORE_B_SEL_MASK __BITS(14,13) 190 1.1 ryo #define RK3588_CLK_CORE_B_GPLL_DIV_MASK __BITS(5,1) 191 1.1 ryo 192 1.1 ryo #define RK3588_ARMCLK_B_RATE(_rate, _bigcore, _apllcore) \ 193 1.1 ryo { \ 194 1.1 ryo .rate = (_rate), \ 195 1.1 ryo .divs[0] = { \ 196 1.1 ryo .reg = CLKSEL_CON(_bigcore, 0), \ 197 1.1 ryo .mask = RK3588_CLK_CORE_B_SEL_MASK | \ 198 1.1 ryo RK3588_CLK_CORE_B_GPLL_DIV_MASK, \ 199 1.1 ryo .val = __SHIFTIN((_apllcore), \ 200 1.1 ryo RK3588_CLK_CORE_B_SEL_MASK) | \ 201 1.1 ryo __SHIFTIN(0, \ 202 1.1 ryo RK3588_CLK_CORE_B_GPLL_DIV_MASK) \ 203 1.1 ryo }, \ 204 1.1 ryo .divs[1] = { \ 205 1.1 ryo .reg = CLKSEL_CON(_bigcore, 1), \ 206 1.1 ryo .mask = RK3588_CLK_CORE_B_SEL_MASK, \ 207 1.1 ryo .val = __SHIFTIN((_apllcore), \ 208 1.1 ryo RK3588_CLK_CORE_B_SEL_MASK) \ 209 1.1 ryo } \ 210 1.1 ryo } 211 1.1 ryo 212 1.1 ryo static const struct rk_cru_cpu_rate armclk_b01_rates[] = { 213 1.1 ryo RK3588_ARMCLK_B_RATE(2496000000, BIGCORE0, 1), 214 1.1 ryo RK3588_ARMCLK_B_RATE(2400000000, BIGCORE0, 1), 215 1.1 ryo RK3588_ARMCLK_B_RATE(2304000000, BIGCORE0, 1), 216 1.1 ryo RK3588_ARMCLK_B_RATE(2208000000, BIGCORE0, 1), 217 1.1 ryo RK3588_ARMCLK_B_RATE(2184000000, BIGCORE0, 1), 218 1.1 ryo RK3588_ARMCLK_B_RATE(2088000000, BIGCORE0, 1), 219 1.1 ryo RK3588_ARMCLK_B_RATE(2040000000, BIGCORE0, 1), 220 1.1 ryo RK3588_ARMCLK_B_RATE(2016000000, BIGCORE0, 1), 221 1.1 ryo RK3588_ARMCLK_B_RATE(1992000000, BIGCORE0, 1), 222 1.1 ryo RK3588_ARMCLK_B_RATE(1896000000, BIGCORE0, 1), 223 1.1 ryo RK3588_ARMCLK_B_RATE(1800000000, BIGCORE0, 1), 224 1.1 ryo RK3588_ARMCLK_B_RATE(1704000000, BIGCORE0, 0), 225 1.1 ryo RK3588_ARMCLK_B_RATE(1608000000, BIGCORE0, 0), 226 1.1 ryo RK3588_ARMCLK_B_RATE(1584000000, BIGCORE0, 0), 227 1.1 ryo RK3588_ARMCLK_B_RATE(1560000000, BIGCORE0, 0), 228 1.1 ryo RK3588_ARMCLK_B_RATE(1536000000, BIGCORE0, 0), 229 1.1 ryo RK3588_ARMCLK_B_RATE(1512000000, BIGCORE0, 0), 230 1.1 ryo RK3588_ARMCLK_B_RATE(1488000000, BIGCORE0, 0), 231 1.1 ryo RK3588_ARMCLK_B_RATE(1464000000, BIGCORE0, 0), 232 1.1 ryo RK3588_ARMCLK_B_RATE(1440000000, BIGCORE0, 0), 233 1.1 ryo RK3588_ARMCLK_B_RATE(1416000000, BIGCORE0, 0), 234 1.1 ryo RK3588_ARMCLK_B_RATE(1392000000, BIGCORE0, 0), 235 1.1 ryo RK3588_ARMCLK_B_RATE(1368000000, BIGCORE0, 0), 236 1.1 ryo RK3588_ARMCLK_B_RATE(1344000000, BIGCORE0, 0), 237 1.1 ryo RK3588_ARMCLK_B_RATE(1320000000, BIGCORE0, 0), 238 1.1 ryo RK3588_ARMCLK_B_RATE(1296000000, BIGCORE0, 0), 239 1.1 ryo RK3588_ARMCLK_B_RATE(1272000000, BIGCORE0, 0), 240 1.1 ryo RK3588_ARMCLK_B_RATE(1248000000, BIGCORE0, 0), 241 1.1 ryo RK3588_ARMCLK_B_RATE(1224000000, BIGCORE0, 0), 242 1.1 ryo RK3588_ARMCLK_B_RATE(1200000000, BIGCORE0, 0), 243 1.1 ryo RK3588_ARMCLK_B_RATE(1104000000, BIGCORE0, 0), 244 1.1 ryo RK3588_ARMCLK_B_RATE(1008000000, BIGCORE0, 0), 245 1.1 ryo RK3588_ARMCLK_B_RATE( 912000000, BIGCORE0, 0), 246 1.1 ryo RK3588_ARMCLK_B_RATE( 816000000, BIGCORE0, 0), 247 1.1 ryo RK3588_ARMCLK_B_RATE( 696000000, BIGCORE0, 0), 248 1.1 ryo RK3588_ARMCLK_B_RATE( 600000000, BIGCORE0, 0), 249 1.1 ryo RK3588_ARMCLK_B_RATE( 408000000, BIGCORE0, 0), 250 1.1 ryo RK3588_ARMCLK_B_RATE( 312000000, BIGCORE0, 0), 251 1.1 ryo RK3588_ARMCLK_B_RATE( 216000000, BIGCORE0, 0), 252 1.1 ryo RK3588_ARMCLK_B_RATE( 96000000, BIGCORE0, 0), 253 1.1 ryo }; 254 1.1 ryo 255 1.1 ryo static const struct rk_cru_cpu_rate armclk_b23_rates[] = { 256 1.1 ryo RK3588_ARMCLK_B_RATE(2496000000, BIGCORE1, 1), 257 1.1 ryo RK3588_ARMCLK_B_RATE(2400000000, BIGCORE1, 1), 258 1.1 ryo RK3588_ARMCLK_B_RATE(2304000000, BIGCORE1, 1), 259 1.1 ryo RK3588_ARMCLK_B_RATE(2208000000, BIGCORE1, 1), 260 1.1 ryo RK3588_ARMCLK_B_RATE(2184000000, BIGCORE1, 1), 261 1.1 ryo RK3588_ARMCLK_B_RATE(2088000000, BIGCORE1, 1), 262 1.1 ryo RK3588_ARMCLK_B_RATE(2040000000, BIGCORE1, 1), 263 1.1 ryo RK3588_ARMCLK_B_RATE(2016000000, BIGCORE1, 1), 264 1.1 ryo RK3588_ARMCLK_B_RATE(1992000000, BIGCORE1, 1), 265 1.1 ryo RK3588_ARMCLK_B_RATE(1896000000, BIGCORE1, 1), 266 1.1 ryo RK3588_ARMCLK_B_RATE(1800000000, BIGCORE1, 1), 267 1.1 ryo RK3588_ARMCLK_B_RATE(1704000000, BIGCORE1, 0), 268 1.1 ryo RK3588_ARMCLK_B_RATE(1608000000, BIGCORE1, 0), 269 1.1 ryo RK3588_ARMCLK_B_RATE(1584000000, BIGCORE1, 0), 270 1.1 ryo RK3588_ARMCLK_B_RATE(1560000000, BIGCORE1, 0), 271 1.1 ryo RK3588_ARMCLK_B_RATE(1536000000, BIGCORE1, 0), 272 1.1 ryo RK3588_ARMCLK_B_RATE(1512000000, BIGCORE1, 0), 273 1.1 ryo RK3588_ARMCLK_B_RATE(1488000000, BIGCORE1, 0), 274 1.1 ryo RK3588_ARMCLK_B_RATE(1464000000, BIGCORE1, 0), 275 1.1 ryo RK3588_ARMCLK_B_RATE(1440000000, BIGCORE1, 0), 276 1.1 ryo RK3588_ARMCLK_B_RATE(1416000000, BIGCORE1, 0), 277 1.1 ryo RK3588_ARMCLK_B_RATE(1392000000, BIGCORE1, 0), 278 1.1 ryo RK3588_ARMCLK_B_RATE(1368000000, BIGCORE1, 0), 279 1.1 ryo RK3588_ARMCLK_B_RATE(1344000000, BIGCORE1, 0), 280 1.1 ryo RK3588_ARMCLK_B_RATE(1320000000, BIGCORE1, 0), 281 1.1 ryo RK3588_ARMCLK_B_RATE(1296000000, BIGCORE1, 0), 282 1.1 ryo RK3588_ARMCLK_B_RATE(1272000000, BIGCORE1, 0), 283 1.1 ryo RK3588_ARMCLK_B_RATE(1248000000, BIGCORE1, 0), 284 1.1 ryo RK3588_ARMCLK_B_RATE(1224000000, BIGCORE1, 0), 285 1.1 ryo RK3588_ARMCLK_B_RATE(1200000000, BIGCORE1, 0), 286 1.1 ryo RK3588_ARMCLK_B_RATE(1104000000, BIGCORE1, 0), 287 1.1 ryo RK3588_ARMCLK_B_RATE(1008000000, BIGCORE1, 0), 288 1.1 ryo RK3588_ARMCLK_B_RATE( 912000000, BIGCORE1, 0), 289 1.1 ryo RK3588_ARMCLK_B_RATE( 816000000, BIGCORE1, 0), 290 1.1 ryo RK3588_ARMCLK_B_RATE( 696000000, BIGCORE1, 0), 291 1.1 ryo RK3588_ARMCLK_B_RATE( 600000000, BIGCORE1, 0), 292 1.1 ryo RK3588_ARMCLK_B_RATE( 408000000, BIGCORE1, 0), 293 1.1 ryo RK3588_ARMCLK_B_RATE( 312000000, BIGCORE1, 0), 294 1.1 ryo RK3588_ARMCLK_B_RATE( 216000000, BIGCORE1, 0), 295 1.1 ryo RK3588_ARMCLK_B_RATE( 96000000, BIGCORE1, 0), 296 1.1 ryo }; 297 1.1 ryo 298 1.1 ryo static struct rk_cru_pll_rate rk3588_pll_rates[] = { 299 1.1 ryo RK3588_PLL_RATE(2520000000, 2, 210, 0, 0), 300 1.1 ryo RK3588_PLL_RATE(2496000000, 2, 208, 0, 0), 301 1.1 ryo RK3588_PLL_RATE(2472000000, 2, 206, 0, 0), 302 1.1 ryo RK3588_PLL_RATE(2448000000, 2, 204, 0, 0), 303 1.1 ryo RK3588_PLL_RATE(2424000000, 2, 202, 0, 0), 304 1.1 ryo RK3588_PLL_RATE(2400000000, 2, 200, 0, 0), 305 1.1 ryo RK3588_PLL_RATE(2376000000, 2, 198, 0, 0), 306 1.1 ryo RK3588_PLL_RATE(2352000000, 2, 196, 0, 0), 307 1.1 ryo RK3588_PLL_RATE(2328000000, 2, 194, 0, 0), 308 1.1 ryo RK3588_PLL_RATE(2304000000, 2, 192, 0, 0), 309 1.1 ryo RK3588_PLL_RATE(2280000000, 2, 190, 0, 0), 310 1.1 ryo RK3588_PLL_RATE(2256000000, 2, 376, 1, 0), 311 1.1 ryo RK3588_PLL_RATE(2232000000, 2, 372, 1, 0), 312 1.1 ryo RK3588_PLL_RATE(2208000000, 2, 368, 1, 0), 313 1.1 ryo RK3588_PLL_RATE(2184000000, 2, 364, 1, 0), 314 1.1 ryo RK3588_PLL_RATE(2160000000, 2, 360, 1, 0), 315 1.1 ryo RK3588_PLL_RATE(2136000000, 2, 356, 1, 0), 316 1.1 ryo RK3588_PLL_RATE(2112000000, 2, 352, 1, 0), 317 1.1 ryo RK3588_PLL_RATE(2088000000, 2, 348, 1, 0), 318 1.1 ryo RK3588_PLL_RATE(2064000000, 2, 344, 1, 0), 319 1.1 ryo RK3588_PLL_RATE(2040000000, 2, 340, 1, 0), 320 1.1 ryo RK3588_PLL_RATE(2016000000, 2, 336, 1, 0), 321 1.1 ryo RK3588_PLL_RATE(1992000000, 2, 332, 1, 0), 322 1.1 ryo RK3588_PLL_RATE(1968000000, 2, 328, 1, 0), 323 1.1 ryo RK3588_PLL_RATE(1944000000, 2, 324, 1, 0), 324 1.1 ryo RK3588_PLL_RATE(1920000000, 2, 320, 1, 0), 325 1.1 ryo RK3588_PLL_RATE(1896000000, 2, 316, 1, 0), 326 1.1 ryo RK3588_PLL_RATE(1872000000, 2, 312, 1, 0), 327 1.1 ryo RK3588_PLL_RATE(1848000000, 2, 308, 1, 0), 328 1.1 ryo RK3588_PLL_RATE(1824000000, 2, 304, 1, 0), 329 1.1 ryo RK3588_PLL_RATE(1800000000, 2, 300, 1, 0), 330 1.1 ryo RK3588_PLL_RATE(1776000000, 2, 296, 1, 0), 331 1.1 ryo RK3588_PLL_RATE(1752000000, 2, 292, 1, 0), 332 1.1 ryo RK3588_PLL_RATE(1728000000, 2, 288, 1, 0), 333 1.1 ryo RK3588_PLL_RATE(1704000000, 2, 284, 1, 0), 334 1.1 ryo RK3588_PLL_RATE(1680000000, 2, 280, 1, 0), 335 1.1 ryo RK3588_PLL_RATE(1656000000, 2, 276, 1, 0), 336 1.1 ryo RK3588_PLL_RATE(1632000000, 2, 272, 1, 0), 337 1.1 ryo RK3588_PLL_RATE(1608000000, 2, 268, 1, 0), 338 1.1 ryo RK3588_PLL_RATE(1584000000, 2, 264, 1, 0), 339 1.1 ryo RK3588_PLL_RATE(1560000000, 2, 260, 1, 0), 340 1.1 ryo RK3588_PLL_RATE(1536000000, 2, 256, 1, 0), 341 1.1 ryo RK3588_PLL_RATE(1512000000, 2, 252, 1, 0), 342 1.1 ryo RK3588_PLL_RATE(1488000000, 2, 248, 1, 0), 343 1.1 ryo RK3588_PLL_RATE(1464000000, 2, 244, 1, 0), 344 1.1 ryo RK3588_PLL_RATE(1440000000, 2, 240, 1, 0), 345 1.1 ryo RK3588_PLL_RATE(1416000000, 2, 236, 1, 0), 346 1.1 ryo RK3588_PLL_RATE(1392000000, 2, 232, 1, 0), 347 1.1 ryo RK3588_PLL_RATE(1320000000, 2, 220, 1, 0), 348 1.1 ryo RK3588_PLL_RATE(1200000000, 2, 200, 1, 0), 349 1.1 ryo RK3588_PLL_RATE(1188000000, 2, 198, 1, 0), 350 1.1 ryo RK3588_PLL_RATE(1100000000, 3, 550, 2, 0), 351 1.1 ryo RK3588_PLL_RATE(1008000000, 2, 336, 2, 0), 352 1.1 ryo RK3588_PLL_RATE(1000000000, 3, 500, 2, 0), 353 1.1 ryo RK3588_PLL_RATE( 983040000, 4, 655, 2, 23592), 354 1.1 ryo RK3588_PLL_RATE( 955520000, 3, 477, 2, 49806), 355 1.1 ryo RK3588_PLL_RATE( 903168000, 6, 903, 2, 11009), 356 1.1 ryo RK3588_PLL_RATE( 900000000, 2, 300, 2, 0), 357 1.1 ryo RK3588_PLL_RATE( 850000000, 3, 425, 2, 0), 358 1.1 ryo RK3588_PLL_RATE( 816000000, 2, 272, 2, 0), 359 1.1 ryo RK3588_PLL_RATE( 786432000, 2, 262, 2, 9437), 360 1.1 ryo RK3588_PLL_RATE( 786000000, 1, 131, 2, 0), 361 1.1 ryo RK3588_PLL_RATE( 785560000, 3, 392, 2, 51117), 362 1.1 ryo RK3588_PLL_RATE( 722534400, 8, 963, 2, 24850), 363 1.1 ryo RK3588_PLL_RATE( 600000000, 2, 200, 2, 0), 364 1.1 ryo RK3588_PLL_RATE( 594000000, 2, 198, 2, 0), 365 1.1 ryo RK3588_PLL_RATE( 408000000, 2, 272, 3, 0), 366 1.1 ryo RK3588_PLL_RATE( 312000000, 2, 208, 3, 0), 367 1.1 ryo RK3588_PLL_RATE( 216000000, 2, 288, 4, 0), 368 1.1 ryo RK3588_PLL_RATE( 100000000, 3, 400, 5, 0), 369 1.1 ryo RK3588_PLL_RATE( 96000000, 2, 256, 5, 0), 370 1.1 ryo }; 371 1.1 ryo 372 1.1 ryo static const char *mux_pll_parents[] = { 373 1.1 ryo "xin24m", "xin32k" }; 374 1.1 ryo static const char *mux_armclkl_parents[] = { 375 1.1 ryo "xin24m", "gpll", "lpll" }; 376 1.1 ryo static const char *mux_armclkb01_parents[] = { 377 1.1 ryo "xin24m", "gpll", "b0pll" }; 378 1.1 ryo static const char *mux_armclkb23_parents[] = { 379 1.1 ryo "xin24m", "gpll", "b1pll" }; 380 1.1 ryo static const char *b0pll_b1pll_lpll_gpll_parents[]= { 381 1.1 ryo "b0pll", "b1pll", "lpll", "gpll" }; 382 1.1 ryo static const char *gpll_24m_parents[] = { 383 1.1 ryo "gpll", "xin24m" }; 384 1.1 ryo static const char *gpll_aupll_parents[] = { 385 1.1 ryo "gpll", "aupll" }; 386 1.1 ryo static const char *gpll_lpll_parents[] = { 387 1.1 ryo "gpll", "lpll" }; 388 1.1 ryo static const char *gpll_cpll_parents[] = { 389 1.1 ryo "gpll", "cpll" }; 390 1.1 ryo static const char *gpll_spll_parents[] = { 391 1.1 ryo "gpll", "spll" }; 392 1.1 ryo static const char *gpll_cpll_24m_parents[] = { 393 1.1 ryo "gpll", "cpll", "xin24m"}; 394 1.1 ryo static const char *gpll_cpll_aupll_parents[] = { 395 1.1 ryo "gpll", "cpll", "aupll"}; 396 1.1 ryo static const char *gpll_cpll_npll_parents[] = { 397 1.1 ryo "gpll", "cpll", "npll"}; 398 1.1 ryo static const char *gpll_cpll_npll_v0pll_parents[]= { 399 1.1 ryo "gpll", "cpll", "npll", "v0pll"}; 400 1.1 ryo static const char *gpll_cpll_24m_spll_parents[] = { 401 1.1 ryo "gpll", "cpll", "xin24m", "spll" }; 402 1.1 ryo static const char *gpll_cpll_aupll_spll_parents[]= { 403 1.1 ryo "gpll", "cpll", "aupll", "spll" }; 404 1.1 ryo static const char *gpll_cpll_aupll_npll_parents[]= { 405 1.1 ryo "gpll", "cpll", "aupll", "npll" }; 406 1.1 ryo static const char *gpll_cpll_v0pll_aupll_parents[]= { 407 1.1 ryo "gpll", "cpll", "v0pll", "aupll" }; 408 1.1 ryo static const char *gpll_cpll_v0pll_spll_parents[]= { 409 1.1 ryo "gpll", "cpll", "v0pll", "spll" }; 410 1.1 ryo static const char *gpll_cpll_aupll_npll_spll_parents[]= { 411 1.1 ryo "gpll", "cpll", "aupll", "npll", "spll" }; 412 1.1 ryo static const char *gpll_cpll_npll_aupll_spll_parents[]= { 413 1.1 ryo "gpll", "cpll", "npll", "aupll", "spll" }; 414 1.1 ryo static const char *gpll_cpll_dmyaupll_npll_spll_parents[] = 415 1.1 ryo { "gpll", "cpll", "dummy_aupll", "npll", "spll" }; 416 1.1 ryo static const char *gpll_cpll_npll_1000m_parents[]= { 417 1.1 ryo "gpll", "cpll", "npll", "clk_1000m_src" }; 418 1.1 ryo static const char *mux_24m_spll_gpll_cpll_parents[]= { 419 1.1 ryo "xin24m", "spll", "gpll", "cpll" }; 420 1.1 ryo static const char *mux_24m_32k_parents[] = { 421 1.1 ryo "xin24m", "xin32k" }; 422 1.1 ryo static const char *mux_24m_100m_parents[] = { 423 1.1 ryo "xin24m", "clk_100m_src" }; 424 1.1 ryo static const char *mux_200m_100m_parents[] = { 425 1.1 ryo "clk_200m_src", "clk_100m_src" }; 426 1.1 ryo static const char *mux_100m_50m_24m_parents[] = { 427 1.1 ryo "clk_100m_src", "clk_50m_src", "xin24m" }; 428 1.1 ryo static const char *mux_150m_50m_24m_parents[] = { 429 1.1 ryo "clk_150m_src", "clk_50m_src", "xin24m" }; 430 1.1 ryo static const char *mux_150m_100m_24m_parents[] = { 431 1.1 ryo "clk_150m_src", "clk_100m_src", "xin24m" }; 432 1.1 ryo static const char *mux_200m_150m_24m_parents[] = { 433 1.1 ryo "clk_200m_src", "clk_150m_src", "xin24m" }; 434 1.1 ryo static const char *mux_150m_100m_50m_24m_parents[]= { 435 1.1 ryo "clk_150m_src", "clk_100m_src", "clk_50m_src", "xin24m" }; 436 1.1 ryo static const char *mux_200m_100m_50m_24m_parents[]= { 437 1.1 ryo "clk_200m_src", "clk_100m_src", "clk_50m_src", "xin24m" }; 438 1.1 ryo static const char *mux_300m_200m_100m_24m_parents[]= { 439 1.1 ryo "clk_300m_src", "clk_200m_src", "clk_100m_src", "xin24m" }; 440 1.1 ryo static const char *mux_700m_400m_200m_24m_parents[]= { 441 1.1 ryo "clk_700m_src", "clk_400m_src", "clk_200m_src", "xin_osc0_func" }; 442 1.1 ryo static const char *mux_500m_250m_100m_24m_parents[]= { 443 1.1 ryo "clk_500m_src", "clk_250m_src", "clk_100m_src", "xin_osc0_func" }; 444 1.1 ryo static const char *mux_500m_300m_100m_24m_parents[]= { 445 1.1 ryo "clk_500m_src", "clk_300m_src", "clk_100m_src", "xin_osc0_func" }; 446 1.1 ryo static const char *mux_400m_200m_100m_24m_parents[]= { 447 1.1 ryo "clk_400m_src", "clk_200m_src", "clk_100m_src", "xin_osc0_func" }; 448 1.1 ryo static const char *clk_i2s2_2ch_parents[] = { 449 1.1 ryo "clk_i2s2_2ch_src", "clk_i2s2_2ch_frac", "i2s2_mclkin", "xin12m" }; 450 1.1 ryo static const char *clk_i2s3_2ch_parents[] = { 451 1.1 ryo "clk_i2s3_2ch_src", "clk_i2s3_2ch_frac", "i2s3_mclkin", "xin12m" }; 452 1.1 ryo static const char *clk_i2s0_8ch_tx_parents[] = { 453 1.1 ryo "clk_i2s0_8ch_tx_src", "clk_i2s0_8ch_tx_frac", "i2s0_mclkin", "xin12m" }; 454 1.1 ryo static const char *clk_i2s0_8ch_rx_parents[] = { 455 1.1 ryo "clk_i2s0_8ch_rx_src", "clk_i2s0_8ch_rx_frac", "i2s0_mclkin", "xin12m" }; 456 1.1 ryo static const char *clk_i2s1_8ch_tx_parents[] = { 457 1.1 ryo "clk_i2s1_8ch_tx_src", "clk_i2s1_8ch_tx_frac", "i2s1_mclkin", "xin12m" }; 458 1.1 ryo static const char *clk_i2s1_8ch_rx_parents[] = { 459 1.1 ryo "clk_i2s1_8ch_rx_src", "clk_i2s1_8ch_rx_frac", "i2s1_mclkin", "xin12m" }; 460 1.1 ryo static const char *clk_i2s4_8ch_tx_parents[] = { 461 1.1 ryo "clk_i2s4_8ch_tx_src", "clk_i2s4_8ch_tx_frac", "i2s4_mclkin", "xin12m" }; 462 1.1 ryo static const char *clk_i2s5_8ch_tx_parents[] = { 463 1.1 ryo "clk_i2s5_8ch_tx_src", "clk_i2s5_8ch_tx_frac", "i2s5_mclkin", "xin12m" }; 464 1.1 ryo static const char *clk_i2s6_8ch_tx_parents[] = { 465 1.1 ryo "clk_i2s6_8ch_tx_src", "clk_i2s6_8ch_tx_frac", "i2s6_mclkin", "xin12m" }; 466 1.1 ryo static const char *clk_i2s6_8ch_rx_parents[] = { 467 1.1 ryo "clk_i2s6_8ch_rx_src", "clk_i2s6_8ch_rx_frac", "i2s6_mclkin", "xin12m" }; 468 1.1 ryo static const char *clk_i2s7_8ch_rx_parents[] = { 469 1.1 ryo "clk_i2s7_8ch_rx_src", "clk_i2s7_8ch_rx_frac", "i2s7_mclkin", "xin12m" }; 470 1.1 ryo static const char *clk_i2s8_8ch_tx_parents[] = { 471 1.1 ryo "clk_i2s8_8ch_tx_src", "clk_i2s8_8ch_tx_frac", "i2s8_mclkin", "xin12m" }; 472 1.1 ryo static const char *clk_i2s9_8ch_rx_parents[] = { 473 1.1 ryo "clk_i2s9_8ch_rx_src", "clk_i2s9_8ch_rx_frac", "i2s9_mclkin", "xin12m" }; 474 1.1 ryo static const char *clk_i2s10_8ch_rx_parents[] = { 475 1.1 ryo "clk_i2s10_8ch_rx_src", "clk_i2s10_8ch_rx_frac", "i2s10_mclkin", "xin12m" }; 476 1.1 ryo static const char *clk_spdif0_parents[] = { 477 1.1 ryo "clk_spdif0_src", "clk_spdif0_frac", "xin12m" }; 478 1.1 ryo static const char *clk_spdif1_parents[] = { 479 1.1 ryo "clk_spdif1_src", "clk_spdif1_frac", "xin12m" }; 480 1.1 ryo static const char *clk_spdif2_dp0_parents[] = { 481 1.1 ryo "clk_spdif2_dp0_src", "clk_spdif2_dp0_frac", "xin12m" }; 482 1.1 ryo static const char *clk_spdif3_parents[] = { 483 1.1 ryo "clk_spdif3_src", "clk_spdif3_frac", "xin12m" }; 484 1.1 ryo static const char *clk_spdif4_parents[] = { 485 1.1 ryo "clk_spdif4_src", "clk_spdif4_frac", "xin12m" }; 486 1.1 ryo static const char *clk_spdif5_dp1_parents[] = { 487 1.1 ryo "clk_spdif5_dp1_src", "clk_spdif5_dp1_frac", "xin12m" }; 488 1.1 ryo static const char *clk_uart0_parents[] = { 489 1.1 ryo "clk_uart0_src", "clk_uart0_frac", "xin24m" }; 490 1.1 ryo static const char *clk_uart1_parents[] = { 491 1.1 ryo "clk_uart1_src", "clk_uart1_frac", "xin24m" }; 492 1.1 ryo static const char *clk_uart2_parents[] = { 493 1.1 ryo "clk_uart2_src", "clk_uart2_frac", "xin24m" }; 494 1.1 ryo static const char *clk_uart3_parents[] = { 495 1.1 ryo "clk_uart3_src", "clk_uart3_frac", "xin24m" }; 496 1.1 ryo static const char *clk_uart4_parents[] = { 497 1.1 ryo "clk_uart4_src", "clk_uart4_frac", "xin24m" }; 498 1.1 ryo static const char *clk_uart5_parents[] = { 499 1.1 ryo "clk_uart5_src", "clk_uart5_frac", "xin24m" }; 500 1.1 ryo static const char *clk_uart6_parents[] = { 501 1.1 ryo "clk_uart6_src", "clk_uart6_frac", "xin24m" }; 502 1.1 ryo static const char *clk_uart7_parents[] = { 503 1.1 ryo "clk_uart7_src", "clk_uart7_frac", "xin24m" }; 504 1.1 ryo static const char *clk_uart8_parents[] = { 505 1.1 ryo "clk_uart8_src", "clk_uart8_frac", "xin24m" }; 506 1.1 ryo static const char *clk_uart9_parents[] = { 507 1.1 ryo "clk_uart9_src", "clk_uart9_frac", "xin24m" }; 508 1.1 ryo static const char *clk_gmac0_ptp_ref_parents[] = { 509 1.1 ryo "cpll", "clk_gmac0_ptpref_io" }; 510 1.1 ryo static const char *clk_gmac1_ptp_ref_parents[] = { 511 1.1 ryo "cpll", "clk_gmac1_ptpref_io" }; 512 1.1 ryo static const char *aclk_hdcp1_root_parents[] = { 513 1.1 ryo "gpll", "cpll", "clk_hdmitrx_refsrc" }; 514 1.1 ryo static const char *dclk_vop0_parents[] = { 515 1.1 ryo "dclk_vop0_src", "clk_hdmiphy_pixel0", "clk_hdmiphy_pixel1" }; 516 1.1 ryo static const char *dclk_vop1_parents[] = { 517 1.1 ryo "dclk_vop1_src", "clk_hdmiphy_pixel0", "clk_hdmiphy_pixel1" }; 518 1.1 ryo static const char *dclk_vop2_parents[] = { 519 1.1 ryo "dclk_vop2_src", "clk_hdmiphy_pixel0", "clk_hdmiphy_pixel1" }; 520 1.1 ryo static const char *pmu_200m_100m_parents[] = { 521 1.1 ryo "clk_pmu1_200m_src", "clk_pmu1_100m_src" }; 522 1.1 ryo static const char *pmu_300m_24m_parents[] = { 523 1.1 ryo "clk_300m_src", "xin24m" }; 524 1.1 ryo static const char *pmu_400m_24m_parents[] = { 525 1.1 ryo "clk_400m_src", "xin24m" }; 526 1.1 ryo static const char *pmu_100m_50m_24m_src_parents[]= { 527 1.1 ryo "clk_pmu1_100m_src", "clk_pmu1_50m_src", "xin24m" }; 528 1.1 ryo static const char *pmu_24m_32k_100m_src_parents[]= { 529 1.1 ryo "xin24m", "32k", "clk_pmu1_100m_src" }; 530 1.1 ryo static const char *hclk_pmu1_root_parents[] = { 531 1.1 ryo "clk_pmu1_200m_src", "clk_pmu1_100m_src", "clk_pmu1_50m_src", "xin24m" }; 532 1.1 ryo static const char *hclk_pmu_cm0_root_parents[] = { 533 1.1 ryo "clk_pmu1_400m_src", "clk_pmu1_200m_src", "clk_pmu1_100m_src", "xin24m" }; 534 1.1 ryo static const char *mclk_pdm0_parents[] = { 535 1.1 ryo "clk_pmu1_300m_src", "clk_pmu1_200m_src" }; 536 1.1 ryo static const char *mux_24m_ppll_spll_parents[] = { 537 1.1 ryo "xin24m", "ppll", "spll" }; 538 1.1 ryo static const char *mux_24m_ppll_parents[] = { 539 1.1 ryo "xin24m", "ppll" }; 540 1.1 ryo static const char *aclk_vop_sub_src_parents[] = { 541 1.1 ryo "aclk_vop_root", "aclk_vop_div2_src" }; 542 1.1 ryo static const char *clk_ref_pipe_phy0_parents[] = { 543 1.1 ryo "clk_ref_pipe_phy0_osc_src", "clk_ref_pipe_phy0_pll_src" }; 544 1.1 ryo static const char *clk_ref_pipe_phy1_parents[] = { 545 1.1 ryo "clk_ref_pipe_phy1_osc_src", "clk_ref_pipe_phy1_pll_src" }; 546 1.1 ryo static const char *clk_ref_pipe_phy2_parents[] = { 547 1.1 ryo "clk_ref_pipe_phy2_osc_src", "clk_ref_pipe_phy2_pll_src" }; 548 1.1 ryo static const char *i2s0_8ch_mclkout_parents[] = { 549 1.1 ryo "mclk_i2s0_8ch_tx", "mclk_i2s0_8ch_rx", "xin12m" }; 550 1.1 ryo static const char *i2s1_8ch_mclkout_parents[] = { 551 1.1 ryo "mclk_i2s1_8ch_tx", "mclk_i2s1_8ch_rx", "xin12m" }; 552 1.1 ryo static const char *i2s2_2ch_mclkout_parents[] = { 553 1.1 ryo "mclk_i2s2_2ch", "xin12m" }; 554 1.1 ryo static const char *i2s3_2ch_mclkout_parents[] = { 555 1.1 ryo "mclk_i2s3_2ch", "xin12m" }; 556 1.1 ryo static const char *i2s6_8ch_mclkout_parents[] = { 557 1.1 ryo "mclk_i2s6_8ch_tx", "mclk_i2s6_8ch_rx", "xin12m" }; 558 1.1 ryo 559 1.1 ryo 560 1.1 ryo static struct rk_cru_clk rk3588_cru_clks[] = { 561 1.1 ryo /* PLLs */ 562 1.1 ryo RK3588_PLL(RK3588_PLL_B0PLL, "b0pll", mux_pll_parents, 563 1.1 ryo PLL_CON(BIGCORE0, 0), 564 1.1 ryo CLKSEL_CON(BIGCORE0, 0), 565 1.1 ryo __BIT(6), 566 1.1 ryo __BIT(15), 567 1.1 ryo rk3588_pll_rates), 568 1.1 ryo RK3588_PLL(RK3588_PLL_B1PLL, "b1pll", mux_pll_parents, 569 1.1 ryo PLL_CON(BIGCORE1, 8), 570 1.1 ryo CLKSEL_CON(BIGCORE1, 0), 571 1.1 ryo __BIT(6), 572 1.1 ryo __BIT(15), 573 1.1 ryo rk3588_pll_rates), 574 1.1 ryo 575 1.1 ryo RK3588_PLL(RK3588_PLL_LPLL, "lpll", mux_pll_parents, 576 1.1 ryo PLL_CON(DSU, 16), 577 1.1 ryo CLKSEL_CON(DSU, 5), 578 1.1 ryo __BIT(14), 579 1.1 ryo __BIT(15), 580 1.1 ryo rk3588_pll_rates), 581 1.1 ryo RK3588_PLL(RK3588_PLL_V0PLL, "v0pll", mux_pll_parents, 582 1.1 ryo PLL_CON(0, 88), 583 1.1 ryo MODE_CON(0, 0), 584 1.1 ryo __BIT(4), 585 1.1 ryo __BIT(15), 586 1.1 ryo rk3588_pll_rates), 587 1.1 ryo RK3588_PLL(RK3588_PLL_AUPLL, "aupll", mux_pll_parents, 588 1.1 ryo PLL_CON(0, 96), 589 1.1 ryo MODE_CON(0, 0), 590 1.1 ryo __BIT(6), 591 1.1 ryo __BIT(15), 592 1.1 ryo rk3588_pll_rates), 593 1.1 ryo RK3588_PLL(RK3588_PLL_CPLL, "cpll", mux_pll_parents, 594 1.1 ryo PLL_CON(0, 104), 595 1.1 ryo MODE_CON(0, 0), 596 1.1 ryo __BIT(8), 597 1.1 ryo __BIT(15), 598 1.1 ryo rk3588_pll_rates), 599 1.1 ryo RK3588_PLL(RK3588_PLL_GPLL, "gpll", mux_pll_parents, 600 1.1 ryo PLL_CON(0, 112), 601 1.1 ryo MODE_CON(0, 0), 602 1.1 ryo __BIT(2), 603 1.1 ryo __BIT(15), 604 1.1 ryo rk3588_pll_rates), 605 1.1 ryo RK3588_PLL(RK3588_PLL_NPLL, "npll", mux_pll_parents, 606 1.1 ryo PLL_CON(0, 120), 607 1.1 ryo MODE_CON(0, 0), 608 1.1 ryo __BIT(0), 609 1.1 ryo __BIT(15), 610 1.1 ryo rk3588_pll_rates), 611 1.1 ryo RK3588_PLL(RK3588_PLL_PPLL, "ppll", mux_pll_parents, 612 1.1 ryo PLL_CON(PHP, 128), 613 1.1 ryo MODE_CON(0, 0), 614 1.1 ryo __BIT(10), 615 1.1 ryo __BIT(15), 616 1.1 ryo rk3588_pll_rates), 617 1.1 ryo 618 1.1 ryo /* big,little cores */ 619 1.1 ryo RK_CPU_CORE4(RK3588_ARMCLK_L, "armclk_l", mux_armclkl_parents, 620 1.1 ryo CLKSEL_CON(DSU, 5), /* mux_reg */ 621 1.1 ryo __BITS(15,14), 2, 1, /* mux_mask, mux_main, mux_alt */ 622 1.1 ryo CLKSEL_CON(DSU, 6), /* div0_reg */ 623 1.1 ryo __BITS(4,0), /* div0_mask */ 624 1.1 ryo CLKSEL_CON(DSU, 6), /* div1_reg */ 625 1.1 ryo __BITS(11,7), /* div1_mask */ 626 1.1 ryo CLKSEL_CON(DSU, 7), /* div2_reg */ 627 1.1 ryo __BITS(4,0), /* div2_mask */ 628 1.1 ryo CLKSEL_CON(DSU, 7), /* div3_reg */ 629 1.1 ryo __BITS(11,7), /* div3_mask */ 630 1.1 ryo armclk_l_rates), 631 1.1 ryo RK_CPU_CORE2(RK3588_ARMCLK_B01, "armclk_b01", mux_armclkb01_parents, 632 1.1 ryo CLKSEL_CON(BIGCORE0, 0), /* mux_reg */ 633 1.1 ryo __BITS(7,6), 2, 1, /* mux_mask, mux_main, mux_alt */ 634 1.1 ryo CLKSEL_CON(BIGCORE0, 0), /* div0_reg */ 635 1.1 ryo __BITS(12,8), /* div0_mask */ 636 1.1 ryo CLKSEL_CON(BIGCORE0, 1), /* div1_reg */ 637 1.1 ryo __BITS(4,0), /* div1_mask */ 638 1.1 ryo armclk_b01_rates), 639 1.2 tnn RK_CPU_CORE2(RK3588_ARMCLK_B23, "armclk_b23", mux_armclkb23_parents, 640 1.1 ryo CLKSEL_CON(BIGCORE1, 0), /* reg */ 641 1.1 ryo __BITS(7,6), 2, 1, /* mux_mask, mux_main, mux_alt */ 642 1.1 ryo CLKSEL_CON(BIGCORE1, 0), /* div0_reg */ 643 1.1 ryo __BITS(12,8), /* div0_mask */ 644 1.1 ryo CLKSEL_CON(BIGCORE1, 1), /* div1_reg */ 645 1.1 ryo __BITS(4,0), /* div1_mask */ 646 1.1 ryo armclk_b23_rates), 647 1.1 ryo 648 1.1 ryo RK_COMPOSITE_NODIV(RK3588_PCLK_BIGCORE0_ROOT, "pclk_bigcore0_root", 649 1.1 ryo mux_100m_50m_24m_parents, 650 1.1 ryo CLKSEL_CON(BIGCORE0, 2), __BITS(1,0), 651 1.1 ryo CLKGATE_CON(BIGCORE0, 0), __BIT(14), 652 1.1 ryo 0), 653 1.1 ryo RK_GATE(RK3588_PCLK_BIGCORE0_PVTM, "pclk_bigcore0_pvtm", 654 1.1 ryo "pclk_bigcore0_root", 655 1.1 ryo CLKGATE_CON(BIGCORE0, 1), 0), 656 1.1 ryo RK_GATE(RK3588_CLK_BIGCORE0_PVTM, "clk_bigcore0_pvtm", "xin24m", 657 1.1 ryo CLKGATE_CON(BIGCORE0, 0), 12), 658 1.1 ryo RK_GATE(RK3588_CLK_CORE_BIGCORE0_PVTM, "clk_core_bigcore0_pvtm", 659 1.1 ryo "armclk_b01", 660 1.1 ryo CLKGATE_CON(BIGCORE0, 0), 13), 661 1.1 ryo 662 1.1 ryo RK_COMPOSITE_NODIV(RK3588_PCLK_BIGCORE1_ROOT, "pclk_bigcore1_root", 663 1.1 ryo mux_100m_50m_24m_parents, 664 1.1 ryo CLKSEL_CON(BIGCORE1, 2), __BITS(1,0), 665 1.1 ryo CLKGATE_CON(BIGCORE1, 0), __BIT(14), 666 1.1 ryo 0), 667 1.1 ryo RK_GATE(RK3588_PCLK_BIGCORE1_PVTM, "pclk_bigcore1_pvtm", 668 1.1 ryo "pclk_bigcore1_root", 669 1.1 ryo CLKGATE_CON(BIGCORE1, 1), 0), 670 1.1 ryo RK_GATE(RK3588_CLK_BIGCORE1_PVTM, "clk_bigcore1_pvtm", "xin24m", 671 1.1 ryo CLKGATE_CON(BIGCORE1, 0), 12), 672 1.1 ryo RK_GATE(RK3588_CLK_CORE_BIGCORE1_PVTM, "clk_core_bigcore1_pvtm", 673 1.1 ryo "armclk_b23", 674 1.1 ryo CLKGATE_CON(BIGCORE1, 0), 13), 675 1.1 ryo 676 1.1 ryo RK_COMPOSITE(RK3588_CLK_50M_SRC, "clk_50m_src", 677 1.1 ryo gpll_cpll_parents, 678 1.1 ryo CLKSEL_CON(0, 0), __BITS(5,5), __BITS(4,0), 679 1.1 ryo CLKGATE_CON(0, 0), __BIT(0), 680 1.1 ryo 0), 681 1.1 ryo RK_COMPOSITE(RK3588_CLK_100M_SRC, "clk_100m_src", 682 1.1 ryo gpll_cpll_parents, 683 1.1 ryo CLKSEL_CON(0, 0), __BITS(11,11), __BITS(10,6), 684 1.1 ryo CLKGATE_CON(0, 0), __BIT(1), 685 1.1 ryo 0), 686 1.1 ryo RK_COMPOSITE(RK3588_CLK_150M_SRC, "clk_150m_src", 687 1.1 ryo gpll_cpll_parents, 688 1.1 ryo CLKSEL_CON(0, 1), __BITS(5,5), __BITS(4,0), 689 1.1 ryo CLKGATE_CON(0, 0), __BIT(2), 690 1.1 ryo 0), 691 1.1 ryo RK_COMPOSITE(RK3588_CLK_200M_SRC, "clk_200m_src", 692 1.1 ryo gpll_cpll_parents, 693 1.1 ryo CLKSEL_CON(0, 1), __BITS(11,11), __BITS(10,6), 694 1.1 ryo CLKGATE_CON(0, 0), __BIT(3), 695 1.1 ryo 0), 696 1.1 ryo RK_COMPOSITE(RK3588_CLK_250M_SRC, "clk_250m_src", 697 1.1 ryo gpll_cpll_parents, 698 1.1 ryo CLKSEL_CON(0, 2), __BITS(5,5), __BITS(4,0), 699 1.1 ryo CLKGATE_CON(0, 0), __BIT(4), 700 1.1 ryo 0), 701 1.1 ryo RK_COMPOSITE(RK3588_CLK_300M_SRC, "clk_300m_src", 702 1.1 ryo gpll_cpll_parents, 703 1.1 ryo CLKSEL_CON(0, 2), __BITS(11,11), __BITS(10,6), 704 1.1 ryo CLKGATE_CON(0, 0), __BIT(5), 705 1.1 ryo 0), 706 1.1 ryo RK_COMPOSITE(RK3588_CLK_350M_SRC, "clk_350m_src", 707 1.1 ryo gpll_spll_parents, 708 1.1 ryo CLKSEL_CON(0, 3), __BITS(5,5), __BITS(4,0), 709 1.1 ryo CLKGATE_CON(0, 0), __BIT(6), 710 1.1 ryo 0), 711 1.1 ryo RK_COMPOSITE(RK3588_CLK_400M_SRC, "clk_400m_src", 712 1.1 ryo gpll_cpll_parents, 713 1.1 ryo CLKSEL_CON(0, 3), __BITS(11,11), __BITS(10,6), 714 1.1 ryo CLKGATE_CON(0, 0), __BIT(7), 715 1.1 ryo 0), 716 1.1 ryo RK_COMPOSITE_HALF(RK3588_CLK_450M_SRC, "clk_450m_src", 717 1.1 ryo gpll_cpll_parents, 718 1.1 ryo CLKSEL_CON(0, 4), __BITS(5,5), 719 1.1 ryo __BITS(4,0), 720 1.1 ryo CLKGATE_CON(0, 0), __BIT(8), 721 1.1 ryo 0), 722 1.1 ryo RK_COMPOSITE(RK3588_CLK_500M_SRC, "clk_500m_src", 723 1.1 ryo gpll_cpll_parents, 724 1.1 ryo CLKSEL_CON(0, 4), __BITS(11,11), __BITS(10,6), 725 1.1 ryo CLKGATE_CON(0, 0), __BIT(9), 726 1.1 ryo 0), 727 1.1 ryo RK_COMPOSITE(RK3588_CLK_600M_SRC, "clk_600m_src", 728 1.1 ryo gpll_cpll_parents, 729 1.1 ryo CLKSEL_CON(0, 5), __BITS(5,5), __BITS(4,0), 730 1.1 ryo CLKGATE_CON(0, 0), __BIT(10), 731 1.1 ryo 0), 732 1.1 ryo RK_COMPOSITE(RK3588_CLK_650M_SRC, "clk_650m_src", 733 1.1 ryo gpll_lpll_parents, 734 1.1 ryo CLKSEL_CON(0, 5), __BITS(11,11), __BITS(10,6), 735 1.1 ryo CLKGATE_CON(0, 0), __BIT(11), 736 1.1 ryo 0), 737 1.1 ryo RK_COMPOSITE(RK3588_CLK_700M_SRC, "clk_700m_src", 738 1.1 ryo gpll_spll_parents, 739 1.1 ryo CLKSEL_CON(0, 6), __BITS(5,5), __BITS(4,0), 740 1.1 ryo CLKGATE_CON(0, 0), __BIT(12), 741 1.1 ryo 0), 742 1.1 ryo RK_COMPOSITE(RK3588_CLK_800M_SRC, "clk_800m_src", 743 1.1 ryo gpll_aupll_parents, 744 1.1 ryo CLKSEL_CON(0, 6), __BITS(11,11), __BITS(10,6), 745 1.1 ryo CLKGATE_CON(0, 0), __BIT(13), 746 1.1 ryo 0), 747 1.1 ryo RK_COMPOSITE_HALF(RK3588_CLK_1000M_SRC, "clk_1000m_src", 748 1.1 ryo gpll_cpll_npll_v0pll_parents, 749 1.1 ryo CLKSEL_CON(0, 7), __BITS(6,5), 750 1.1 ryo __BITS(4,0), 751 1.1 ryo CLKGATE_CON(0, 0), __BIT(14), 752 1.1 ryo 0), 753 1.1 ryo RK_COMPOSITE(RK3588_CLK_1200M_SRC, "clk_1200m_src", 754 1.1 ryo gpll_cpll_parents, 755 1.1 ryo CLKSEL_CON(0, 7), __BITS(12,12), __BITS(11,7), 756 1.1 ryo CLKGATE_CON(0, 0), __BIT(15), 757 1.1 ryo 0), 758 1.1 ryo RK_COMPOSITE_NODIV(RK3588_ACLK_TOP_M300_ROOT, "aclk_top_m300_root", 759 1.1 ryo mux_300m_200m_100m_24m_parents, 760 1.1 ryo CLKSEL_CON(0, 9), __BITS(1,0), 761 1.1 ryo CLKGATE_CON(0, 1), __BIT(10), 762 1.1 ryo 0), 763 1.1 ryo RK_COMPOSITE_NODIV(RK3588_ACLK_TOP_M500_ROOT, "aclk_top_m500_root", 764 1.1 ryo mux_500m_300m_100m_24m_parents, 765 1.1 ryo CLKSEL_CON(0, 9), __BITS(3,2), 766 1.1 ryo CLKGATE_CON(0, 1), __BIT(11), 767 1.1 ryo 0), 768 1.1 ryo RK_COMPOSITE_NODIV(RK3588_ACLK_TOP_M400_ROOT, "aclk_top_m400_root", 769 1.1 ryo mux_400m_200m_100m_24m_parents, 770 1.1 ryo CLKSEL_CON(0, 9), __BITS(5,4), 771 1.1 ryo CLKGATE_CON(0, 1), __BIT(12), 772 1.1 ryo 0), 773 1.1 ryo RK_COMPOSITE_NODIV(RK3588_ACLK_TOP_S200_ROOT, "aclk_top_s200_root", 774 1.1 ryo mux_200m_100m_50m_24m_parents, 775 1.1 ryo CLKSEL_CON(0, 9), __BITS(7,6), 776 1.1 ryo CLKGATE_CON(0, 1), __BIT(13), 777 1.1 ryo 0), 778 1.1 ryo RK_COMPOSITE_NODIV(RK3588_ACLK_TOP_S400_ROOT, "aclk_top_s400_root", 779 1.1 ryo mux_400m_200m_100m_24m_parents, 780 1.1 ryo CLKSEL_CON(0, 9), __BITS(9,8), 781 1.1 ryo CLKGATE_CON(0, 1), __BIT(14), 782 1.1 ryo 0), 783 1.1 ryo RK_COMPOSITE(RK3588_ACLK_TOP_ROOT, "aclk_top_root", 784 1.1 ryo gpll_cpll_aupll_parents, 785 1.1 ryo CLKSEL_CON(0, 8), __BITS(6,5), __BITS(4,0), 786 1.1 ryo CLKGATE_CON(0, 1), __BIT(0), 787 1.1 ryo 0), 788 1.1 ryo RK_COMPOSITE_NODIV(RK3588_PCLK_TOP_ROOT, "pclk_top_root", 789 1.1 ryo mux_100m_50m_24m_parents, 790 1.1 ryo CLKSEL_CON(0, 8), __BITS(8,7), 791 1.1 ryo CLKGATE_CON(0, 1), __BIT(1), 792 1.1 ryo 0), 793 1.1 ryo RK_COMPOSITE(RK3588_ACLK_LOW_TOP_ROOT, "aclk_low_top_root", 794 1.1 ryo gpll_cpll_parents, 795 1.1 ryo CLKSEL_CON(0, 8), __BITS(14,14), __BITS(13,9), 796 1.1 ryo CLKGATE_CON(0, 1), __BIT(2), 797 1.1 ryo 0), 798 1.1 ryo RK_COMPOSITE(RK3588_CLK_MIPI_CAMARAOUT_M0, "clk_mipi_camaraout_m0", 799 1.1 ryo mux_24m_spll_gpll_cpll_parents, 800 1.1 ryo CLKSEL_CON(0, 18), __BITS(9,8), __BITS(7,0), 801 1.1 ryo CLKGATE_CON(0, 5), __BIT(9), 802 1.1 ryo 0), 803 1.1 ryo RK_COMPOSITE(RK3588_CLK_MIPI_CAMARAOUT_M1, "clk_mipi_camaraout_m1", 804 1.1 ryo mux_24m_spll_gpll_cpll_parents, 805 1.1 ryo CLKSEL_CON(0, 19), __BITS(9,8), __BITS(7,0), 806 1.1 ryo CLKGATE_CON(0, 5), __BIT(10), 807 1.1 ryo 0), 808 1.1 ryo RK_COMPOSITE(RK3588_CLK_MIPI_CAMARAOUT_M2, "clk_mipi_camaraout_m2", 809 1.1 ryo mux_24m_spll_gpll_cpll_parents, 810 1.1 ryo CLKSEL_CON(0, 20), __BITS(9,8), __BITS(7,0), 811 1.1 ryo CLKGATE_CON(0, 5), __BIT(11), 812 1.1 ryo 0), 813 1.1 ryo RK_COMPOSITE(RK3588_CLK_MIPI_CAMARAOUT_M3, "clk_mipi_camaraout_m3", 814 1.1 ryo mux_24m_spll_gpll_cpll_parents, 815 1.1 ryo CLKSEL_CON(0, 21), __BITS(9,8), __BITS(7,0), 816 1.1 ryo CLKGATE_CON(0, 5), __BIT(12), 817 1.1 ryo 0), 818 1.1 ryo RK_COMPOSITE(RK3588_CLK_MIPI_CAMARAOUT_M4, "clk_mipi_camaraout_m4", 819 1.1 ryo mux_24m_spll_gpll_cpll_parents, 820 1.1 ryo CLKSEL_CON(0, 22), __BITS(9,8), __BITS(7,0), 821 1.1 ryo CLKGATE_CON(0, 5), __BIT(13), 822 1.1 ryo 0), 823 1.1 ryo RK_COMPOSITE(RK3588_MCLK_GMAC0_OUT, "mclk_gmac0_out", 824 1.1 ryo gpll_cpll_parents, 825 1.1 ryo CLKSEL_CON(0, 15), __BITS(7,7), __BITS(6,0), 826 1.1 ryo CLKGATE_CON(0, 5), __BIT(3), 827 1.1 ryo 0), 828 1.1 ryo RK_COMPOSITE(RK3588_REFCLKO25M_ETH0_OUT, "refclko25m_eth0_out", 829 1.1 ryo gpll_cpll_parents, 830 1.1 ryo CLKSEL_CON(0, 15), __BITS(15,15), __BITS(14,8), 831 1.1 ryo CLKGATE_CON(0, 5), __BIT(4), 832 1.1 ryo 0), 833 1.1 ryo RK_COMPOSITE(RK3588_REFCLKO25M_ETH1_OUT, "refclko25m_eth1_out", 834 1.1 ryo gpll_cpll_parents, 835 1.1 ryo CLKSEL_CON(0, 16), __BITS(7,7), __BITS(6,0), 836 1.1 ryo CLKGATE_CON(0, 5), __BIT(5), 837 1.1 ryo 0), 838 1.1 ryo RK_COMPOSITE(RK3588_CLK_CIFOUT_OUT, "clk_cifout_out", 839 1.1 ryo gpll_cpll_24m_spll_parents, 840 1.1 ryo CLKSEL_CON(0, 17), __BITS(9,8), __BITS(7,0), 841 1.1 ryo CLKGATE_CON(0, 5), __BIT(6), 842 1.1 ryo 0), 843 1.1 ryo RK_GATE(RK3588_PCLK_MIPI_DCPHY0, "pclk_mipi_dcphy0", "pclk_top_root", 844 1.1 ryo CLKGATE_CON(0, 3), 14), 845 1.1 ryo RK_GATE(RK3588_PCLK_MIPI_DCPHY1, "pclk_mipi_dcphy1", "pclk_top_root", 846 1.1 ryo CLKGATE_CON(0, 4), 3), 847 1.1 ryo RK_GATE(RK3588_PCLK_CSIPHY0, "pclk_csiphy0", "pclk_top_root", 848 1.1 ryo CLKGATE_CON(0, 1), 6), 849 1.1 ryo RK_GATE(RK3588_PCLK_CSIPHY1, "pclk_csiphy1", "pclk_top_root", 850 1.1 ryo CLKGATE_CON(0, 1), 8), 851 1.1 ryo RK_GATE(RK3588_PCLK_CRU, "pclk_cru", "pclk_top_root", 852 1.1 ryo CLKGATE_CON(0, 5), 0), 853 1.1 ryo RK_COMPOSITE(0, "sclk_dsu", 854 1.1 ryo b0pll_b1pll_lpll_gpll_parents, 855 1.1 ryo CLKSEL_CON(DSU, 0), __BITS(13,12), __BITS(4,0), 856 1.1 ryo CLKGATE_CON(DSU, 0), __BIT(4), 857 1.1 ryo 0), 858 1.1 ryo RK_COMPOSITE_NOMUX(0, "atclk_dsu", "sclk_dsu", 859 1.1 ryo CLKSEL_CON(DSU, 3), __BITS(4,0), 860 1.1 ryo CLKGATE_CON(DSU, 1), __BIT(0), 861 1.1 ryo 0), 862 1.1 ryo RK_COMPOSITE_NOMUX(0, "gicclk_dsu", "sclk_dsu", 863 1.1 ryo CLKSEL_CON(DSU, 3), __BITS(9,5), 864 1.1 ryo CLKGATE_CON(DSU, 1), __BIT(1), 865 1.1 ryo 0), 866 1.1 ryo RK_COMPOSITE_NOMUX(0, "aclkmp_dsu", "sclk_dsu", 867 1.1 ryo CLKSEL_CON(DSU, 1), __BITS(15,11), 868 1.1 ryo CLKGATE_CON(DSU, 0), __BIT(12), 869 1.1 ryo 0), 870 1.1 ryo RK_COMPOSITE_NOMUX(0, "aclkm_dsu", "sclk_dsu", 871 1.1 ryo CLKSEL_CON(DSU, 1), __BITS(5,1), 872 1.1 ryo CLKGATE_CON(DSU, 0), __BIT(8), 873 1.1 ryo 0), 874 1.1 ryo RK_COMPOSITE_NOMUX(0, "aclks_dsu", "sclk_dsu", 875 1.1 ryo CLKSEL_CON(DSU, 1), __BITS(10,6), 876 1.1 ryo CLKGATE_CON(DSU, 0), __BIT(9), 877 1.1 ryo 0), 878 1.1 ryo RK_COMPOSITE_NOMUX(0, "periph_dsu", "sclk_dsu", 879 1.1 ryo CLKSEL_CON(DSU, 2), __BITS(4,0), 880 1.1 ryo CLKGATE_CON(DSU, 0), __BIT(13), 881 1.1 ryo 0), 882 1.1 ryo RK_COMPOSITE_NOMUX(0, "cntclk_dsu", "periph_dsu", 883 1.1 ryo CLKSEL_CON(DSU, 2), __BITS(9,5), 884 1.1 ryo CLKGATE_CON(DSU, 0), __BIT(14), 885 1.1 ryo 0), 886 1.1 ryo RK_COMPOSITE_NOMUX(0, "tsclk_dsu", "periph_dsu", 887 1.1 ryo CLKSEL_CON(DSU, 2), __BITS(14,10), 888 1.1 ryo CLKGATE_CON(DSU, 0), __BIT(15), 889 1.1 ryo 0), 890 1.1 ryo RK_COMPOSITE_NODIV(RK3588_PCLK_DSU_S_ROOT, "pclk_dsu_s_root", 891 1.1 ryo mux_100m_50m_24m_parents, 892 1.1 ryo CLKSEL_CON(DSU, 4), __BITS(12,11), 893 1.1 ryo CLKGATE_CON(DSU, 2), __BIT(2), 894 1.1 ryo 0), 895 1.1 ryo RK_COMPOSITE(RK3588_PCLK_DSU_ROOT, "pclk_dsu_root", 896 1.1 ryo b0pll_b1pll_lpll_gpll_parents, 897 1.1 ryo CLKSEL_CON(DSU, 4), __BITS(6,5), __BITS(4,0), 898 1.1 ryo CLKGATE_CON(DSU, 1), __BIT(3), 899 1.1 ryo 0), 900 1.1 ryo RK_COMPOSITE_NODIV(RK3588_PCLK_DSU_NS_ROOT, "pclk_dsu_ns_root", 901 1.1 ryo mux_100m_50m_24m_parents, 902 1.1 ryo CLKSEL_CON(DSU, 4), __BITS(8,7), 903 1.1 ryo CLKGATE_CON(DSU, 1), __BIT(4), 904 1.1 ryo 0), 905 1.1 ryo RK_GATE(RK3588_PCLK_LITCORE_PVTM, "pclk_litcore_pvtm", 906 1.1 ryo "pclk_dsu_ns_root", 907 1.1 ryo CLKGATE_CON(DSU, 2), 6), 908 1.1 ryo RK_GATE(RK3588_PCLK_DBG, "pclk_dbg", "pclk_dsu_root", 909 1.1 ryo CLKGATE_CON(DSU, 1), 7), 910 1.1 ryo RK_GATE(RK3588_PCLK_DSU, "pclk_dsu", "pclk_dsu_root", 911 1.1 ryo CLKGATE_CON(DSU, 1), 6), 912 1.1 ryo RK_GATE(RK3588_PCLK_S_DAPLITE, "pclk_s_daplite", "pclk_dsu_ns_root", 913 1.1 ryo CLKGATE_CON(DSU, 1), 8), 914 1.1 ryo RK_GATE(RK3588_PCLK_M_DAPLITE, "pclk_m_daplite", "pclk_dsu_root", 915 1.1 ryo CLKGATE_CON(DSU, 1), 9), 916 1.1 ryo RK_GATE(RK3588_CLK_LITCORE_PVTM, "clk_litcore_pvtm", "xin24m", 917 1.1 ryo CLKGATE_CON(DSU, 2), 0), 918 1.1 ryo RK_GATE(RK3588_CLK_CORE_LITCORE_PVTM, "clk_core_litcore_pvtm", 919 1.1 ryo "armclk_l", 920 1.1 ryo CLKGATE_CON(DSU, 2), 1), 921 1.1 ryo RK_COMPOSITE_NODIV(RK3588_HCLK_AUDIO_ROOT, "hclk_audio_root", 922 1.1 ryo mux_200m_100m_50m_24m_parents, 923 1.1 ryo CLKSEL_CON(0, 24), __BITS(1,0), 924 1.1 ryo CLKGATE_CON(0, 7), __BIT(0), 925 1.1 ryo 0), 926 1.1 ryo RK_COMPOSITE_NODIV(RK3588_PCLK_AUDIO_ROOT, "pclk_audio_root", 927 1.1 ryo mux_100m_50m_24m_parents, 928 1.1 ryo CLKSEL_CON(0, 24), __BITS(3,2), 929 1.1 ryo CLKGATE_CON(0, 7), __BIT(1), 930 1.1 ryo 0), 931 1.1 ryo RK_GATE(RK3588_HCLK_I2S2_2CH, "hclk_i2s2_2ch", "hclk_audio_root", 932 1.1 ryo CLKGATE_CON(0, 7), 12), 933 1.1 ryo RK_GATE(RK3588_HCLK_I2S3_2CH, "hclk_i2s3_2ch", "hclk_audio_root", 934 1.1 ryo CLKGATE_CON(0, 7), 13), 935 1.1 ryo RK_COMPOSITE(RK3588_CLK_I2S2_2CH_SRC, "clk_i2s2_2ch_src", 936 1.1 ryo gpll_aupll_parents, 937 1.1 ryo CLKSEL_CON(0, 28), __BITS(9,9), __BITS(8,4), 938 1.1 ryo CLKGATE_CON(0, 7), __BIT(14), 939 1.1 ryo 0), 940 1.1 ryo RK_COMPOSITE_FRAC(RK3588_CLK_I2S2_2CH_FRAC, "clk_i2s2_2ch_frac", 941 1.1 ryo "clk_i2s2_2ch_src", 942 1.1 ryo CLKGATE_CON(0, 7), 943 1.1 ryo RK_COMPOSITE_SET_RATE_PARENT), 944 1.1 ryo RK_MUX(RK3588_CLK_I2S2_2CH, "clk_i2s2_2ch", clk_i2s2_2ch_parents, 945 1.1 ryo CLKSEL_CON(0, 30), __BITS(1,0)), 946 1.1 ryo RK_GATE(RK3588_MCLK_I2S2_2CH, "mclk_i2s2_2ch", "clk_i2s2_2ch", 947 1.1 ryo CLKGATE_CON(0, 8), 0), 948 1.1 ryo RK_MUX(RK3588_I2S2_2CH_MCLKOUT, "i2s2_2ch_mclkout", 949 1.1 ryo i2s2_2ch_mclkout_parents, 950 1.1 ryo CLKSEL_CON(0, 30), __BITS(2,2)), 951 1.1 ryo RK_COMPOSITE(RK3588_CLK_I2S3_2CH_SRC, "clk_i2s3_2ch_src", 952 1.1 ryo gpll_aupll_parents, 953 1.1 ryo CLKSEL_CON(0, 30), __BITS(8,8), __BITS(7,3), 954 1.1 ryo CLKGATE_CON(0, 8), __BIT(1), 955 1.1 ryo 0), 956 1.1 ryo RK_COMPOSITE_FRAC(RK3588_CLK_I2S3_2CH_FRAC, "clk_i2s3_2ch_frac", 957 1.1 ryo "clk_i2s3_2ch_src", 958 1.1 ryo CLKGATE_CON(0, 8), 959 1.1 ryo RK_COMPOSITE_SET_RATE_PARENT), 960 1.1 ryo RK_MUX(RK3588_CLK_I2S3_2CH, "clk_i2s3_2ch", clk_i2s3_2ch_parents, 961 1.1 ryo CLKSEL_CON(0, 32), __BITS(1,0)), 962 1.1 ryo RK_GATE(RK3588_MCLK_I2S3_2CH, "mclk_i2s3_2ch", "clk_i2s3_2ch", 963 1.1 ryo CLKGATE_CON(0, 8), 3), 964 1.1 ryo RK_GATE(RK3588_CLK_DAC_ACDCDIG, "clk_dac_acdcdig", "mclk_i2s3_2ch", 965 1.1 ryo CLKGATE_CON(0, 8), 4), 966 1.1 ryo RK_MUX(RK3588_I2S3_2CH_MCLKOUT, "i2s3_2ch_mclkout", 967 1.1 ryo i2s3_2ch_mclkout_parents, 968 1.1 ryo CLKSEL_CON(0, 32), __BITS(2,2)), 969 1.1 ryo RK_GATE(RK3588_PCLK_ACDCDIG, "pclk_acdcdig", "pclk_audio_root", 970 1.1 ryo CLKGATE_CON(0, 7), 11), 971 1.1 ryo RK_GATE(RK3588_HCLK_I2S0_8CH, "hclk_i2s0_8ch", "hclk_audio_root", 972 1.1 ryo CLKGATE_CON(0, 7), 4), 973 1.1 ryo RK_COMPOSITE(RK3588_CLK_I2S0_8CH_TX_SRC, "clk_i2s0_8ch_tx_src", 974 1.1 ryo gpll_aupll_parents, 975 1.1 ryo CLKSEL_CON(0, 24), __BITS(9,9), __BITS(8,4), 976 1.1 ryo CLKGATE_CON(0, 7), __BIT(5), 977 1.1 ryo 0), 978 1.1 ryo RK_COMPOSITE_FRAC(RK3588_CLK_I2S0_8CH_TX_FRAC, "clk_i2s0_8ch_tx_frac", 979 1.1 ryo "clk_i2s0_8ch_tx_src", 980 1.1 ryo CLKGATE_CON(0, 7), 981 1.1 ryo RK_COMPOSITE_SET_RATE_PARENT), 982 1.1 ryo RK_MUX(RK3588_CLK_I2S0_8CH_TX, "clk_i2s0_8ch_tx", 983 1.1 ryo clk_i2s0_8ch_tx_parents, 984 1.1 ryo CLKSEL_CON(0, 26), __BITS(1,0)), 985 1.1 ryo RK_GATE(RK3588_MCLK_I2S0_8CH_TX, "mclk_i2s0_8ch_tx", "clk_i2s0_8ch_tx", 986 1.1 ryo CLKGATE_CON(0, 7), 7), 987 1.1 ryo RK_COMPOSITE(RK3588_CLK_I2S0_8CH_RX_SRC, "clk_i2s0_8ch_rx_src", 988 1.1 ryo gpll_aupll_parents, 989 1.1 ryo CLKSEL_CON(0, 26), __BITS(7,7), __BITS(6,2), 990 1.1 ryo CLKGATE_CON(0, 7), __BIT(8), 991 1.1 ryo 0), 992 1.1 ryo RK_COMPOSITE_FRAC(RK3588_CLK_I2S0_8CH_RX_FRAC, "clk_i2s0_8ch_rx_frac", 993 1.1 ryo "clk_i2s0_8ch_rx_src", 994 1.1 ryo CLKGATE_CON(0, 7), 995 1.1 ryo RK_COMPOSITE_SET_RATE_PARENT), 996 1.1 ryo RK_MUX(RK3588_CLK_I2S0_8CH_RX, "clk_i2s0_8ch_rx", 997 1.1 ryo clk_i2s0_8ch_rx_parents, 998 1.1 ryo CLKSEL_CON(0, 28), __BITS(1,0)), 999 1.1 ryo RK_GATE(RK3588_MCLK_I2S0_8CH_RX, "mclk_i2s0_8ch_rx", "clk_i2s0_8ch_rx", 1000 1.1 ryo CLKGATE_CON(0, 7), 10), 1001 1.1 ryo RK_MUX(RK3588_I2S0_8CH_MCLKOUT, "i2s0_8ch_mclkout", 1002 1.1 ryo i2s0_8ch_mclkout_parents, 1003 1.1 ryo CLKSEL_CON(0, 28), __BITS(3,2)), 1004 1.1 ryo RK_GATE(RK3588_HCLK_PDM1, "hclk_pdm1", "hclk_audio_root", 1005 1.1 ryo CLKGATE_CON(0, 9), 6), 1006 1.1 ryo RK_COMPOSITE(RK3588_MCLK_PDM1, "mclk_pdm1", 1007 1.1 ryo gpll_cpll_aupll_parents, 1008 1.1 ryo CLKSEL_CON(0, 36), __BITS(8,7), __BITS(6,2), 1009 1.1 ryo CLKGATE_CON(0, 9), __BIT(7), 1010 1.1 ryo 0), 1011 1.1 ryo RK_GATE(RK3588_HCLK_SPDIF0, "hclk_spdif0", "hclk_audio_root", 1012 1.1 ryo CLKGATE_CON(0, 8), 14), 1013 1.1 ryo RK_COMPOSITE(RK3588_CLK_SPDIF0_SRC, "clk_spdif0_src", 1014 1.1 ryo gpll_aupll_parents, 1015 1.1 ryo CLKSEL_CON(0, 32), __BITS(8,8), __BITS(7,3), 1016 1.1 ryo CLKGATE_CON(0, 8), __BIT(15), 1017 1.1 ryo 0), 1018 1.1 ryo RK_COMPOSITE_FRAC(RK3588_CLK_SPDIF0_FRAC, "clk_spdif0_frac", 1019 1.1 ryo "clk_spdif0_src", 1020 1.1 ryo CLKGATE_CON(0, 9), 1021 1.1 ryo RK_COMPOSITE_SET_RATE_PARENT), 1022 1.1 ryo RK_MUX(RK3588_CLK_SPDIF0, "clk_spdif0", clk_spdif0_parents, 1023 1.1 ryo CLKSEL_CON(0, 34), __BITS(1,0)), 1024 1.1 ryo RK_GATE(RK3588_MCLK_SPDIF0, "mclk_spdif0", "clk_spdif0", 1025 1.1 ryo CLKGATE_CON(0, 9), 1), 1026 1.1 ryo RK_GATE(RK3588_HCLK_SPDIF1, "hclk_spdif1", "hclk_audio_root", 1027 1.1 ryo CLKGATE_CON(0, 9), 2), 1028 1.1 ryo RK_COMPOSITE(RK3588_CLK_SPDIF1_SRC, "clk_spdif1_src", 1029 1.1 ryo gpll_aupll_parents, 1030 1.1 ryo CLKSEL_CON(0, 34), __BITS(7,7), __BITS(6,2), 1031 1.1 ryo CLKGATE_CON(0, 9), __BIT(3), 1032 1.1 ryo 0), 1033 1.1 ryo RK_COMPOSITE_FRAC(RK3588_CLK_SPDIF1_FRAC, "clk_spdif1_frac", 1034 1.1 ryo "clk_spdif1_src", 1035 1.1 ryo CLKGATE_CON(0, 9), 1036 1.1 ryo RK_COMPOSITE_SET_RATE_PARENT), 1037 1.1 ryo RK_MUX(RK3588_CLK_SPDIF1, "clk_spdif1", clk_spdif1_parents, 1038 1.1 ryo CLKSEL_CON(0, 36), __BITS(1,0)), 1039 1.1 ryo RK_GATE(RK3588_MCLK_SPDIF1, "mclk_spdif1", "clk_spdif1", 1040 1.1 ryo CLKGATE_CON(0, 9), 5), 1041 1.1 ryo RK_COMPOSITE(RK3588_ACLK_AV1_ROOT, "aclk_av1_root", 1042 1.1 ryo gpll_cpll_aupll_parents, 1043 1.1 ryo CLKSEL_CON(0, 163), __BITS(6,5), __BITS(4,0), 1044 1.1 ryo CLKGATE_CON(0, 68), __BIT(0), 1045 1.1 ryo 0), 1046 1.1 ryo RK_COMPOSITE_NODIV(RK3588_PCLK_AV1_ROOT, "pclk_av1_root", 1047 1.1 ryo mux_200m_100m_50m_24m_parents, 1048 1.1 ryo CLKSEL_CON(0, 163), __BITS(8,7), 1049 1.1 ryo CLKGATE_CON(0, 68), __BIT(3), 1050 1.1 ryo 0), 1051 1.1 ryo RK_COMPOSITE(RK3588_ACLK_BUS_ROOT, "aclk_bus_root", 1052 1.1 ryo gpll_cpll_parents, 1053 1.1 ryo CLKSEL_CON(0, 38), __BITS(5,5), __BITS(4,0), 1054 1.1 ryo CLKGATE_CON(0, 10), __BIT(0), 1055 1.1 ryo 0), 1056 1.1 ryo RK_GATE(RK3588_PCLK_MAILBOX0, "pclk_mailbox0", "pclk_top_root", 1057 1.1 ryo CLKGATE_CON(0, 16), 11), 1058 1.1 ryo RK_GATE(RK3588_PCLK_MAILBOX1, "pclk_mailbox1", "pclk_top_root", 1059 1.1 ryo CLKGATE_CON(0, 16), 12), 1060 1.1 ryo RK_GATE(RK3588_PCLK_MAILBOX2, "pclk_mailbox2", "pclk_top_root", 1061 1.1 ryo CLKGATE_CON(0, 16), 13), 1062 1.1 ryo RK_GATE(RK3588_PCLK_PMU2, "pclk_pmu2", "pclk_top_root", 1063 1.1 ryo CLKGATE_CON(0, 19), 3), 1064 1.1 ryo RK_GATE(RK3588_PCLK_PMUCM0_INTMUX, "pclk_pmucm0_intmux", 1065 1.1 ryo "pclk_top_root", 1066 1.1 ryo CLKGATE_CON(0, 19), 4), 1067 1.1 ryo RK_GATE(RK3588_PCLK_DDRCM0_INTMUX, "pclk_ddrcm0_intmux", 1068 1.1 ryo "pclk_top_root", 1069 1.1 ryo CLKGATE_CON(0, 19), 5), 1070 1.1 ryo RK_GATE(RK3588_PCLK_PWM1, "pclk_pwm1", "pclk_top_root", 1071 1.1 ryo CLKGATE_CON(0, 15), 3), 1072 1.1 ryo RK_COMPOSITE_NODIV(RK3588_CLK_PWM1, "clk_pwm1", 1073 1.1 ryo mux_100m_50m_24m_parents, 1074 1.1 ryo CLKSEL_CON(0, 59), __BITS(13,12), 1075 1.1 ryo CLKGATE_CON(0, 15), __BIT(4), 1076 1.1 ryo 0), 1077 1.1 ryo RK_GATE(RK3588_CLK_PWM1_CAPTURE, "clk_pwm1_capture", "xin24m", 1078 1.1 ryo CLKGATE_CON(0, 15), 5), 1079 1.1 ryo RK_GATE(RK3588_PCLK_PWM2, "pclk_pwm2", "pclk_top_root", 1080 1.1 ryo CLKGATE_CON(0, 15), 6), 1081 1.1 ryo RK_COMPOSITE_NODIV(RK3588_CLK_PWM2, "clk_pwm2", 1082 1.1 ryo mux_100m_50m_24m_parents, 1083 1.1 ryo CLKSEL_CON(0, 59), __BITS(15,14), 1084 1.1 ryo CLKGATE_CON(0, 15), __BIT(7), 1085 1.1 ryo 0), 1086 1.1 ryo RK_GATE(RK3588_CLK_PWM2_CAPTURE, "clk_pwm2_capture", "xin24m", 1087 1.1 ryo CLKGATE_CON(0, 15), 8), 1088 1.1 ryo RK_GATE(RK3588_PCLK_PWM3, "pclk_pwm3", "pclk_top_root", 1089 1.1 ryo CLKGATE_CON(0, 15), 9), 1090 1.1 ryo RK_COMPOSITE_NODIV(RK3588_CLK_PWM3, "clk_pwm3", 1091 1.1 ryo mux_100m_50m_24m_parents, 1092 1.1 ryo CLKSEL_CON(0, 60), __BITS(1,0), 1093 1.1 ryo CLKGATE_CON(0, 15), __BIT(10), 1094 1.1 ryo 0), 1095 1.1 ryo RK_GATE(RK3588_CLK_PWM3_CAPTURE, "clk_pwm3_capture", "xin24m", 1096 1.1 ryo CLKGATE_CON(0, 15), 11), 1097 1.1 ryo RK_GATE(RK3588_PCLK_BUSTIMER0, "pclk_bustimer0", "pclk_top_root", 1098 1.1 ryo CLKGATE_CON(0, 15), 12), 1099 1.1 ryo RK_GATE(RK3588_PCLK_BUSTIMER1, "pclk_bustimer1", "pclk_top_root", 1100 1.1 ryo CLKGATE_CON(0, 15), 13), 1101 1.1 ryo RK_COMPOSITE_NODIV(RK3588_CLK_BUS_TIMER_ROOT, "clk_bus_timer_root", 1102 1.1 ryo mux_24m_100m_parents, 1103 1.1 ryo CLKSEL_CON(0, 60), __BITS(2,2), 1104 1.1 ryo CLKGATE_CON(0, 15), __BIT(14), 1105 1.1 ryo 0), 1106 1.1 ryo RK_GATE(RK3588_CLK_BUSTIMER0, "clk_bustimer0", "clk_bus_timer_root", 1107 1.1 ryo CLKGATE_CON(0, 15), 15), 1108 1.1 ryo RK_GATE(RK3588_CLK_BUSTIMER1, "clk_bustimer1", "clk_bus_timer_root", 1109 1.1 ryo CLKGATE_CON(0, 16), 0), 1110 1.1 ryo RK_GATE(RK3588_CLK_BUSTIMER2, "clk_bustimer2", "clk_bus_timer_root", 1111 1.1 ryo CLKGATE_CON(0, 16), 1), 1112 1.1 ryo RK_GATE(RK3588_CLK_BUSTIMER3, "clk_bustimer3", "clk_bus_timer_root", 1113 1.1 ryo CLKGATE_CON(0, 16), 2), 1114 1.1 ryo RK_GATE(RK3588_CLK_BUSTIMER4, "clk_bustimer4", "clk_bus_timer_root", 1115 1.1 ryo CLKGATE_CON(0, 16), 3), 1116 1.1 ryo RK_GATE(RK3588_CLK_BUSTIMER5, "clk_bustimer5", "clk_bus_timer_root", 1117 1.1 ryo CLKGATE_CON(0, 16), 4), 1118 1.1 ryo RK_GATE(RK3588_CLK_BUSTIMER6, "clk_bustimer6", "clk_bus_timer_root", 1119 1.1 ryo CLKGATE_CON(0, 16), 5), 1120 1.1 ryo RK_GATE(RK3588_CLK_BUSTIMER7, "clk_bustimer7", "clk_bus_timer_root", 1121 1.1 ryo CLKGATE_CON(0, 16), 6), 1122 1.1 ryo RK_GATE(RK3588_CLK_BUSTIMER8, "clk_bustimer8", "clk_bus_timer_root", 1123 1.1 ryo CLKGATE_CON(0, 16), 7), 1124 1.1 ryo RK_GATE(RK3588_CLK_BUSTIMER9, "clk_bustimer9", "clk_bus_timer_root", 1125 1.1 ryo CLKGATE_CON(0, 16), 8), 1126 1.1 ryo RK_GATE(RK3588_CLK_BUSTIMER10, "clk_bustimer10", "clk_bus_timer_root", 1127 1.1 ryo CLKGATE_CON(0, 16), 9), 1128 1.1 ryo RK_GATE(RK3588_CLK_BUSTIMER11, "clk_bustimer11", "clk_bus_timer_root", 1129 1.1 ryo CLKGATE_CON(0, 16), 10), 1130 1.1 ryo RK_GATE(RK3588_PCLK_WDT0, "pclk_wdt0", "pclk_top_root", 1131 1.1 ryo CLKGATE_CON(0, 15), 0), 1132 1.1 ryo RK_GATE(RK3588_TCLK_WDT0, "tclk_wdt0", "xin24m", 1133 1.1 ryo CLKGATE_CON(0, 15), 1), 1134 1.1 ryo RK_GATE(RK3588_PCLK_CAN0, "pclk_can0", "pclk_top_root", 1135 1.1 ryo CLKGATE_CON(0, 11), 8), 1136 1.1 ryo RK_COMPOSITE(RK3588_CLK_CAN0, "clk_can0", 1137 1.1 ryo gpll_cpll_parents, 1138 1.1 ryo CLKSEL_CON(0, 39), __BITS(5,5), __BITS(4,0), 1139 1.1 ryo CLKGATE_CON(0, 11), __BIT(9), 1140 1.1 ryo 0), 1141 1.1 ryo RK_GATE(RK3588_PCLK_CAN1, "pclk_can1", "pclk_top_root", 1142 1.1 ryo CLKGATE_CON(0, 11), 10), 1143 1.1 ryo RK_COMPOSITE(RK3588_CLK_CAN1, "clk_can1", 1144 1.1 ryo gpll_cpll_parents, 1145 1.1 ryo CLKSEL_CON(0, 39), __BITS(11,11), __BITS(10,6), 1146 1.1 ryo CLKGATE_CON(0, 11), __BIT(11), 1147 1.1 ryo 0), 1148 1.1 ryo RK_GATE(RK3588_PCLK_CAN2, "pclk_can2", "pclk_top_root", 1149 1.1 ryo CLKGATE_CON(0, 11), 12), 1150 1.1 ryo RK_COMPOSITE(RK3588_CLK_CAN2, "clk_can2", 1151 1.1 ryo gpll_cpll_parents, 1152 1.1 ryo CLKSEL_CON(0, 40), __BITS(5,5), __BITS(4,0), 1153 1.1 ryo CLKGATE_CON(0, 11), __BIT(13), 1154 1.1 ryo 0), 1155 1.1 ryo RK_GATE(RK3588_ACLK_DECOM, "aclk_decom", "aclk_bus_root", 1156 1.1 ryo CLKGATE_CON(0, 17), 6), 1157 1.1 ryo RK_GATE(RK3588_PCLK_DECOM, "pclk_decom", "pclk_top_root", 1158 1.1 ryo CLKGATE_CON(0, 17), 7), 1159 1.1 ryo RK_COMPOSITE(RK3588_DCLK_DECOM, "dclk_decom", 1160 1.1 ryo gpll_spll_parents, 1161 1.1 ryo CLKSEL_CON(0, 62), __BITS(5,5), __BITS(4,0), 1162 1.1 ryo CLKGATE_CON(0, 17), __BIT(8), 1163 1.1 ryo 0), 1164 1.1 ryo RK_GATE(RK3588_ACLK_DMAC0, "aclk_dmac0", "aclk_bus_root", 1165 1.1 ryo CLKGATE_CON(0, 10), 5), 1166 1.1 ryo RK_GATE(RK3588_ACLK_DMAC1, "aclk_dmac1", "aclk_bus_root", 1167 1.1 ryo CLKGATE_CON(0, 10), 6), 1168 1.1 ryo RK_GATE(RK3588_ACLK_DMAC2, "aclk_dmac2", "aclk_bus_root", 1169 1.1 ryo CLKGATE_CON(0, 10), 7), 1170 1.1 ryo RK_GATE(RK3588_ACLK_GIC, "aclk_gic", "aclk_bus_root", 1171 1.1 ryo CLKGATE_CON(0, 10), 3), 1172 1.1 ryo RK_GATE(RK3588_PCLK_GPIO1, "pclk_gpio1", "pclk_top_root", 1173 1.1 ryo CLKGATE_CON(0, 16), 14), 1174 1.1 ryo RK_COMPOSITE(RK3588_DBCLK_GPIO1, "dbclk_gpio1", 1175 1.1 ryo mux_24m_32k_parents, 1176 1.1 ryo CLKSEL_CON(0, 60), __BITS(8,8), __BITS(7,3), 1177 1.1 ryo CLKGATE_CON(0, 16), __BIT(15), 1178 1.1 ryo 0), 1179 1.1 ryo RK_GATE(RK3588_PCLK_GPIO2, "pclk_gpio2", "pclk_top_root", 1180 1.1 ryo CLKGATE_CON(0, 17), 0), 1181 1.1 ryo RK_COMPOSITE(RK3588_DBCLK_GPIO2, "dbclk_gpio2", 1182 1.1 ryo mux_24m_32k_parents, 1183 1.1 ryo CLKSEL_CON(0, 60), __BITS(14,14), __BITS(13,9), 1184 1.1 ryo CLKGATE_CON(0, 17), __BIT(1), 1185 1.1 ryo 0), 1186 1.1 ryo RK_GATE(RK3588_PCLK_GPIO3, "pclk_gpio3", "pclk_top_root", 1187 1.1 ryo CLKGATE_CON(0, 17), 2), 1188 1.1 ryo RK_COMPOSITE(RK3588_DBCLK_GPIO3, "dbclk_gpio3", 1189 1.1 ryo mux_24m_32k_parents, 1190 1.1 ryo CLKSEL_CON(0, 61), __BITS(5,5), __BITS(4,0), 1191 1.1 ryo CLKGATE_CON(0, 17), __BIT(3), 1192 1.1 ryo 0), 1193 1.1 ryo RK_GATE(RK3588_PCLK_GPIO4, "pclk_gpio4", "pclk_top_root", 1194 1.1 ryo CLKGATE_CON(0, 17), 4), 1195 1.1 ryo RK_COMPOSITE(RK3588_DBCLK_GPIO4, "dbclk_gpio4", 1196 1.1 ryo mux_24m_32k_parents, 1197 1.1 ryo CLKSEL_CON(0, 61), __BITS(11,11), __BITS(10,6), 1198 1.1 ryo CLKGATE_CON(0, 17), __BIT(5), 1199 1.1 ryo 0), 1200 1.1 ryo RK_GATE(RK3588_PCLK_I2C1, "pclk_i2c1", "pclk_top_root", 1201 1.1 ryo CLKGATE_CON(0, 10), 8), 1202 1.1 ryo RK_GATE(RK3588_PCLK_I2C2, "pclk_i2c2", "pclk_top_root", 1203 1.1 ryo CLKGATE_CON(0, 10), 9), 1204 1.1 ryo RK_GATE(RK3588_PCLK_I2C3, "pclk_i2c3", "pclk_top_root", 1205 1.1 ryo CLKGATE_CON(0, 10), 10), 1206 1.1 ryo RK_GATE(RK3588_PCLK_I2C4, "pclk_i2c4", "pclk_top_root", 1207 1.1 ryo CLKGATE_CON(0, 10), 11), 1208 1.1 ryo RK_GATE(RK3588_PCLK_I2C5, "pclk_i2c5", "pclk_top_root", 1209 1.1 ryo CLKGATE_CON(0, 10), 12), 1210 1.1 ryo RK_GATE(RK3588_PCLK_I2C6, "pclk_i2c6", "pclk_top_root", 1211 1.1 ryo CLKGATE_CON(0, 10), 13), 1212 1.1 ryo RK_GATE(RK3588_PCLK_I2C7, "pclk_i2c7", "pclk_top_root", 1213 1.1 ryo CLKGATE_CON(0, 10), 14), 1214 1.1 ryo RK_GATE(RK3588_PCLK_I2C8, "pclk_i2c8", "pclk_top_root", 1215 1.1 ryo CLKGATE_CON(0, 10), 15), 1216 1.1 ryo RK_COMPOSITE_NODIV(RK3588_CLK_I2C1, "clk_i2c1", 1217 1.1 ryo mux_200m_100m_parents, 1218 1.1 ryo CLKSEL_CON(0, 38), __BITS(6,6), 1219 1.1 ryo CLKGATE_CON(0, 11), __BIT(0), 1220 1.1 ryo 0), 1221 1.1 ryo RK_COMPOSITE_NODIV(RK3588_CLK_I2C2, "clk_i2c2", 1222 1.1 ryo mux_200m_100m_parents, 1223 1.1 ryo CLKSEL_CON(0, 38), __BITS(7,7), 1224 1.1 ryo CLKGATE_CON(0, 11), __BIT(1), 1225 1.1 ryo 0), 1226 1.1 ryo RK_COMPOSITE_NODIV(RK3588_CLK_I2C3, "clk_i2c3", 1227 1.1 ryo mux_200m_100m_parents, 1228 1.1 ryo CLKSEL_CON(0, 38), __BITS(8,8), 1229 1.1 ryo CLKGATE_CON(0, 11), __BIT(2), 1230 1.1 ryo 0), 1231 1.1 ryo RK_COMPOSITE_NODIV(RK3588_CLK_I2C4, "clk_i2c4", 1232 1.1 ryo mux_200m_100m_parents, 1233 1.1 ryo CLKSEL_CON(0, 38), __BITS(9,9), 1234 1.1 ryo CLKGATE_CON(0, 11), __BIT(3), 1235 1.1 ryo 0), 1236 1.1 ryo RK_COMPOSITE_NODIV(RK3588_CLK_I2C5, "clk_i2c5", 1237 1.1 ryo mux_200m_100m_parents, 1238 1.1 ryo CLKSEL_CON(0, 38), __BITS(10,10), 1239 1.1 ryo CLKGATE_CON(0, 11), __BIT(4), 1240 1.1 ryo 0), 1241 1.1 ryo RK_COMPOSITE_NODIV(RK3588_CLK_I2C6, "clk_i2c6", 1242 1.1 ryo mux_200m_100m_parents, 1243 1.1 ryo CLKSEL_CON(0, 38), __BITS(11,11), 1244 1.1 ryo CLKGATE_CON(0, 11), __BIT(5), 1245 1.1 ryo 0), 1246 1.1 ryo RK_COMPOSITE_NODIV(RK3588_CLK_I2C7, "clk_i2c7", 1247 1.1 ryo mux_200m_100m_parents, 1248 1.1 ryo CLKSEL_CON(0, 38), __BITS(12,12), 1249 1.1 ryo CLKGATE_CON(0, 11), __BIT(6), 1250 1.1 ryo 0), 1251 1.1 ryo RK_COMPOSITE_NODIV(RK3588_CLK_I2C8, "clk_i2c8", 1252 1.1 ryo mux_200m_100m_parents, 1253 1.1 ryo CLKSEL_CON(0, 38), __BITS(13,13), 1254 1.1 ryo CLKGATE_CON(0, 11), __BIT(7), 1255 1.1 ryo 0), 1256 1.1 ryo RK_GATE(RK3588_PCLK_OTPC_NS, "pclk_otpc_ns", "pclk_top_root", 1257 1.1 ryo CLKGATE_CON(0, 18), 9), 1258 1.1 ryo RK_GATE(RK3588_CLK_OTPC_NS, "clk_otpc_ns", "xin24m", 1259 1.1 ryo CLKGATE_CON(0, 18), 10), 1260 1.1 ryo RK_GATE(RK3588_CLK_OTPC_ARB, "clk_otpc_arb", "xin24m", 1261 1.1 ryo CLKGATE_CON(0, 18), 11), 1262 1.1 ryo RK_GATE(RK3588_CLK_OTP_PHY_G, "clk_otp_phy_g", "xin24m", 1263 1.1 ryo CLKGATE_CON(0, 18), 13), 1264 1.1 ryo RK_GATE(RK3588_CLK_OTPC_AUTO_RD_G, "clk_otpc_auto_rd_g", "xin24m", 1265 1.1 ryo CLKGATE_CON(0, 18), 12), 1266 1.1 ryo RK_GATE(RK3588_PCLK_SARADC, "pclk_saradc", "pclk_top_root", 1267 1.1 ryo CLKGATE_CON(0, 11), 14), 1268 1.1 ryo RK_COMPOSITE(RK3588_CLK_SARADC, "clk_saradc", 1269 1.1 ryo gpll_24m_parents, 1270 1.1 ryo CLKSEL_CON(0, 40), __BITS(14,14), __BITS(13,6), 1271 1.1 ryo CLKGATE_CON(0, 11), __BIT(15), 1272 1.1 ryo 0), 1273 1.1 ryo RK_GATE(RK3588_PCLK_SPI0, "pclk_spi0", "pclk_top_root", 1274 1.1 ryo CLKGATE_CON(0, 14), 6), 1275 1.1 ryo RK_GATE(RK3588_PCLK_SPI1, "pclk_spi1", "pclk_top_root", 1276 1.1 ryo CLKGATE_CON(0, 14), 7), 1277 1.1 ryo RK_GATE(RK3588_PCLK_SPI2, "pclk_spi2", "pclk_top_root", 1278 1.1 ryo CLKGATE_CON(0, 14), 8), 1279 1.1 ryo RK_GATE(RK3588_PCLK_SPI3, "pclk_spi3", "pclk_top_root", 1280 1.1 ryo CLKGATE_CON(0, 14), 9), 1281 1.1 ryo RK_GATE(RK3588_PCLK_SPI4, "pclk_spi4", "pclk_top_root", 1282 1.1 ryo CLKGATE_CON(0, 14), 10), 1283 1.1 ryo RK_COMPOSITE_NODIV(RK3588_CLK_SPI0, "clk_spi0", 1284 1.1 ryo mux_200m_150m_24m_parents, 1285 1.1 ryo CLKSEL_CON(0, 59), __BITS(3,2), 1286 1.1 ryo CLKGATE_CON(0, 14), __BIT(11), 1287 1.1 ryo 0), 1288 1.1 ryo RK_COMPOSITE_NODIV(RK3588_CLK_SPI1, "clk_spi1", 1289 1.1 ryo mux_200m_150m_24m_parents, 1290 1.1 ryo CLKSEL_CON(0, 59), __BITS(5,4), 1291 1.1 ryo CLKGATE_CON(0, 14), __BIT(12), 1292 1.1 ryo 0), 1293 1.1 ryo RK_COMPOSITE_NODIV(RK3588_CLK_SPI2, "clk_spi2", 1294 1.1 ryo mux_200m_150m_24m_parents, 1295 1.1 ryo CLKSEL_CON(0, 59), __BITS(7,6), 1296 1.1 ryo CLKGATE_CON(0, 14), __BIT(13), 1297 1.1 ryo 0), 1298 1.1 ryo RK_COMPOSITE_NODIV(RK3588_CLK_SPI3, "clk_spi3", 1299 1.1 ryo mux_200m_150m_24m_parents, 1300 1.1 ryo CLKSEL_CON(0, 59), __BITS(9,8), 1301 1.1 ryo CLKGATE_CON(0, 14), __BIT(14), 1302 1.1 ryo 0), 1303 1.1 ryo RK_COMPOSITE_NODIV(RK3588_CLK_SPI4, "clk_spi4", 1304 1.1 ryo mux_200m_150m_24m_parents, 1305 1.1 ryo CLKSEL_CON(0, 59), __BITS(11,10), 1306 1.1 ryo CLKGATE_CON(0, 14), __BIT(15), 1307 1.1 ryo 0), 1308 1.1 ryo RK_GATE(RK3588_ACLK_SPINLOCK, "aclk_spinlock", "aclk_bus_root", 1309 1.1 ryo CLKGATE_CON(0, 18), 6), 1310 1.1 ryo RK_GATE(RK3588_PCLK_TSADC, "pclk_tsadc", "pclk_top_root", 1311 1.1 ryo CLKGATE_CON(0, 12), 0), 1312 1.1 ryo RK_COMPOSITE(RK3588_CLK_TSADC, "clk_tsadc", 1313 1.1 ryo gpll_24m_parents, 1314 1.1 ryo CLKSEL_CON(0, 41), __BITS(8,8), __BITS(7,0), 1315 1.1 ryo CLKGATE_CON(0, 12), __BIT(1), 1316 1.1 ryo 0), 1317 1.1 ryo RK_GATE(RK3588_PCLK_UART1, "pclk_uart1", "pclk_top_root", 1318 1.1 ryo CLKGATE_CON(0, 12), 2), 1319 1.1 ryo RK_GATE(RK3588_PCLK_UART2, "pclk_uart2", "pclk_top_root", 1320 1.1 ryo CLKGATE_CON(0, 12), 3), 1321 1.1 ryo RK_GATE(RK3588_PCLK_UART3, "pclk_uart3", "pclk_top_root", 1322 1.1 ryo CLKGATE_CON(0, 12), 4), 1323 1.1 ryo RK_GATE(RK3588_PCLK_UART4, "pclk_uart4", "pclk_top_root", 1324 1.1 ryo CLKGATE_CON(0, 12), 5), 1325 1.1 ryo RK_GATE(RK3588_PCLK_UART5, "pclk_uart5", "pclk_top_root", 1326 1.1 ryo CLKGATE_CON(0, 12), 6), 1327 1.1 ryo RK_GATE(RK3588_PCLK_UART6, "pclk_uart6", "pclk_top_root", 1328 1.1 ryo CLKGATE_CON(0, 12), 7), 1329 1.1 ryo RK_GATE(RK3588_PCLK_UART7, "pclk_uart7", "pclk_top_root", 1330 1.1 ryo CLKGATE_CON(0, 12), 8), 1331 1.1 ryo RK_GATE(RK3588_PCLK_UART8, "pclk_uart8", "pclk_top_root", 1332 1.1 ryo CLKGATE_CON(0, 12), 9), 1333 1.1 ryo RK_GATE(RK3588_PCLK_UART9, "pclk_uart9", "pclk_top_root", 1334 1.1 ryo CLKGATE_CON(0, 12), 10), 1335 1.1 ryo RK_COMPOSITE(RK3588_CLK_UART1_SRC, "clk_uart1_src", 1336 1.1 ryo gpll_cpll_parents, 1337 1.1 ryo CLKSEL_CON(0, 41), __BITS(14,14), __BITS(13,9), 1338 1.1 ryo CLKGATE_CON(0, 12), __BIT(11), 1339 1.1 ryo 0), 1340 1.1 ryo RK_COMPOSITE_FRAC(RK3588_CLK_UART1_FRAC, "clk_uart1_frac", 1341 1.1 ryo "clk_uart1_src", 1342 1.1 ryo CLKGATE_CON(0, 12), 1343 1.1 ryo RK_COMPOSITE_SET_RATE_PARENT), 1344 1.1 ryo RK_MUX(RK3588_CLK_UART1, "clk_uart1", clk_uart1_parents, 1345 1.1 ryo CLKSEL_CON(0, 43), __BITS(1,0)), 1346 1.1 ryo RK_GATE(RK3588_SCLK_UART1, "sclk_uart1", "clk_uart1", 1347 1.1 ryo CLKGATE_CON(0, 12), 13), 1348 1.1 ryo RK_COMPOSITE(RK3588_CLK_UART2_SRC, "clk_uart2_src", 1349 1.1 ryo gpll_cpll_parents, 1350 1.1 ryo CLKSEL_CON(0, 43), __BITS(7,7), __BITS(6,2), 1351 1.1 ryo CLKGATE_CON(0, 12), __BIT(14), 1352 1.1 ryo 0), 1353 1.1 ryo RK_COMPOSITE_FRAC(RK3588_CLK_UART2_FRAC, "clk_uart2_frac", 1354 1.1 ryo "clk_uart2_src", 1355 1.1 ryo CLKGATE_CON(0, 12), 1356 1.1 ryo RK_COMPOSITE_SET_RATE_PARENT), 1357 1.1 ryo RK_MUX(RK3588_CLK_UART2, "clk_uart2", clk_uart2_parents, 1358 1.1 ryo CLKSEL_CON(0, 45), __BITS(1,0)), 1359 1.1 ryo RK_GATE(RK3588_SCLK_UART2, "sclk_uart2", "clk_uart2", 1360 1.1 ryo CLKGATE_CON(0, 13), 0), 1361 1.1 ryo RK_COMPOSITE(RK3588_CLK_UART3_SRC, "clk_uart3_src", 1362 1.1 ryo gpll_cpll_parents, 1363 1.1 ryo CLKSEL_CON(0, 45), __BITS(7,7), __BITS(6,2), 1364 1.1 ryo CLKGATE_CON(0, 13), __BIT(1), 1365 1.1 ryo 0), 1366 1.1 ryo RK_COMPOSITE_FRAC(RK3588_CLK_UART3_FRAC, "clk_uart3_frac", 1367 1.1 ryo "clk_uart3_src", 1368 1.1 ryo CLKGATE_CON(0, 13), 1369 1.1 ryo RK_COMPOSITE_SET_RATE_PARENT), 1370 1.1 ryo RK_MUX(RK3588_CLK_UART3, "clk_uart3", clk_uart3_parents, 1371 1.1 ryo CLKSEL_CON(0, 47), __BITS(1,0)), 1372 1.1 ryo RK_GATE(RK3588_SCLK_UART3, "sclk_uart3", "clk_uart3", 1373 1.1 ryo CLKGATE_CON(0, 13), 3), 1374 1.1 ryo RK_COMPOSITE(RK3588_CLK_UART4_SRC, "clk_uart4_src", 1375 1.1 ryo gpll_cpll_parents, 1376 1.1 ryo CLKSEL_CON(0, 47), __BITS(7,7), __BITS(6,2), 1377 1.1 ryo CLKGATE_CON(0, 13), __BIT(4), 1378 1.1 ryo 0), 1379 1.1 ryo RK_COMPOSITE_FRAC(RK3588_CLK_UART4_FRAC, "clk_uart4_frac", 1380 1.1 ryo "clk_uart4_src", 1381 1.1 ryo CLKGATE_CON(0, 13), 1382 1.1 ryo RK_COMPOSITE_SET_RATE_PARENT), 1383 1.1 ryo RK_MUX(RK3588_CLK_UART4, "clk_uart4", clk_uart4_parents, 1384 1.1 ryo CLKSEL_CON(0, 49), __BITS(1,0)), 1385 1.1 ryo RK_GATE(RK3588_SCLK_UART4, "sclk_uart4", "clk_uart4", 1386 1.1 ryo CLKGATE_CON(0, 13), 6), 1387 1.1 ryo RK_COMPOSITE(RK3588_CLK_UART5_SRC, "clk_uart5_src", 1388 1.1 ryo gpll_cpll_parents, 1389 1.1 ryo CLKSEL_CON(0, 49), __BITS(7,7), __BITS(6,2), 1390 1.1 ryo CLKGATE_CON(0, 13), __BIT(7), 1391 1.1 ryo 0), 1392 1.1 ryo RK_COMPOSITE_FRAC(RK3588_CLK_UART5_FRAC, "clk_uart5_frac", 1393 1.1 ryo "clk_uart5_src", 1394 1.1 ryo CLKGATE_CON(0, 13), 1395 1.1 ryo RK_COMPOSITE_SET_RATE_PARENT), 1396 1.1 ryo RK_MUX(RK3588_CLK_UART5, "clk_uart5", clk_uart5_parents, 1397 1.1 ryo CLKSEL_CON(0, 51), __BITS(1,0)), 1398 1.1 ryo RK_GATE(RK3588_SCLK_UART5, "sclk_uart5", "clk_uart5", 1399 1.1 ryo CLKGATE_CON(0, 13), 9), 1400 1.1 ryo RK_COMPOSITE(RK3588_CLK_UART6_SRC, "clk_uart6_src", 1401 1.1 ryo gpll_cpll_parents, 1402 1.1 ryo CLKSEL_CON(0, 51), __BITS(7,7), __BITS(6,2), 1403 1.1 ryo CLKGATE_CON(0, 13), __BIT(10), 1404 1.1 ryo 0), 1405 1.1 ryo RK_COMPOSITE_FRAC(RK3588_CLK_UART6_FRAC, "clk_uart6_frac", 1406 1.1 ryo "clk_uart6_src", 1407 1.1 ryo CLKGATE_CON(0, 13), 1408 1.1 ryo RK_COMPOSITE_SET_RATE_PARENT), 1409 1.1 ryo RK_MUX(RK3588_CLK_UART6, "clk_uart6", clk_uart6_parents, 1410 1.1 ryo CLKSEL_CON(0, 53), __BITS(1,0)), 1411 1.1 ryo RK_GATE(RK3588_SCLK_UART6, "sclk_uart6", "clk_uart6", 1412 1.1 ryo CLKGATE_CON(0, 13), 12), 1413 1.1 ryo RK_COMPOSITE(RK3588_CLK_UART7_SRC, "clk_uart7_src", 1414 1.1 ryo gpll_cpll_parents, 1415 1.1 ryo CLKSEL_CON(0, 53), __BITS(7,7), __BITS(6,2), 1416 1.1 ryo CLKGATE_CON(0, 13), __BIT(13), 1417 1.1 ryo 0), 1418 1.1 ryo RK_COMPOSITE_FRAC(RK3588_CLK_UART7_FRAC, "clk_uart7_frac", 1419 1.1 ryo "clk_uart7_src", 1420 1.1 ryo CLKGATE_CON(0, 13), 1421 1.1 ryo RK_COMPOSITE_SET_RATE_PARENT), 1422 1.1 ryo RK_MUX(RK3588_CLK_UART7, "clk_uart7", clk_uart7_parents, 1423 1.1 ryo CLKSEL_CON(0, 55), __BITS(1,0)), 1424 1.1 ryo RK_GATE(RK3588_SCLK_UART7, "sclk_uart7", "clk_uart7", 1425 1.1 ryo CLKGATE_CON(0, 13), 15), 1426 1.1 ryo RK_COMPOSITE(RK3588_CLK_UART8_SRC, "clk_uart8_src", 1427 1.1 ryo gpll_cpll_parents, 1428 1.1 ryo CLKSEL_CON(0, 55), __BITS(7,7), __BITS(6,2), 1429 1.1 ryo CLKGATE_CON(0, 14), __BIT(0), 1430 1.1 ryo 0), 1431 1.1 ryo RK_COMPOSITE_FRAC(RK3588_CLK_UART8_FRAC, "clk_uart8_frac", 1432 1.1 ryo "clk_uart8_src", 1433 1.1 ryo CLKGATE_CON(0, 14), 1434 1.1 ryo RK_COMPOSITE_SET_RATE_PARENT), 1435 1.1 ryo RK_MUX(RK3588_CLK_UART8, "clk_uart8", clk_uart8_parents, 1436 1.1 ryo CLKSEL_CON(0, 57), __BITS(1,0)), 1437 1.1 ryo RK_GATE(RK3588_SCLK_UART8, "sclk_uart8", "clk_uart8", 1438 1.1 ryo CLKGATE_CON(0, 14), 2), 1439 1.1 ryo RK_COMPOSITE(RK3588_CLK_UART9_SRC, "clk_uart9_src", 1440 1.1 ryo gpll_cpll_parents, 1441 1.1 ryo CLKSEL_CON(0, 57), __BITS(7,7), __BITS(6,2), 1442 1.1 ryo CLKGATE_CON(0, 14), __BIT(3), 1443 1.1 ryo 0), 1444 1.1 ryo RK_COMPOSITE_FRAC(RK3588_CLK_UART9_FRAC, "clk_uart9_frac", 1445 1.1 ryo "clk_uart9_src", 1446 1.1 ryo CLKGATE_CON(0, 14), 1447 1.1 ryo RK_COMPOSITE_SET_RATE_PARENT), 1448 1.1 ryo RK_MUX(RK3588_CLK_UART9, "clk_uart9", clk_uart9_parents, 1449 1.1 ryo CLKSEL_CON(0, 59), __BITS(1,0)), 1450 1.1 ryo RK_GATE(RK3588_SCLK_UART9, "sclk_uart9", "clk_uart9", 1451 1.1 ryo CLKGATE_CON(0, 14), 5), 1452 1.1 ryo RK_COMPOSITE_NODIV(RK3588_ACLK_CENTER_ROOT, "aclk_center_root", 1453 1.1 ryo mux_700m_400m_200m_24m_parents, 1454 1.1 ryo CLKSEL_CON(0, 165), __BITS(1,0), 1455 1.1 ryo CLKGATE_CON(0, 69), __BIT(0), 1456 1.1 ryo 0), 1457 1.1 ryo RK_COMPOSITE_NODIV(RK3588_ACLK_CENTER_LOW_ROOT, "aclk_center_low_root", 1458 1.1 ryo mux_500m_250m_100m_24m_parents, 1459 1.1 ryo CLKSEL_CON(0, 165), __BITS(3,2), 1460 1.1 ryo CLKGATE_CON(0, 69), __BIT(1), 1461 1.1 ryo 0), 1462 1.1 ryo RK_COMPOSITE_NODIV(RK3588_HCLK_CENTER_ROOT, "hclk_center_root", 1463 1.1 ryo mux_400m_200m_100m_24m_parents, 1464 1.1 ryo CLKSEL_CON(0, 165), __BITS(5,4), 1465 1.1 ryo CLKGATE_CON(0, 69), __BIT(2), 1466 1.1 ryo 0), 1467 1.1 ryo RK_COMPOSITE_NODIV(RK3588_PCLK_CENTER_ROOT, "pclk_center_root", 1468 1.1 ryo mux_200m_100m_50m_24m_parents, 1469 1.1 ryo CLKSEL_CON(0, 165), __BITS(7,6), 1470 1.1 ryo CLKGATE_CON(0, 69), __BIT(3), 1471 1.1 ryo 0), 1472 1.1 ryo RK_GATE(RK3588_ACLK_DMA2DDR, "aclk_dma2ddr", "aclk_center_root", 1473 1.1 ryo CLKGATE_CON(0, 69), 5), 1474 1.1 ryo RK_GATE(RK3588_ACLK_DDR_SHAREMEM, "aclk_ddr_sharemem", 1475 1.1 ryo "aclk_center_low_root", 1476 1.1 ryo CLKGATE_CON(0, 69), 6), 1477 1.1 ryo RK_COMPOSITE_NODIV(RK3588_ACLK_CENTER_S200_ROOT, 1478 1.1 ryo "aclk_center_s200_root", 1479 1.1 ryo mux_200m_100m_50m_24m_parents, 1480 1.1 ryo CLKSEL_CON(0, 165), __BITS(9,8), 1481 1.1 ryo CLKGATE_CON(0, 69), __BIT(8), 1482 1.1 ryo 0), 1483 1.1 ryo RK_COMPOSITE_NODIV(RK3588_ACLK_CENTER_S400_ROOT, 1484 1.1 ryo "aclk_center_s400_root", mux_400m_200m_100m_24m_parents, 1485 1.1 ryo CLKSEL_CON(0, 165), __BITS(11,10), 1486 1.1 ryo CLKGATE_CON(0, 69), __BIT(9), 1487 1.1 ryo 0), 1488 1.1 ryo RK_GATE(RK3588_FCLK_DDR_CM0_CORE, "fclk_ddr_cm0_core", 1489 1.1 ryo "hclk_center_root", 1490 1.1 ryo CLKGATE_CON(0, 69), 14), 1491 1.1 ryo RK_COMPOSITE_NODIV(RK3588_CLK_DDR_TIMER_ROOT, "clk_ddr_timer_root", 1492 1.1 ryo mux_24m_100m_parents, 1493 1.1 ryo CLKSEL_CON(0, 165), __BITS(12,12), 1494 1.1 ryo CLKGATE_CON(0, 69), __BIT(15), 1495 1.1 ryo 0), 1496 1.1 ryo RK_GATE(RK3588_CLK_DDR_TIMER0, "clk_ddr_timer0", "clk_ddr_timer_root", 1497 1.1 ryo CLKGATE_CON(0, 70), 0), 1498 1.1 ryo RK_GATE(RK3588_CLK_DDR_TIMER1, "clk_ddr_timer1", "clk_ddr_timer_root", 1499 1.1 ryo CLKGATE_CON(0, 70), 1), 1500 1.1 ryo RK_GATE(RK3588_TCLK_WDT_DDR, "tclk_wdt_ddr", "xin24m", 1501 1.1 ryo CLKGATE_CON(0, 70), 2), 1502 1.1 ryo RK_COMPOSITE(RK3588_CLK_DDR_CM0_RTC, "clk_ddr_cm0_rtc", 1503 1.1 ryo mux_24m_32k_parents, 1504 1.1 ryo CLKSEL_CON(0, 166), __BITS(5,5), __BITS(4,0), 1505 1.1 ryo CLKGATE_CON(0, 70), __BIT(4), 1506 1.1 ryo 0), 1507 1.1 ryo RK_GATE(RK3588_PCLK_WDT, "pclk_wdt", "pclk_center_root", 1508 1.1 ryo CLKGATE_CON(0, 70), 7), 1509 1.1 ryo RK_GATE(RK3588_PCLK_TIMER, "pclk_timer", "pclk_center_root", 1510 1.1 ryo CLKGATE_CON(0, 70), 8), 1511 1.1 ryo RK_GATE(RK3588_PCLK_DMA2DDR, "pclk_dma2ddr", "pclk_center_root", 1512 1.1 ryo CLKGATE_CON(0, 70), 9), 1513 1.1 ryo RK_GATE(RK3588_PCLK_SHAREMEM, "pclk_sharemem", "pclk_center_root", 1514 1.1 ryo CLKGATE_CON(0, 70), 10), 1515 1.1 ryo RK_COMPOSITE(RK3588_CLK_GPU_SRC, "clk_gpu_src", 1516 1.1 ryo gpll_cpll_aupll_npll_spll_parents, 1517 1.1 ryo CLKSEL_CON(0, 158), __BITS(7,5), __BITS(4,0), 1518 1.1 ryo CLKGATE_CON(0, 66), __BIT(1), 1519 1.1 ryo 0), 1520 1.1 ryo RK_GATE(RK3588_CLK_GPU, "clk_gpu", "clk_gpu_src", 1521 1.1 ryo CLKGATE_CON(0, 66), 4), 1522 1.1 ryo RK_GATE(RK3588_CLK_GPU_COREGROUP, "clk_gpu_coregroup", "clk_gpu_src", 1523 1.1 ryo CLKGATE_CON(0, 66), 6), 1524 1.1 ryo RK_COMPOSITE_NOMUX(RK3588_CLK_GPU_STACKS, "clk_gpu_stacks", 1525 1.1 ryo "clk_gpu_src", 1526 1.1 ryo CLKSEL_CON(0, 159), __BITS(4,0), 1527 1.1 ryo CLKGATE_CON(0, 66), __BIT(7), 1528 1.1 ryo 0), 1529 1.1 ryo RK_GATE(RK3588_CLK_GPU_PVTM, "clk_gpu_pvtm", "xin24m", 1530 1.1 ryo CLKGATE_CON(0, 67), 0), 1531 1.1 ryo RK_GATE(RK3588_CLK_CORE_GPU_PVTM, "clk_core_gpu_pvtm", "clk_gpu_src", 1532 1.1 ryo CLKGATE_CON(0, 67), 1), 1533 1.1 ryo RK_COMPOSITE(RK3588_ACLK_ISP1_ROOT, "aclk_isp1_root", 1534 1.1 ryo gpll_cpll_aupll_spll_parents, 1535 1.1 ryo CLKSEL_CON(0, 67), __BITS(6,5), __BITS(4,0), 1536 1.1 ryo CLKGATE_CON(0, 26), __BIT(0), 1537 1.1 ryo 0), 1538 1.1 ryo RK_COMPOSITE_NODIV(RK3588_HCLK_ISP1_ROOT, "hclk_isp1_root", 1539 1.1 ryo mux_200m_100m_50m_24m_parents, 1540 1.1 ryo CLKSEL_CON(0, 67), __BITS(8,7), 1541 1.1 ryo CLKGATE_CON(0, 26), __BIT(1), 1542 1.1 ryo 0), 1543 1.1 ryo RK_COMPOSITE(RK3588_CLK_ISP1_CORE, "clk_isp1_core", 1544 1.1 ryo gpll_cpll_aupll_spll_parents, 1545 1.1 ryo CLKSEL_CON(0, 67), __BITS(15,14), __BITS(13,9), 1546 1.1 ryo CLKGATE_CON(0, 26), __BIT(2), 1547 1.1 ryo 0), 1548 1.1 ryo RK_GATE(RK3588_CLK_ISP1_CORE_MARVIN, "clk_isp1_core_marvin", 1549 1.1 ryo "clk_isp1_core", 1550 1.1 ryo CLKGATE_CON(0, 26), 3), 1551 1.1 ryo RK_GATE(RK3588_CLK_ISP1_CORE_VICAP, "clk_isp1_core_vicap", 1552 1.1 ryo "clk_isp1_core", 1553 1.1 ryo CLKGATE_CON(0, 26), 4), 1554 1.1 ryo RK_COMPOSITE_NODIV(RK3588_HCLK_NPU_ROOT, "hclk_npu_root", 1555 1.1 ryo mux_200m_100m_50m_24m_parents, 1556 1.1 ryo CLKSEL_CON(0, 73), __BITS(1,0), 1557 1.1 ryo CLKGATE_CON(0, 29), __BIT(0), 1558 1.1 ryo 0), 1559 1.1 ryo RK_COMPOSITE(RK3588_CLK_NPU_DSU0, "clk_npu_dsu0", 1560 1.1 ryo gpll_cpll_aupll_npll_spll_parents, 1561 1.1 ryo CLKSEL_CON(0, 73), __BITS(9,7), __BITS(6,2), 1562 1.1 ryo CLKGATE_CON(0, 29), __BIT(1), 1563 1.1 ryo 0), 1564 1.1 ryo RK_COMPOSITE_NODIV(RK3588_PCLK_NPU_ROOT, "pclk_npu_root", 1565 1.1 ryo mux_100m_50m_24m_parents, 1566 1.1 ryo CLKSEL_CON(0, 74), __BITS(2,1), 1567 1.1 ryo CLKGATE_CON(0, 29), __BIT(4), 1568 1.1 ryo 0), 1569 1.1 ryo RK_GATE(RK3588_ACLK_NPU1, "aclk_npu1", "clk_npu_dsu0", 1570 1.1 ryo CLKGATE_CON(0, 27), 0), 1571 1.1 ryo RK_GATE(RK3588_HCLK_NPU1, "hclk_npu1", "hclk_npu_root", 1572 1.1 ryo CLKGATE_CON(0, 27), 2), 1573 1.1 ryo RK_GATE(RK3588_ACLK_NPU2, "aclk_npu2", "clk_npu_dsu0", 1574 1.1 ryo CLKGATE_CON(0, 28), 0), 1575 1.1 ryo RK_GATE(RK3588_HCLK_NPU2, "hclk_npu2", "hclk_npu_root", 1576 1.1 ryo CLKGATE_CON(0, 28), 2), 1577 1.1 ryo RK_COMPOSITE_NODIV(RK3588_HCLK_NPU_CM0_ROOT, "hclk_npu_cm0_root", 1578 1.1 ryo mux_400m_200m_100m_24m_parents, 1579 1.1 ryo CLKSEL_CON(0, 74), __BITS(6,5), 1580 1.1 ryo CLKGATE_CON(0, 30), __BIT(1), 1581 1.1 ryo 0), 1582 1.1 ryo RK_GATE(RK3588_FCLK_NPU_CM0_CORE, "fclk_npu_cm0_core", 1583 1.1 ryo "hclk_npu_cm0_root", 1584 1.1 ryo CLKGATE_CON(0, 30), 3), 1585 1.1 ryo RK_COMPOSITE(RK3588_CLK_NPU_CM0_RTC, "clk_npu_cm0_rtc", 1586 1.1 ryo mux_24m_32k_parents, 1587 1.1 ryo CLKSEL_CON(0, 74), __BITS(12,12), __BITS(11,7), 1588 1.1 ryo CLKGATE_CON(0, 30), __BIT(5), 1589 1.1 ryo 0), 1590 1.1 ryo RK_GATE(RK3588_PCLK_NPU_PVTM, "pclk_npu_pvtm", "pclk_npu_root", 1591 1.1 ryo CLKGATE_CON(0, 29), 12), 1592 1.1 ryo RK_GATE(RK3588_PCLK_NPU_GRF, "pclk_npu_grf", "pclk_npu_root", 1593 1.1 ryo CLKGATE_CON(0, 29), 13), 1594 1.1 ryo RK_GATE(RK3588_CLK_NPU_PVTM, "clk_npu_pvtm", "xin24m", 1595 1.1 ryo CLKGATE_CON(0, 29), 14), 1596 1.1 ryo RK_GATE(RK3588_CLK_CORE_NPU_PVTM, "clk_core_npu_pvtm", "clk_npu_dsu0", 1597 1.1 ryo CLKGATE_CON(0, 29), 15), 1598 1.1 ryo RK_GATE(RK3588_ACLK_NPU0, "aclk_npu0", "clk_npu_dsu0", 1599 1.1 ryo CLKGATE_CON(0, 30), 6), 1600 1.1 ryo RK_GATE(RK3588_HCLK_NPU0, "hclk_npu0", "hclk_npu_root", 1601 1.1 ryo CLKGATE_CON(0, 30), 8), 1602 1.1 ryo RK_GATE(RK3588_PCLK_NPU_TIMER, "pclk_npu_timer", "pclk_npu_root", 1603 1.1 ryo CLKGATE_CON(0, 29), 6), 1604 1.1 ryo RK_COMPOSITE_NODIV(RK3588_CLK_NPUTIMER_ROOT, "clk_nputimer_root", 1605 1.1 ryo mux_24m_100m_parents, 1606 1.1 ryo CLKSEL_CON(0, 74), __BITS(3,3), 1607 1.1 ryo CLKGATE_CON(0, 29), __BIT(7), 1608 1.1 ryo 0), 1609 1.1 ryo RK_GATE(RK3588_CLK_NPUTIMER0, "clk_nputimer0", "clk_nputimer_root", 1610 1.1 ryo CLKGATE_CON(0, 29), 8), 1611 1.1 ryo RK_GATE(RK3588_CLK_NPUTIMER1, "clk_nputimer1", "clk_nputimer_root", 1612 1.1 ryo CLKGATE_CON(0, 29), 9), 1613 1.1 ryo RK_GATE(RK3588_PCLK_NPU_WDT, "pclk_npu_wdt", "pclk_npu_root", 1614 1.1 ryo CLKGATE_CON(0, 29), 10), 1615 1.1 ryo RK_GATE(RK3588_TCLK_NPU_WDT, "tclk_npu_wdt", "xin24m", 1616 1.1 ryo CLKGATE_CON(0, 29), 11), 1617 1.1 ryo RK_COMPOSITE_NODIV(RK3588_HCLK_NVM_ROOT, "hclk_nvm_root", 1618 1.1 ryo mux_200m_100m_50m_24m_parents, 1619 1.1 ryo CLKSEL_CON(0, 77), __BITS(1,0), 1620 1.1 ryo CLKGATE_CON(0, 31), __BIT(0), 1621 1.1 ryo 0), 1622 1.1 ryo RK_COMPOSITE(RK3588_ACLK_NVM_ROOT, "aclk_nvm_root", 1623 1.1 ryo gpll_cpll_parents, 1624 1.1 ryo CLKSEL_CON(0, 77), __BITS(7,7), __BITS(6,2), 1625 1.1 ryo CLKGATE_CON(0, 31), __BIT(1), 1626 1.1 ryo 0), 1627 1.1 ryo RK_GATE(RK3588_ACLK_EMMC, "aclk_emmc", "aclk_nvm_root", 1628 1.1 ryo CLKGATE_CON(0, 31), 5), 1629 1.1 ryo RK_COMPOSITE(RK3588_CCLK_EMMC, "cclk_emmc", 1630 1.1 ryo gpll_cpll_24m_parents, 1631 1.1 ryo CLKSEL_CON(0, 77), __BITS(15,14), __BITS(13,8), 1632 1.1 ryo CLKGATE_CON(0, 31), __BIT(6), 1633 1.1 ryo 0), 1634 1.1 ryo RK_COMPOSITE(RK3588_BCLK_EMMC, "bclk_emmc", 1635 1.1 ryo gpll_cpll_parents, 1636 1.1 ryo CLKSEL_CON(0, 78), __BITS(5,5), __BITS(4,0), 1637 1.1 ryo CLKGATE_CON(0, 31), __BIT(7), 1638 1.1 ryo 0), 1639 1.1 ryo RK_GATE(RK3588_TMCLK_EMMC, "tmclk_emmc", "xin24m", 1640 1.1 ryo CLKGATE_CON(0, 31), 8), 1641 1.1 ryo RK_COMPOSITE(RK3588_SCLK_SFC, "sclk_sfc", 1642 1.1 ryo gpll_cpll_24m_parents, 1643 1.1 ryo CLKSEL_CON(0, 78), __BITS(13,12), __BITS(11,6), 1644 1.1 ryo CLKGATE_CON(0, 31), __BIT(9), 1645 1.1 ryo 0), 1646 1.1 ryo RK_COMPOSITE(RK3588_CLK_GMAC0_PTP_REF, "clk_gmac0_ptp_ref", 1647 1.1 ryo clk_gmac0_ptp_ref_parents, 1648 1.1 ryo CLKSEL_CON(0, 81), __BITS(6,6), __BITS(5,0), 1649 1.1 ryo CLKGATE_CON(0, 34), __BIT(10), 1650 1.1 ryo 0), 1651 1.1 ryo RK_COMPOSITE(RK3588_CLK_GMAC1_PTP_REF, "clk_gmac1_ptp_ref", 1652 1.1 ryo clk_gmac1_ptp_ref_parents, 1653 1.1 ryo CLKSEL_CON(0, 81), __BITS(13,13), __BITS(12,7), 1654 1.1 ryo CLKGATE_CON(0, 34), __BIT(11), 1655 1.1 ryo 0), 1656 1.1 ryo RK_COMPOSITE(RK3588_CLK_GMAC_125M, "clk_gmac_125m", 1657 1.1 ryo gpll_cpll_parents, 1658 1.1 ryo CLKSEL_CON(0, 83), __BITS(15,15), __BITS(14,8), 1659 1.1 ryo CLKGATE_CON(0, 35), __BIT(5), 1660 1.1 ryo 0), 1661 1.1 ryo RK_COMPOSITE(RK3588_CLK_GMAC_50M, "clk_gmac_50m", 1662 1.1 ryo gpll_cpll_parents, 1663 1.1 ryo CLKSEL_CON(0, 84), __BITS(7,7), __BITS(6,0), 1664 1.1 ryo CLKGATE_CON(0, 35), __BIT(6), 1665 1.1 ryo 0), 1666 1.1 ryo RK_COMPOSITE(RK3588_ACLK_PCIE_ROOT, "aclk_pcie_root", 1667 1.1 ryo gpll_cpll_parents, 1668 1.1 ryo CLKSEL_CON(0, 80), __BITS(7,7), __BITS(6,2), 1669 1.1 ryo CLKGATE_CON(0, 32), __BIT(6), 1670 1.1 ryo 0), 1671 1.1 ryo RK_COMPOSITE(RK3588_ACLK_PHP_ROOT, "aclk_php_root", 1672 1.1 ryo gpll_cpll_parents, 1673 1.1 ryo CLKSEL_CON(0, 80), __BITS(13,13), __BITS(12,8), 1674 1.1 ryo CLKGATE_CON(0, 32), __BIT(7), 1675 1.1 ryo 0), 1676 1.1 ryo RK_COMPOSITE_NODIV(RK3588_PCLK_PHP_ROOT, "pclk_php_root", 1677 1.1 ryo mux_150m_50m_24m_parents, 1678 1.1 ryo CLKSEL_CON(0, 80), __BITS(1,0), 1679 1.1 ryo CLKGATE_CON(0, 32), __BIT(0), 1680 1.1 ryo 0), 1681 1.1 ryo RK_GATE(RK3588_ACLK_PHP_GIC_ITS, "aclk_php_gic_its", "aclk_pcie_root", 1682 1.1 ryo CLKGATE_CON(0, 34), 6), 1683 1.1 ryo RK_GATE(RK3588_ACLK_PCIE_BRIDGE, "aclk_pcie_bridge", "aclk_pcie_root", 1684 1.1 ryo CLKGATE_CON(0, 32), 8), 1685 1.1 ryo RK_GATE(RK3588_ACLK_MMU_PCIE, "aclk_mmu_pcie", "aclk_pcie_bridge", 1686 1.1 ryo CLKGATE_CON(0, 34), 7), 1687 1.1 ryo RK_GATE(RK3588_ACLK_MMU_PHP, "aclk_mmu_php", "aclk_php_root", 1688 1.1 ryo CLKGATE_CON(0, 34), 8), 1689 1.1 ryo RK_GATE(RK3588_ACLK_PCIE_4L_DBI, "aclk_pcie_4l_dbi", "aclk_php_root", 1690 1.1 ryo CLKGATE_CON(0, 32), 13), 1691 1.1 ryo RK_GATE(RK3588_ACLK_PCIE_2L_DBI, "aclk_pcie_2l_dbi", "aclk_php_root", 1692 1.1 ryo CLKGATE_CON(0, 32), 14), 1693 1.1 ryo RK_GATE(RK3588_ACLK_PCIE_1L0_DBI, "aclk_pcie_1l0_dbi", "aclk_php_root", 1694 1.1 ryo CLKGATE_CON(0, 32), 15), 1695 1.1 ryo RK_GATE(RK3588_ACLK_PCIE_1L1_DBI, "aclk_pcie_1l1_dbi", "aclk_php_root", 1696 1.1 ryo CLKGATE_CON(0, 33), 0), 1697 1.1 ryo RK_GATE(RK3588_ACLK_PCIE_1L2_DBI, "aclk_pcie_1l2_dbi", "aclk_php_root", 1698 1.1 ryo CLKGATE_CON(0, 33), 1), 1699 1.1 ryo RK_GATE(RK3588_ACLK_PCIE_4L_MSTR, "aclk_pcie_4l_mstr", "aclk_mmu_pcie", 1700 1.1 ryo CLKGATE_CON(0, 33), 2), 1701 1.1 ryo RK_GATE(RK3588_ACLK_PCIE_2L_MSTR, "aclk_pcie_2l_mstr", "aclk_mmu_pcie", 1702 1.1 ryo CLKGATE_CON(0, 33), 3), 1703 1.1 ryo RK_GATE(RK3588_ACLK_PCIE_1L0_MSTR, "aclk_pcie_1l0_mstr", 1704 1.1 ryo "aclk_mmu_pcie", 1705 1.1 ryo CLKGATE_CON(0, 33), 4), 1706 1.1 ryo RK_GATE(RK3588_ACLK_PCIE_1L1_MSTR, "aclk_pcie_1l1_mstr", 1707 1.1 ryo "aclk_mmu_pcie", 1708 1.1 ryo CLKGATE_CON(0, 33), 5), 1709 1.1 ryo RK_GATE(RK3588_ACLK_PCIE_1L2_MSTR, "aclk_pcie_1l2_mstr", 1710 1.1 ryo "aclk_mmu_pcie", 1711 1.1 ryo CLKGATE_CON(0, 33), 6), 1712 1.1 ryo RK_GATE(RK3588_ACLK_PCIE_4L_SLV, "aclk_pcie_4l_slv", "aclk_php_root", 1713 1.1 ryo CLKGATE_CON(0, 33), 7), 1714 1.1 ryo RK_GATE(RK3588_ACLK_PCIE_2L_SLV, "aclk_pcie_2l_slv", "aclk_php_root", 1715 1.1 ryo CLKGATE_CON(0, 33), 8), 1716 1.1 ryo RK_GATE(RK3588_ACLK_PCIE_1L0_SLV, "aclk_pcie_1l0_slv", "aclk_php_root", 1717 1.1 ryo CLKGATE_CON(0, 33), 9), 1718 1.1 ryo RK_GATE(RK3588_ACLK_PCIE_1L1_SLV, "aclk_pcie_1l1_slv", "aclk_php_root", 1719 1.1 ryo CLKGATE_CON(0, 33), 10), 1720 1.1 ryo RK_GATE(RK3588_ACLK_PCIE_1L2_SLV, "aclk_pcie_1l2_slv", "aclk_php_root", 1721 1.1 ryo CLKGATE_CON(0, 33), 11), 1722 1.1 ryo RK_GATE(RK3588_PCLK_PCIE_4L, "pclk_pcie_4l", "pclk_php_root", 1723 1.1 ryo CLKGATE_CON(0, 33), 12), 1724 1.1 ryo RK_GATE(RK3588_PCLK_PCIE_2L, "pclk_pcie_2l", "pclk_php_root", 1725 1.1 ryo CLKGATE_CON(0, 33), 13), 1726 1.1 ryo RK_GATE(RK3588_PCLK_PCIE_1L0, "pclk_pcie_1l0", "pclk_php_root", 1727 1.1 ryo CLKGATE_CON(0, 33), 14), 1728 1.1 ryo RK_GATE(RK3588_PCLK_PCIE_1L1, "pclk_pcie_1l1", "pclk_php_root", 1729 1.1 ryo CLKGATE_CON(0, 33), 15), 1730 1.1 ryo RK_GATE(RK3588_PCLK_PCIE_1L2, "pclk_pcie_1l2", "pclk_php_root", 1731 1.1 ryo CLKGATE_CON(0, 34), 0), 1732 1.1 ryo RK_GATE(RK3588_CLK_PCIE_AUX0, "clk_pcie_aux0", "xin24m", 1733 1.1 ryo CLKGATE_CON(0, 34), 1), 1734 1.1 ryo RK_GATE(RK3588_CLK_PCIE_AUX1, "clk_pcie_aux1", "xin24m", 1735 1.1 ryo CLKGATE_CON(0, 34), 2), 1736 1.1 ryo RK_GATE(RK3588_CLK_PCIE_AUX2, "clk_pcie_aux2", "xin24m", 1737 1.1 ryo CLKGATE_CON(0, 34), 3), 1738 1.1 ryo RK_GATE(RK3588_CLK_PCIE_AUX3, "clk_pcie_aux3", "xin24m", 1739 1.1 ryo CLKGATE_CON(0, 34), 4), 1740 1.1 ryo RK_GATE(RK3588_CLK_PCIE_AUX4, "clk_pcie_aux4", "xin24m", 1741 1.1 ryo CLKGATE_CON(0, 34), 5), 1742 1.1 ryo RK_GATE(RK3588_CLK_PIPEPHY0_REF, "clk_pipephy0_ref", "xin24m", 1743 1.1 ryo CLKGATE_CON(0, 37), 0), 1744 1.1 ryo RK_GATE(RK3588_CLK_PIPEPHY1_REF, "clk_pipephy1_ref", "xin24m", 1745 1.1 ryo CLKGATE_CON(0, 37), 1), 1746 1.1 ryo RK_GATE(RK3588_CLK_PIPEPHY2_REF, "clk_pipephy2_ref", "xin24m", 1747 1.1 ryo CLKGATE_CON(0, 37), 2), 1748 1.1 ryo RK_GATE(RK3588_PCLK_GMAC0, "pclk_gmac0", "pclk_php_root", 1749 1.1 ryo CLKGATE_CON(0, 32), 3), 1750 1.1 ryo RK_GATE(RK3588_PCLK_GMAC1, "pclk_gmac1", "pclk_php_root", 1751 1.1 ryo CLKGATE_CON(0, 32), 4), 1752 1.1 ryo RK_GATE(RK3588_ACLK_GMAC0, "aclk_gmac0", "aclk_mmu_php", 1753 1.1 ryo CLKGATE_CON(0, 32), 10), 1754 1.1 ryo RK_GATE(RK3588_ACLK_GMAC1, "aclk_gmac1", "aclk_mmu_php", 1755 1.1 ryo CLKGATE_CON(0, 32), 11), 1756 1.1 ryo RK_GATE(RK3588_CLK_PMALIVE0, "clk_pmalive0", "xin24m", 1757 1.1 ryo CLKGATE_CON(0, 37), 4), 1758 1.1 ryo RK_GATE(RK3588_CLK_PMALIVE1, "clk_pmalive1", "xin24m", 1759 1.1 ryo CLKGATE_CON(0, 37), 5), 1760 1.1 ryo RK_GATE(RK3588_CLK_PMALIVE2, "clk_pmalive2", "xin24m", 1761 1.1 ryo CLKGATE_CON(0, 37), 6), 1762 1.1 ryo RK_GATE(RK3588_ACLK_SATA0, "aclk_sata0", "aclk_mmu_php", 1763 1.1 ryo CLKGATE_CON(0, 37), 7), 1764 1.1 ryo RK_GATE(RK3588_ACLK_SATA1, "aclk_sata1", "aclk_mmu_php", 1765 1.1 ryo CLKGATE_CON(0, 37), 8), 1766 1.1 ryo RK_GATE(RK3588_ACLK_SATA2, "aclk_sata2", "aclk_mmu_php", 1767 1.1 ryo CLKGATE_CON(0, 37), 9), 1768 1.1 ryo RK_COMPOSITE(RK3588_CLK_RXOOB0, "clk_rxoob0", 1769 1.1 ryo gpll_cpll_parents, 1770 1.1 ryo CLKSEL_CON(0, 82), __BITS(7,7), __BITS(6,0), 1771 1.1 ryo CLKGATE_CON(0, 37), __BIT(10), 1772 1.1 ryo 0), 1773 1.1 ryo RK_COMPOSITE(RK3588_CLK_RXOOB1, "clk_rxoob1", 1774 1.1 ryo gpll_cpll_parents, 1775 1.1 ryo CLKSEL_CON(0, 82), __BITS(15,15), __BITS(14,8), 1776 1.1 ryo CLKGATE_CON(0, 37), __BIT(11), 1777 1.1 ryo 0), 1778 1.1 ryo RK_COMPOSITE(RK3588_CLK_RXOOB2, "clk_rxoob2", 1779 1.1 ryo gpll_cpll_parents, 1780 1.1 ryo CLKSEL_CON(0, 83), __BITS(7,7), __BITS(6,0), 1781 1.1 ryo CLKGATE_CON(0, 37), __BIT(12), 1782 1.1 ryo 0), 1783 1.1 ryo RK_GATE(RK3588_ACLK_USB3OTG2, "aclk_usb3otg2", "aclk_mmu_php", 1784 1.1 ryo CLKGATE_CON(0, 35), 7), 1785 1.1 ryo RK_GATE(RK3588_SUSPEND_CLK_USB3OTG2, "suspend_clk_usb3otg2", "xin24m", 1786 1.1 ryo CLKGATE_CON(0, 35), 8), 1787 1.1 ryo RK_GATE(RK3588_REF_CLK_USB3OTG2, "ref_clk_usb3otg2", "xin24m", 1788 1.1 ryo CLKGATE_CON(0, 35), 9), 1789 1.1 ryo RK_COMPOSITE(RK3588_CLK_UTMI_OTG2, "clk_utmi_otg2", 1790 1.1 ryo mux_150m_50m_24m_parents, 1791 1.1 ryo CLKSEL_CON(0, 84), __BITS(13,12), __BITS(11,8), 1792 1.1 ryo CLKGATE_CON(0, 35), __BIT(10), 1793 1.1 ryo 0), 1794 1.1 ryo RK_GATE(RK3588_PCLK_PCIE_COMBO_PIPE_PHY0, "pclk_pcie_combo_pipe_phy0", 1795 1.1 ryo "pclk_top_root", 1796 1.1 ryo CLKGATE_CON(PHP, 0), 5), 1797 1.1 ryo RK_GATE(RK3588_PCLK_PCIE_COMBO_PIPE_PHY1, "pclk_pcie_combo_pipe_phy1", 1798 1.1 ryo "pclk_top_root", 1799 1.1 ryo CLKGATE_CON(PHP, 0), 6), 1800 1.1 ryo RK_GATE(RK3588_PCLK_PCIE_COMBO_PIPE_PHY2, "pclk_pcie_combo_pipe_phy2", 1801 1.1 ryo "pclk_top_root", 1802 1.1 ryo CLKGATE_CON(PHP, 0), 7), 1803 1.1 ryo RK_GATE(RK3588_PCLK_PCIE_COMBO_PIPE_PHY, "pclk_pcie_combo_pipe_phy", 1804 1.1 ryo "pclk_top_root", 1805 1.1 ryo CLKGATE_CON(PHP, 0), 8), 1806 1.1 ryo RK_COMPOSITE(RK3588_CLK_RGA3_1_CORE, "clk_rga3_1_core", 1807 1.1 ryo gpll_cpll_aupll_spll_parents, 1808 1.1 ryo CLKSEL_CON(0, 174), __BITS(15,14), __BITS(13,9), 1809 1.1 ryo CLKGATE_CON(0, 76), __BIT(6), 1810 1.1 ryo 0), 1811 1.1 ryo RK_COMPOSITE(RK3588_ACLK_RGA3_ROOT, "aclk_rga3_root", 1812 1.1 ryo gpll_cpll_aupll_parents, 1813 1.1 ryo CLKSEL_CON(0, 174), __BITS(6,5), __BITS(4,0), 1814 1.1 ryo CLKGATE_CON(0, 76), __BIT(0), 1815 1.1 ryo 0), 1816 1.1 ryo RK_COMPOSITE_NODIV(RK3588_HCLK_RGA3_ROOT, "hclk_rga3_root", 1817 1.1 ryo mux_200m_100m_50m_24m_parents, 1818 1.1 ryo CLKSEL_CON(0, 174), __BITS(8,7), 1819 1.1 ryo CLKGATE_CON(0, 76), __BIT(1), 1820 1.1 ryo 0), 1821 1.1 ryo RK_GATE(RK3588_HCLK_RGA3_1, "hclk_rga3_1", "hclk_rga3_root", 1822 1.1 ryo CLKGATE_CON(0, 76), 4), 1823 1.1 ryo RK_GATE(RK3588_ACLK_RGA3_1, "aclk_rga3_1", "aclk_rga3_root", 1824 1.1 ryo CLKGATE_CON(0, 76), 5), 1825 1.1 ryo RK_COMPOSITE_NODIV(0, "hclk_rkvdec0_root", 1826 1.1 ryo mux_200m_100m_50m_24m_parents, 1827 1.1 ryo CLKSEL_CON(0, 89), __BITS(1,0), 1828 1.1 ryo CLKGATE_CON(0, 40), __BIT(0), 1829 1.1 ryo 0), 1830 1.1 ryo RK_COMPOSITE(0, "aclk_rkvdec0_root", 1831 1.1 ryo gpll_cpll_aupll_spll_parents, 1832 1.1 ryo CLKSEL_CON(0, 89), __BITS(8,7), __BITS(6,2), 1833 1.1 ryo CLKGATE_CON(0, 40), __BIT(1), 1834 1.1 ryo 0), 1835 1.1 ryo RK_COMPOSITE(RK3588_ACLK_RKVDEC_CCU, "aclk_rkvdec_ccu", 1836 1.1 ryo gpll_cpll_aupll_spll_parents, 1837 1.1 ryo CLKSEL_CON(0, 89), __BITS(15,14), __BITS(13,9), 1838 1.1 ryo CLKGATE_CON(0, 40), __BIT(2), 1839 1.1 ryo 0), 1840 1.1 ryo RK_COMPOSITE(RK3588_CLK_RKVDEC0_CA, "clk_rkvdec0_ca", 1841 1.1 ryo gpll_cpll_parents, 1842 1.1 ryo CLKSEL_CON(0, 90), __BITS(5,5), __BITS(4,0), 1843 1.1 ryo CLKGATE_CON(0, 40), __BIT(7), 1844 1.1 ryo 0), 1845 1.1 ryo RK_COMPOSITE(RK3588_CLK_RKVDEC0_HEVC_CA, "clk_rkvdec0_hevc_ca", 1846 1.1 ryo gpll_cpll_npll_1000m_parents, 1847 1.1 ryo CLKSEL_CON(0, 90), __BITS(12,11), __BITS(10,6), 1848 1.1 ryo CLKGATE_CON(0, 40), __BIT(8), 1849 1.1 ryo 0), 1850 1.1 ryo RK_COMPOSITE(RK3588_CLK_RKVDEC0_CORE, "clk_rkvdec0_core", 1851 1.1 ryo gpll_cpll_parents, 1852 1.1 ryo CLKSEL_CON(0, 91), __BITS(5,5), __BITS(4,0), 1853 1.1 ryo CLKGATE_CON(0, 40), __BIT(9), 1854 1.1 ryo 0), 1855 1.1 ryo RK_COMPOSITE_NODIV(0, "hclk_rkvdec1_root", 1856 1.1 ryo mux_200m_100m_50m_24m_parents, 1857 1.1 ryo CLKSEL_CON(0, 93), __BITS(1,0), 1858 1.1 ryo CLKGATE_CON(0, 41), __BIT(0), 1859 1.1 ryo 0), 1860 1.1 ryo RK_COMPOSITE(0, "aclk_rkvdec1_root", 1861 1.1 ryo gpll_cpll_aupll_npll_parents, 1862 1.1 ryo CLKSEL_CON(0, 93), __BITS(8,7), __BITS(6,2), 1863 1.1 ryo CLKGATE_CON(0, 41), __BIT(1), 1864 1.1 ryo 0), 1865 1.1 ryo RK_COMPOSITE(RK3588_CLK_RKVDEC1_CA, "clk_rkvdec1_ca", 1866 1.1 ryo gpll_cpll_parents, 1867 1.1 ryo CLKSEL_CON(0, 93), __BITS(14,14), __BITS(13,9), 1868 1.1 ryo CLKGATE_CON(0, 41), __BIT(6), 1869 1.1 ryo 0), 1870 1.1 ryo RK_COMPOSITE(RK3588_CLK_RKVDEC1_HEVC_CA, "clk_rkvdec1_hevc_ca", 1871 1.1 ryo gpll_cpll_npll_1000m_parents, 1872 1.1 ryo CLKSEL_CON(0, 94), __BITS(6,5), __BITS(4,0), 1873 1.1 ryo CLKGATE_CON(0, 41), __BIT(7), 1874 1.1 ryo 0), 1875 1.1 ryo RK_COMPOSITE(RK3588_CLK_RKVDEC1_CORE, "clk_rkvdec1_core", 1876 1.1 ryo gpll_cpll_parents, 1877 1.1 ryo CLKSEL_CON(0, 94), __BITS(12,12), __BITS(11,7), 1878 1.1 ryo CLKGATE_CON(0, 41), __BIT(8), 1879 1.1 ryo 0), 1880 1.1 ryo RK_COMPOSITE_NODIV(0, "hclk_sdio_root", 1881 1.1 ryo mux_200m_100m_50m_24m_parents, 1882 1.1 ryo CLKSEL_CON(0, 172), __BITS(1,0), 1883 1.1 ryo CLKGATE_CON(0, 75), __BIT(0), 1884 1.1 ryo 0), 1885 1.1 ryo RK_COMPOSITE(RK3588_CCLK_SRC_SDIO, "cclk_src_sdio", 1886 1.1 ryo gpll_cpll_24m_parents, 1887 1.1 ryo CLKSEL_CON(0, 172), __BITS(9,8), __BITS(7,2), 1888 1.1 ryo CLKGATE_CON(0, 75), __BIT(3), 1889 1.1 ryo 0), 1890 1.1 ryo RK_COMPOSITE(RK3588_ACLK_USB_ROOT, "aclk_usb_root", 1891 1.1 ryo gpll_cpll_parents, 1892 1.1 ryo CLKSEL_CON(0, 96), __BITS(5,5), __BITS(4,0), 1893 1.1 ryo CLKGATE_CON(0, 42), __BIT(0), 1894 1.1 ryo 0), 1895 1.1 ryo RK_COMPOSITE_NODIV(RK3588_HCLK_USB_ROOT, "hclk_usb_root", 1896 1.1 ryo mux_150m_100m_50m_24m_parents, 1897 1.1 ryo CLKSEL_CON(0, 96), __BITS(7,6), 1898 1.1 ryo CLKGATE_CON(0, 42), __BIT(1), 1899 1.1 ryo 0), 1900 1.1 ryo RK_GATE(RK3588_SUSPEND_CLK_USB3OTG0, "suspend_clk_usb3otg0", "xin24m", 1901 1.1 ryo CLKGATE_CON(0, 42), 5), 1902 1.1 ryo RK_GATE(RK3588_REF_CLK_USB3OTG0, "ref_clk_usb3otg0", "xin24m", 1903 1.1 ryo CLKGATE_CON(0, 42), 6), 1904 1.1 ryo RK_GATE(RK3588_SUSPEND_CLK_USB3OTG1, "suspend_clk_usb3otg1", "xin24m", 1905 1.1 ryo CLKGATE_CON(0, 42), 8), 1906 1.1 ryo RK_GATE(RK3588_REF_CLK_USB3OTG1, "ref_clk_usb3otg1", "xin24m", 1907 1.1 ryo CLKGATE_CON(0, 42), 9), 1908 1.1 ryo RK_COMPOSITE(RK3588_ACLK_VDPU_ROOT, "aclk_vdpu_root", 1909 1.1 ryo gpll_cpll_aupll_parents, 1910 1.1 ryo CLKSEL_CON(0, 98), __BITS(6,5), __BITS(4,0), 1911 1.1 ryo CLKGATE_CON(0, 44), __BIT(0), 1912 1.1 ryo 0), 1913 1.1 ryo RK_COMPOSITE_NODIV(RK3588_ACLK_VDPU_LOW_ROOT, "aclk_vdpu_low_root", 1914 1.1 ryo mux_400m_200m_100m_24m_parents, 1915 1.1 ryo CLKSEL_CON(0, 98), __BITS(8,7), 1916 1.1 ryo CLKGATE_CON(0, 44), __BIT(1), 1917 1.1 ryo 0), 1918 1.1 ryo RK_COMPOSITE_NODIV(RK3588_HCLK_VDPU_ROOT, "hclk_vdpu_root", 1919 1.1 ryo mux_200m_100m_50m_24m_parents, 1920 1.1 ryo CLKSEL_CON(0, 98), __BITS(10,9), 1921 1.1 ryo CLKGATE_CON(0, 44), __BIT(2), 1922 1.1 ryo 0), 1923 1.1 ryo RK_COMPOSITE(RK3588_ACLK_JPEG_DECODER_ROOT, "aclk_jpeg_decoder_root", 1924 1.1 ryo gpll_cpll_aupll_spll_parents, 1925 1.1 ryo CLKSEL_CON(0, 99), __BITS(6,5), __BITS(4,0), 1926 1.1 ryo CLKGATE_CON(0, 44), __BIT(3), 1927 1.1 ryo 0), 1928 1.1 ryo RK_GATE(RK3588_HCLK_IEP2P0, "hclk_iep2p0", "hclk_vdpu_root", 1929 1.1 ryo CLKGATE_CON(0, 45), 4), 1930 1.1 ryo RK_COMPOSITE(RK3588_CLK_IEP2P0_CORE, "clk_iep2p0_core", 1931 1.1 ryo gpll_cpll_parents, 1932 1.1 ryo CLKSEL_CON(0, 99), __BITS(12,12), __BITS(11,7), 1933 1.1 ryo CLKGATE_CON(0, 45), __BIT(6), 1934 1.1 ryo 0), 1935 1.1 ryo RK_GATE(RK3588_HCLK_JPEG_ENCODER0, "hclk_jpeg_encoder0", 1936 1.1 ryo "hclk_vdpu_root", 1937 1.1 ryo CLKGATE_CON(0, 44), 11), 1938 1.1 ryo RK_GATE(RK3588_HCLK_JPEG_ENCODER1, "hclk_jpeg_encoder1", 1939 1.1 ryo "hclk_vdpu_root", 1940 1.1 ryo CLKGATE_CON(0, 44), 13), 1941 1.1 ryo RK_GATE(RK3588_HCLK_JPEG_ENCODER2, "hclk_jpeg_encoder2", 1942 1.1 ryo "hclk_vdpu_root", 1943 1.1 ryo CLKGATE_CON(0, 44), 15), 1944 1.1 ryo RK_GATE(RK3588_HCLK_JPEG_ENCODER3, "hclk_jpeg_encoder3", 1945 1.1 ryo "hclk_vdpu_root", 1946 1.1 ryo CLKGATE_CON(0, 45), 1), 1947 1.1 ryo RK_GATE(RK3588_HCLK_JPEG_DECODER, "hclk_jpeg_decoder", "hclk_vdpu_root", 1948 1.1 ryo CLKGATE_CON(0, 45), 3), 1949 1.1 ryo RK_GATE(RK3588_HCLK_RGA2, "hclk_rga2", "hclk_vdpu_root", 1950 1.1 ryo CLKGATE_CON(0, 45), 7), 1951 1.1 ryo RK_GATE(RK3588_ACLK_RGA2, "aclk_rga2", "aclk_vdpu_root", 1952 1.1 ryo CLKGATE_CON(0, 45), 8), 1953 1.1 ryo RK_COMPOSITE(RK3588_CLK_RGA2_CORE, "clk_rga2_core", 1954 1.1 ryo gpll_cpll_npll_aupll_spll_parents, 1955 1.1 ryo CLKSEL_CON(0, 100), __BITS(7,5), __BITS(4,0), 1956 1.1 ryo CLKGATE_CON(0, 45), __BIT(9), 1957 1.1 ryo 0), 1958 1.1 ryo RK_GATE(RK3588_HCLK_RGA3_0, "hclk_rga3_0", "hclk_vdpu_root", 1959 1.1 ryo CLKGATE_CON(0, 45), 10), 1960 1.1 ryo RK_GATE(RK3588_ACLK_RGA3_0, "aclk_rga3_0", "aclk_vdpu_root", 1961 1.1 ryo CLKGATE_CON(0, 45), 11), 1962 1.1 ryo RK_COMPOSITE(RK3588_CLK_RGA3_0_CORE, "clk_rga3_0_core", 1963 1.1 ryo gpll_cpll_npll_aupll_spll_parents, 1964 1.1 ryo CLKSEL_CON(0, 100), __BITS(15,13), __BITS(12,8), 1965 1.1 ryo CLKGATE_CON(0, 45), __BIT(12), 1966 1.1 ryo 0), 1967 1.1 ryo RK_GATE(RK3588_HCLK_VPU, "hclk_vpu", "hclk_vdpu_root", 1968 1.1 ryo CLKGATE_CON(0, 44), 9), 1969 1.1 ryo RK_COMPOSITE_NODIV(RK3588_HCLK_RKVENC1_ROOT, "hclk_rkvenc1_root", 1970 1.1 ryo mux_200m_100m_50m_24m_parents, 1971 1.1 ryo CLKSEL_CON(0, 104), __BITS(1,0), 1972 1.1 ryo CLKGATE_CON(0, 48), __BIT(0), 1973 1.1 ryo 0), 1974 1.1 ryo RK_COMPOSITE(RK3588_ACLK_RKVENC1_ROOT, "aclk_rkvenc1_root", 1975 1.1 ryo gpll_cpll_npll_parents, 1976 1.1 ryo CLKSEL_CON(0, 104), __BITS(8,7), __BITS(6,2), 1977 1.1 ryo CLKGATE_CON(0, 48), __BIT(1), 1978 1.1 ryo 0), 1979 1.1 ryo RK_COMPOSITE_NODIV(RK3588_HCLK_RKVENC0_ROOT, "hclk_rkvenc0_root", 1980 1.1 ryo mux_200m_100m_50m_24m_parents, 1981 1.1 ryo CLKSEL_CON(0, 102), __BITS(1,0), 1982 1.1 ryo CLKGATE_CON(0, 47), __BIT(0), 1983 1.1 ryo 0), 1984 1.1 ryo RK_COMPOSITE(RK3588_ACLK_RKVENC0_ROOT, "aclk_rkvenc0_root", 1985 1.1 ryo gpll_cpll_npll_parents, 1986 1.1 ryo CLKSEL_CON(0, 102), __BITS(8,7), __BITS(6,2), 1987 1.1 ryo CLKGATE_CON(0, 47), __BIT(1), 1988 1.1 ryo 0), 1989 1.1 ryo RK_GATE(RK3588_HCLK_RKVENC0, "hclk_rkvenc0", "hclk_rkvenc0_root", 1990 1.1 ryo CLKGATE_CON(0, 47), 4), 1991 1.1 ryo RK_GATE(RK3588_ACLK_RKVENC0, "aclk_rkvenc0", "aclk_rkvenc0_root", 1992 1.1 ryo CLKGATE_CON(0, 47), 5), 1993 1.1 ryo RK_COMPOSITE(RK3588_CLK_RKVENC0_CORE, "clk_rkvenc0_core", 1994 1.1 ryo gpll_cpll_aupll_npll_parents, 1995 1.1 ryo CLKSEL_CON(0, 102), __BITS(15,14), __BITS(13,9), 1996 1.1 ryo CLKGATE_CON(0, 47), __BIT(6), 1997 1.1 ryo 0), 1998 1.1 ryo RK_COMPOSITE(RK3588_CLK_RKVENC1_CORE, "clk_rkvenc1_core", 1999 1.1 ryo gpll_cpll_aupll_npll_parents, 2000 1.1 ryo CLKSEL_CON(0, 104), __BITS(15,14), __BITS(13,9), 2001 1.1 ryo CLKGATE_CON(0, 48), __BIT(6), 2002 1.1 ryo 0), 2003 1.1 ryo RK_COMPOSITE(RK3588_ACLK_VI_ROOT, "aclk_vi_root", 2004 1.1 ryo gpll_cpll_npll_aupll_spll_parents, 2005 1.1 ryo CLKSEL_CON(0, 106), __BITS(7,5), __BITS(4,0), 2006 1.1 ryo CLKGATE_CON(0, 49), __BIT(0), 2007 1.1 ryo 0), 2008 1.1 ryo RK_COMPOSITE_NODIV(RK3588_HCLK_VI_ROOT, "hclk_vi_root", 2009 1.1 ryo mux_200m_100m_50m_24m_parents, 2010 1.1 ryo CLKSEL_CON(0, 106), __BITS(9,8), 2011 1.1 ryo CLKGATE_CON(0, 49), __BIT(1), 2012 1.1 ryo 0), 2013 1.1 ryo RK_COMPOSITE_NODIV(RK3588_PCLK_VI_ROOT, "pclk_vi_root", 2014 1.1 ryo mux_100m_50m_24m_parents, 2015 1.1 ryo CLKSEL_CON(0, 106), __BITS(11,10), 2016 1.1 ryo CLKGATE_CON(0, 49), __BIT(2), 2017 1.1 ryo 0), 2018 1.1 ryo RK_COMPOSITE_NODIV(RK3588_ICLK_CSIHOST01, "iclk_csihost01", 2019 1.1 ryo mux_400m_200m_100m_24m_parents, 2020 1.1 ryo CLKSEL_CON(0, 108), __BITS(15,14), 2021 1.1 ryo CLKGATE_CON(0, 51), __BIT(10), 2022 1.1 ryo 0), 2023 1.1 ryo RK_GATE(RK3588_ICLK_CSIHOST0, "iclk_csihost0", "iclk_csihost01", 2024 1.1 ryo CLKGATE_CON(0, 51), 11), 2025 1.1 ryo RK_GATE(RK3588_ICLK_CSIHOST1, "iclk_csihost1", "iclk_csihost01", 2026 1.1 ryo CLKGATE_CON(0, 51), 12), 2027 1.1 ryo RK_GATE(RK3588_PCLK_CSI_HOST_0, "pclk_csi_host_0", "pclk_vi_root", 2028 1.1 ryo CLKGATE_CON(0, 50), 4), 2029 1.1 ryo RK_GATE(RK3588_PCLK_CSI_HOST_1, "pclk_csi_host_1", "pclk_vi_root", 2030 1.1 ryo CLKGATE_CON(0, 50), 5), 2031 1.1 ryo RK_GATE(RK3588_PCLK_CSI_HOST_2, "pclk_csi_host_2", "pclk_vi_root", 2032 1.1 ryo CLKGATE_CON(0, 50), 6), 2033 1.1 ryo RK_GATE(RK3588_PCLK_CSI_HOST_3, "pclk_csi_host_3", "pclk_vi_root", 2034 1.1 ryo CLKGATE_CON(0, 50), 7), 2035 1.1 ryo RK_GATE(RK3588_PCLK_CSI_HOST_4, "pclk_csi_host_4", "pclk_vi_root", 2036 1.1 ryo CLKGATE_CON(0, 50), 8), 2037 1.1 ryo RK_GATE(RK3588_PCLK_CSI_HOST_5, "pclk_csi_host_5", "pclk_vi_root", 2038 1.1 ryo CLKGATE_CON(0, 50), 9), 2039 1.1 ryo RK_GATE(RK3588_ACLK_FISHEYE0, "aclk_fisheye0", "aclk_vi_root", 2040 1.1 ryo CLKGATE_CON(0, 49), 14), 2041 1.1 ryo RK_GATE(RK3588_HCLK_FISHEYE0, "hclk_fisheye0", "hclk_vi_root", 2042 1.1 ryo CLKGATE_CON(0, 49), 15), 2043 1.1 ryo RK_COMPOSITE(RK3588_CLK_FISHEYE0_CORE, "clk_fisheye0_core", 2044 1.1 ryo gpll_cpll_aupll_spll_parents, 2045 1.1 ryo CLKSEL_CON(0, 108), __BITS(6,5), __BITS(4,0), 2046 1.1 ryo CLKGATE_CON(0, 50), __BIT(0), 2047 1.1 ryo 0), 2048 1.1 ryo RK_GATE(RK3588_ACLK_FISHEYE1, "aclk_fisheye1", "aclk_vi_root", 2049 1.1 ryo CLKGATE_CON(0, 50), 1), 2050 1.1 ryo RK_GATE(RK3588_HCLK_FISHEYE1, "hclk_fisheye1", "hclk_vi_root", 2051 1.1 ryo CLKGATE_CON(0, 50), 2), 2052 1.1 ryo RK_COMPOSITE(RK3588_CLK_FISHEYE1_CORE, "clk_fisheye1_core", 2053 1.1 ryo gpll_cpll_aupll_spll_parents, 2054 1.1 ryo CLKSEL_CON(0, 108), __BITS(13,12), __BITS(11,7), 2055 1.1 ryo CLKGATE_CON(0, 50), __BIT(3), 2056 1.1 ryo 0), 2057 1.1 ryo RK_COMPOSITE(RK3588_CLK_ISP0_CORE, "clk_isp0_core", 2058 1.1 ryo gpll_cpll_aupll_spll_parents, 2059 1.1 ryo CLKSEL_CON(0, 107), __BITS(12,11), __BITS(10,6), 2060 1.1 ryo CLKGATE_CON(0, 49), __BIT(9), 2061 1.1 ryo 0), 2062 1.1 ryo RK_GATE(RK3588_CLK_ISP0_CORE_MARVIN, "clk_isp0_core_marvin", 2063 1.1 ryo "clk_isp0_core", 2064 1.1 ryo CLKGATE_CON(0, 49), 10), 2065 1.1 ryo RK_GATE(RK3588_CLK_ISP0_CORE_VICAP, "clk_isp0_core_vicap", 2066 1.1 ryo "clk_isp0_core", 2067 1.1 ryo CLKGATE_CON(0, 49), 11), 2068 1.1 ryo RK_GATE(RK3588_ACLK_ISP0, "aclk_isp0", "aclk_vi_root", 2069 1.1 ryo CLKGATE_CON(0, 49), 12), 2070 1.1 ryo RK_GATE(RK3588_HCLK_ISP0, "hclk_isp0", "hclk_vi_root", 2071 1.1 ryo CLKGATE_CON(0, 49), 13), 2072 1.1 ryo RK_COMPOSITE(RK3588_DCLK_VICAP, "dclk_vicap", 2073 1.1 ryo gpll_cpll_parents, 2074 1.1 ryo CLKSEL_CON(0, 107), __BITS(5,5), __BITS(4,0), 2075 1.1 ryo CLKGATE_CON(0, 49), __BIT(6), 2076 1.1 ryo 0), 2077 1.1 ryo RK_GATE(RK3588_ACLK_VICAP, "aclk_vicap", "aclk_vi_root", 2078 1.1 ryo CLKGATE_CON(0, 49), 7), 2079 1.1 ryo RK_GATE(RK3588_HCLK_VICAP, "hclk_vicap", "hclk_vi_root", 2080 1.1 ryo CLKGATE_CON(0, 49), 8), 2081 1.1 ryo RK_COMPOSITE(RK3588_ACLK_VO0_ROOT, "aclk_vo0_root", 2082 1.1 ryo gpll_cpll_parents, 2083 1.1 ryo CLKSEL_CON(0, 116), __BITS(5,5), __BITS(4,0), 2084 1.1 ryo CLKGATE_CON(0, 55), __BIT(0), 2085 1.1 ryo 0), 2086 1.1 ryo RK_COMPOSITE_NODIV(RK3588_HCLK_VO0_ROOT, "hclk_vo0_root", 2087 1.1 ryo mux_200m_100m_50m_24m_parents, 2088 1.1 ryo CLKSEL_CON(0, 116), __BITS(7,6), 2089 1.1 ryo CLKGATE_CON(0, 55), __BIT(1), 2090 1.1 ryo 0), 2091 1.1 ryo RK_COMPOSITE_NODIV(RK3588_HCLK_VO0_S_ROOT, "hclk_vo0_s_root", 2092 1.1 ryo mux_200m_100m_50m_24m_parents, 2093 1.1 ryo CLKSEL_CON(0, 116), __BITS(9,8), 2094 1.1 ryo CLKGATE_CON(0, 55), __BIT(2), 2095 1.1 ryo 0), 2096 1.1 ryo RK_COMPOSITE_NODIV(RK3588_PCLK_VO0_ROOT, "pclk_vo0_root", 2097 1.1 ryo mux_100m_50m_24m_parents, 2098 1.1 ryo CLKSEL_CON(0, 116), __BITS(11,10), 2099 1.1 ryo CLKGATE_CON(0, 55), __BIT(3), 2100 1.1 ryo 0), 2101 1.1 ryo RK_COMPOSITE_NODIV(RK3588_PCLK_VO0_S_ROOT, "pclk_vo0_s_root", 2102 1.1 ryo mux_100m_50m_24m_parents, 2103 1.1 ryo CLKSEL_CON(0, 116), __BITS(13,12), 2104 1.1 ryo CLKGATE_CON(0, 55), __BIT(4), 2105 1.1 ryo 0), 2106 1.1 ryo RK_GATE(RK3588_PCLK_DP0, "pclk_dp0", "pclk_vo0_root", 2107 1.1 ryo CLKGATE_CON(0, 56), 4), 2108 1.1 ryo RK_GATE(RK3588_PCLK_DP1, "pclk_dp1", "pclk_vo0_root", 2109 1.1 ryo CLKGATE_CON(0, 56), 5), 2110 1.1 ryo RK_GATE(RK3588_PCLK_S_DP0, "pclk_s_dp0", "pclk_vo0_s_root", 2111 1.1 ryo CLKGATE_CON(0, 56), 6), 2112 1.1 ryo RK_GATE(RK3588_PCLK_S_DP1, "pclk_s_dp1", "pclk_vo0_s_root", 2113 1.1 ryo CLKGATE_CON(0, 56), 7), 2114 1.1 ryo RK_GATE(RK3588_CLK_DP0, "clk_dp0", "aclk_vo0_root", 2115 1.1 ryo CLKGATE_CON(0, 56), 8), 2116 1.1 ryo RK_GATE(RK3588_CLK_DP1, "clk_dp1", "aclk_vo0_root", 2117 1.1 ryo CLKGATE_CON(0, 56), 9), 2118 1.1 ryo RK_GATE(RK3588_HCLK_HDCP_KEY0, "hclk_hdcp_key0", "hclk_vo0_s_root", 2119 1.1 ryo CLKGATE_CON(0, 55), 11), 2120 1.1 ryo RK_GATE(RK3588_PCLK_HDCP0, "pclk_hdcp0", "pclk_vo0_root", 2121 1.1 ryo CLKGATE_CON(0, 55), 14), 2122 1.1 ryo RK_GATE(RK3588_ACLK_TRNG0, "aclk_trng0", "aclk_vo0_root", 2123 1.1 ryo CLKGATE_CON(0, 56), 0), 2124 1.1 ryo RK_GATE(RK3588_PCLK_TRNG0, "pclk_trng0", "pclk_vo0_root", 2125 1.1 ryo CLKGATE_CON(0, 56), 1), 2126 1.1 ryo RK_GATE(RK3588_PCLK_VO0GRF, "pclk_vo0grf", "pclk_vo0_root", 2127 1.1 ryo CLKGATE_CON(0, 55), 10), 2128 1.1 ryo RK_COMPOSITE(RK3588_CLK_I2S4_8CH_TX_SRC, "clk_i2s4_8ch_tx_src", 2129 1.1 ryo gpll_aupll_parents, 2130 1.1 ryo CLKSEL_CON(0, 118), __BITS(5,5), __BITS(4,0), 2131 1.1 ryo CLKGATE_CON(0, 56), __BIT(11), 2132 1.1 ryo 0), 2133 1.1 ryo RK_COMPOSITE_FRAC(RK3588_CLK_I2S4_8CH_TX_FRAC, "clk_i2s4_8ch_tx_frac", 2134 1.1 ryo "clk_i2s4_8ch_tx_src", 2135 1.1 ryo CLKGATE_CON(0, 56), 2136 1.1 ryo RK_COMPOSITE_SET_RATE_PARENT), 2137 1.1 ryo RK_MUX(RK3588_CLK_I2S4_8CH_TX, "clk_i2s4_8ch_tx", 2138 1.1 ryo clk_i2s4_8ch_tx_parents, 2139 1.1 ryo CLKSEL_CON(0, 120), __BITS(1,0)), 2140 1.1 ryo RK_GATE(RK3588_MCLK_I2S4_8CH_TX, "mclk_i2s4_8ch_tx", "clk_i2s4_8ch_tx", 2141 1.1 ryo CLKGATE_CON(0, 56), 13), 2142 1.1 ryo RK_COMPOSITE(RK3588_CLK_I2S8_8CH_TX_SRC, "clk_i2s8_8ch_tx_src", 2143 1.1 ryo gpll_aupll_parents, 2144 1.1 ryo CLKSEL_CON(0, 120), __BITS(8,8), __BITS(7,3), 2145 1.1 ryo CLKGATE_CON(0, 56), __BIT(15), 2146 1.1 ryo 0), 2147 1.1 ryo RK_COMPOSITE_FRAC(RK3588_CLK_I2S8_8CH_TX_FRAC, "clk_i2s8_8ch_tx_frac", 2148 1.1 ryo "clk_i2s8_8ch_tx_src", 2149 1.1 ryo CLKGATE_CON(0, 57), 2150 1.1 ryo RK_COMPOSITE_SET_RATE_PARENT), 2151 1.1 ryo RK_MUX(RK3588_CLK_I2S8_8CH_TX, "clk_i2s8_8ch_tx", 2152 1.1 ryo clk_i2s8_8ch_tx_parents, 2153 1.1 ryo CLKSEL_CON(0, 122), __BITS(1,0)), 2154 1.1 ryo RK_GATE(RK3588_MCLK_I2S8_8CH_TX, "mclk_i2s8_8ch_tx", "clk_i2s8_8ch_tx", 2155 1.1 ryo CLKGATE_CON(0, 57), 1), 2156 1.1 ryo RK_COMPOSITE(RK3588_CLK_SPDIF2_DP0_SRC, "clk_spdif2_dp0_src", 2157 1.1 ryo gpll_aupll_parents, 2158 1.1 ryo CLKSEL_CON(0, 122), __BITS(8,8), __BITS(7,3), 2159 1.1 ryo CLKGATE_CON(0, 57), __BIT(3), 2160 1.1 ryo 0), 2161 1.1 ryo RK_COMPOSITE_FRAC(RK3588_CLK_SPDIF2_DP0_FRAC, "clk_spdif2_dp0_frac", 2162 1.1 ryo "clk_spdif2_dp0_src", 2163 1.1 ryo CLKGATE_CON(0, 57), 2164 1.1 ryo RK_COMPOSITE_SET_RATE_PARENT), 2165 1.1 ryo RK_MUX(RK3588_CLK_SPDIF2_DP0, "clk_spdif2_dp0", clk_spdif2_dp0_parents, 2166 1.1 ryo CLKSEL_CON(0, 124), __BITS(1,0)), 2167 1.1 ryo RK_GATE(RK3588_MCLK_SPDIF2_DP0, "mclk_spdif2_dp0", "clk_spdif2_dp0", 2168 1.1 ryo CLKGATE_CON(0, 57), 5), 2169 1.1 ryo RK_GATE(RK3588_MCLK_SPDIF2, "mclk_spdif2", "clk_spdif2_dp0", 2170 1.1 ryo CLKGATE_CON(0, 57), 6), 2171 1.1 ryo RK_COMPOSITE(RK3588_CLK_SPDIF5_DP1_SRC, "clk_spdif5_dp1_src", 2172 1.1 ryo gpll_aupll_parents, 2173 1.1 ryo CLKSEL_CON(0, 124), __BITS(7,7), __BITS(6,2), 2174 1.1 ryo CLKGATE_CON(0, 57), __BIT(8), 2175 1.1 ryo 0), 2176 1.1 ryo RK_COMPOSITE_FRAC(RK3588_CLK_SPDIF5_DP1_FRAC, "clk_spdif5_dp1_frac", 2177 1.1 ryo "clk_spdif5_dp1_src", 2178 1.1 ryo CLKGATE_CON(0, 57), 2179 1.1 ryo RK_COMPOSITE_SET_RATE_PARENT), 2180 1.1 ryo RK_MUX(RK3588_CLK_SPDIF5_DP1, "clk_spdif5_dp1", clk_spdif5_dp1_parents, 2181 1.1 ryo CLKSEL_CON(0, 126), __BITS(1,0)), 2182 1.1 ryo RK_GATE(RK3588_MCLK_SPDIF5_DP1, "mclk_spdif5_dp1", "clk_spdif5_dp1", 2183 1.1 ryo CLKGATE_CON(0, 57), 10), 2184 1.1 ryo RK_GATE(RK3588_MCLK_SPDIF5, "mclk_spdif5", "clk_spdif5_dp1", 2185 1.1 ryo CLKGATE_CON(0, 57), 11), 2186 1.1 ryo RK_COMPOSITE_NOMUX(RK3588_CLK_AUX16M_0, "clk_aux16m_0", "gpll", 2187 1.1 ryo CLKSEL_CON(0, 117), __BITS(7,0), 2188 1.1 ryo CLKGATE_CON(0, 56), __BIT(2), 2189 1.1 ryo 0), 2190 1.1 ryo RK_COMPOSITE_NOMUX(RK3588_CLK_AUX16M_1, "clk_aux16m_1", "gpll", 2191 1.1 ryo CLKSEL_CON(0, 117), __BITS(15,8), 2192 1.1 ryo CLKGATE_CON(0, 56), __BIT(3), 2193 1.1 ryo 0), 2194 1.1 ryo RK_COMPOSITE_HALF(RK3588_CLK_HDMITRX_REFSRC, "clk_hdmitrx_refsrc", 2195 1.1 ryo gpll_cpll_parents, 2196 1.1 ryo CLKSEL_CON(0, 157), __BITS(7,7), 2197 1.1 ryo __BITS(6,2), 2198 1.1 ryo CLKGATE_CON(0, 65), __BIT(9), 2199 1.1 ryo 0), 2200 1.1 ryo RK_COMPOSITE(RK3588_ACLK_HDCP1_ROOT, "aclk_hdcp1_root", 2201 1.1 ryo aclk_hdcp1_root_parents, 2202 1.1 ryo CLKSEL_CON(0, 128), __BITS(6,5), __BITS(4,0), 2203 1.1 ryo CLKGATE_CON(0, 59), __BIT(0), 2204 1.1 ryo 0), 2205 1.1 ryo RK_COMPOSITE(RK3588_ACLK_HDMIRX_ROOT, "aclk_hdmirx_root", 2206 1.1 ryo gpll_cpll_parents, 2207 1.1 ryo CLKSEL_CON(0, 128), __BITS(12,12), __BITS(11,7), 2208 1.1 ryo CLKGATE_CON(0, 59), __BIT(1), 2209 1.1 ryo 0), 2210 1.1 ryo RK_COMPOSITE_NODIV(RK3588_HCLK_VO1_ROOT, "hclk_vo1_root", 2211 1.1 ryo mux_200m_100m_50m_24m_parents, 2212 1.1 ryo CLKSEL_CON(0, 128), __BITS(14,13), 2213 1.1 ryo CLKGATE_CON(0, 59), __BIT(2), 2214 1.1 ryo 0), 2215 1.1 ryo RK_COMPOSITE_NODIV(RK3588_HCLK_VO1_S_ROOT, "hclk_vo1_s_root", 2216 1.1 ryo mux_200m_100m_50m_24m_parents, 2217 1.1 ryo CLKSEL_CON(0, 129), __BITS(1,0), 2218 1.1 ryo CLKGATE_CON(0, 59), __BIT(3), 2219 1.1 ryo 0), 2220 1.1 ryo RK_COMPOSITE_NODIV(RK3588_PCLK_VO1_ROOT, "pclk_vo1_root", 2221 1.1 ryo mux_150m_100m_24m_parents, 2222 1.1 ryo CLKSEL_CON(0, 129), __BITS(3,2), 2223 1.1 ryo CLKGATE_CON(0, 59), __BIT(4), 2224 1.1 ryo 0), 2225 1.1 ryo RK_COMPOSITE_NODIV(RK3588_PCLK_VO1_S_ROOT, "pclk_vo1_s_root", 2226 1.1 ryo mux_100m_50m_24m_parents, 2227 1.1 ryo CLKSEL_CON(0, 129), __BITS(5,4), 2228 1.1 ryo CLKGATE_CON(0, 59), __BIT(5), 2229 1.1 ryo 0), 2230 1.1 ryo RK_COMPOSITE(RK3588_ACLK_VOP_ROOT, "aclk_vop_root", 2231 1.1 ryo gpll_cpll_dmyaupll_npll_spll_parents, 2232 1.1 ryo CLKSEL_CON(0, 110), __BITS(7,5), __BITS(4,0), 2233 1.1 ryo CLKGATE_CON(0, 52), __BIT(0), 2234 1.1 ryo 0), 2235 1.1 ryo RK_COMPOSITE_NODIV(RK3588_ACLK_VOP_LOW_ROOT, "aclk_vop_low_root", 2236 1.1 ryo mux_400m_200m_100m_24m_parents, 2237 1.1 ryo CLKSEL_CON(0, 110), __BITS(9,8), 2238 1.1 ryo CLKGATE_CON(0, 52), __BIT(1), 2239 1.1 ryo 0), 2240 1.1 ryo RK_COMPOSITE_NODIV(RK3588_HCLK_VOP_ROOT, "hclk_vop_root", 2241 1.1 ryo mux_200m_100m_50m_24m_parents, 2242 1.1 ryo CLKSEL_CON(0, 110), __BITS(11,10), 2243 1.1 ryo CLKGATE_CON(0, 52), __BIT(2), 2244 1.1 ryo 0), 2245 1.1 ryo RK_COMPOSITE_NODIV(RK3588_PCLK_VOP_ROOT, "pclk_vop_root", 2246 1.1 ryo mux_100m_50m_24m_parents, 2247 1.1 ryo CLKSEL_CON(0, 110), __BITS(13,12), 2248 1.1 ryo CLKGATE_CON(0, 52), __BIT(3), 2249 1.1 ryo 0), 2250 1.1 ryo RK_COMPOSITE(RK3588_ACLK_VO1USB_TOP_ROOT, "aclk_vo1usb_top_root", 2251 1.1 ryo gpll_cpll_parents, 2252 1.1 ryo CLKSEL_CON(0, 170), __BITS(5,5), __BITS(4,0), 2253 1.1 ryo CLKGATE_CON(0, 74), __BIT(0), 2254 1.1 ryo 0), 2255 1.1 ryo RK_COMPOSITE_NODIV(RK3588_HCLK_VO1USB_TOP_ROOT, "hclk_vo1usb_top_root", 2256 1.1 ryo mux_200m_100m_50m_24m_parents, 2257 1.1 ryo CLKSEL_CON(0, 170), __BITS(7,6), 2258 1.1 ryo CLKGATE_CON(0, 74), __BIT(2), 2259 1.1 ryo 0), 2260 1.1 ryo RK_MUX(RK3588_ACLK_VOP_SUB_SRC, "aclk_vop_sub_src", 2261 1.1 ryo aclk_vop_sub_src_parents, 2262 1.1 ryo CLKSEL_CON(0, 115), __BITS(9,9)), 2263 1.1 ryo RK_GATE(RK3588_PCLK_EDP0, "pclk_edp0", "pclk_vo1_root", 2264 1.1 ryo CLKGATE_CON(0, 62), 0), 2265 1.1 ryo RK_GATE(RK3588_CLK_EDP0_24M, "clk_edp0_24m", "xin24m", 2266 1.1 ryo CLKGATE_CON(0, 62), 1), 2267 1.1 ryo RK_COMPOSITE_NODIV(RK3588_CLK_EDP0_200M, "clk_edp0_200m", 2268 1.1 ryo mux_200m_100m_50m_24m_parents, 2269 1.1 ryo CLKSEL_CON(0, 140), __BITS(2,1), 2270 1.1 ryo CLKGATE_CON(0, 62), __BIT(2), 2271 1.1 ryo 0), 2272 1.1 ryo RK_GATE(RK3588_PCLK_EDP1, "pclk_edp1", "pclk_vo1_root", 2273 1.1 ryo CLKGATE_CON(0, 62), 3), 2274 1.1 ryo RK_GATE(RK3588_CLK_EDP1_24M, "clk_edp1_24m", "xin24m", 2275 1.1 ryo CLKGATE_CON(0, 62), 4), 2276 1.1 ryo RK_COMPOSITE_NODIV(RK3588_CLK_EDP1_200M, "clk_edp1_200m", 2277 1.1 ryo mux_200m_100m_50m_24m_parents, 2278 1.1 ryo CLKSEL_CON(0, 140), __BITS(4,3), 2279 1.1 ryo CLKGATE_CON(0, 62), __BIT(5), 2280 1.1 ryo 0), 2281 1.1 ryo RK_GATE(RK3588_HCLK_HDCP_KEY1, "hclk_hdcp_key1", "hclk_vo1_s_root", 2282 1.1 ryo CLKGATE_CON(0, 60), 4), 2283 1.1 ryo RK_GATE(RK3588_PCLK_HDCP1, "pclk_hdcp1", "pclk_vo1_root", 2284 1.1 ryo CLKGATE_CON(0, 60), 7), 2285 1.1 ryo RK_GATE(RK3588_ACLK_HDMIRX, "aclk_hdmirx", "aclk_hdmirx_root", 2286 1.1 ryo CLKGATE_CON(0, 61), 9), 2287 1.1 ryo RK_GATE(RK3588_PCLK_HDMIRX, "pclk_hdmirx", "pclk_vo1_root", 2288 1.1 ryo CLKGATE_CON(0, 61), 10), 2289 1.1 ryo RK_GATE(RK3588_CLK_HDMIRX_REF, "clk_hdmirx_ref", "aclk_hdcp1_root", 2290 1.1 ryo CLKGATE_CON(0, 61), 11), 2291 1.1 ryo RK_COMPOSITE(RK3588_CLK_HDMIRX_AUD_SRC, "clk_hdmirx_aud_src", 2292 1.1 ryo gpll_aupll_parents, 2293 1.1 ryo CLKSEL_CON(0, 138), __BITS(8,8), __BITS(7,0), 2294 1.1 ryo CLKGATE_CON(0, 61), __BIT(12), 2295 1.1 ryo 0), 2296 1.1 ryo RK_COMPOSITE_FRAC(RK3588_CLK_HDMIRX_AUD_FRAC, "clk_hdmirx_aud_frac", 2297 1.1 ryo "clk_hdmirx_aud_src", 2298 1.1 ryo CLKGATE_CON(0, 61), 2299 1.1 ryo RK_COMPOSITE_SET_RATE_PARENT), 2300 1.1 ryo RK_GATE(RK3588_CLK_HDMIRX_AUD, "clk_hdmirx_aud", "clk_hdmirx_aud_mux", 2301 1.1 ryo CLKGATE_CON(0, 61), 14), 2302 1.1 ryo RK_GATE(RK3588_PCLK_HDMITX0, "pclk_hdmitx0", "pclk_vo1_root", 2303 1.1 ryo CLKGATE_CON(0, 60), 11), 2304 1.1 ryo RK_COMPOSITE(RK3588_CLK_HDMITX0_EARC, "clk_hdmitx0_earc", 2305 1.1 ryo gpll_cpll_parents, 2306 1.1 ryo CLKSEL_CON(0, 133), __BITS(6,6), __BITS(5,1), 2307 1.1 ryo CLKGATE_CON(0, 60), __BIT(15), 2308 1.1 ryo 0), 2309 1.1 ryo RK_GATE(RK3588_CLK_HDMITX0_REF, "clk_hdmitx0_ref", "aclk_hdcp1_root", 2310 1.1 ryo CLKGATE_CON(0, 61), 0), 2311 1.1 ryo RK_GATE(RK3588_PCLK_HDMITX1, "pclk_hdmitx1", "pclk_vo1_root", 2312 1.1 ryo CLKGATE_CON(0, 61), 2), 2313 1.1 ryo RK_COMPOSITE(RK3588_CLK_HDMITX1_EARC, "clk_hdmitx1_earc", 2314 1.1 ryo gpll_cpll_parents, 2315 1.1 ryo CLKSEL_CON(0, 136), __BITS(6,6), __BITS(5,1), 2316 1.1 ryo CLKGATE_CON(0, 61), __BIT(6), 2317 1.1 ryo 0), 2318 1.1 ryo RK_GATE(RK3588_CLK_HDMITX1_REF, "clk_hdmitx1_ref", "aclk_hdcp1_root", 2319 1.1 ryo CLKGATE_CON(0, 61), 7), 2320 1.1 ryo RK_GATE(RK3588_ACLK_TRNG1, "aclk_trng1", "aclk_hdcp1_root", 2321 1.1 ryo CLKGATE_CON(0, 60), 9), 2322 1.1 ryo RK_GATE(RK3588_PCLK_TRNG1, "pclk_trng1", "pclk_vo1_root", 2323 1.1 ryo CLKGATE_CON(0, 60), 10), 2324 1.1 ryo RK_GATE(0, "pclk_vo1grf", "pclk_vo1_root", 2325 1.1 ryo CLKGATE_CON(0, 59), 12), 2326 1.1 ryo RK_GATE(RK3588_PCLK_S_EDP0, "pclk_s_edp0", "pclk_vo1_s_root", 2327 1.1 ryo CLKGATE_CON(0, 59), 14), 2328 1.1 ryo RK_GATE(RK3588_PCLK_S_EDP1, "pclk_s_edp1", "pclk_vo1_s_root", 2329 1.1 ryo CLKGATE_CON(0, 59), 15), 2330 1.1 ryo RK_GATE(RK3588_PCLK_S_HDMIRX, "pclk_s_hdmirx", "pclk_vo1_s_root", 2331 1.1 ryo CLKGATE_CON(0, 65), 8), 2332 1.1 ryo RK_COMPOSITE(RK3588_CLK_I2S10_8CH_RX_SRC, "clk_i2s10_8ch_rx_src", 2333 1.1 ryo gpll_aupll_parents, 2334 1.1 ryo CLKSEL_CON(0, 155), __BITS(8,8), __BITS(7,3), 2335 1.1 ryo CLKGATE_CON(0, 65), __BIT(5), 2336 1.1 ryo 0), 2337 1.1 ryo RK_COMPOSITE_FRAC(RK3588_CLK_I2S10_8CH_RX_FRAC, "clk_i2s10_8ch_rx_frac", 2338 1.1 ryo "clk_i2s10_8ch_rx_src", 2339 1.1 ryo CLKGATE_CON(0, 65), 2340 1.1 ryo RK_COMPOSITE_SET_RATE_PARENT), 2341 1.1 ryo RK_MUX(RK3588_CLK_I2S10_8CH_RX, "clk_i2s10_8ch_rx", 2342 1.1 ryo clk_i2s10_8ch_rx_parents, 2343 1.1 ryo CLKSEL_CON(0, 157), __BITS(1,0)), 2344 1.1 ryo RK_GATE(RK3588_MCLK_I2S10_8CH_RX, "mclk_i2s10_8ch_rx", 2345 1.1 ryo "clk_i2s10_8ch_rx", 2346 1.1 ryo CLKGATE_CON(0, 65), 7), 2347 1.1 ryo RK_COMPOSITE(RK3588_CLK_I2S7_8CH_RX_SRC, "clk_i2s7_8ch_rx_src", 2348 1.1 ryo gpll_aupll_parents, 2349 1.1 ryo CLKSEL_CON(0, 129), __BITS(11,11), __BITS(10,6), 2350 1.1 ryo CLKGATE_CON(0, 60), __BIT(1), 2351 1.1 ryo 0), 2352 1.1 ryo RK_COMPOSITE_FRAC(RK3588_CLK_I2S7_8CH_RX_FRAC, "clk_i2s7_8ch_rx_frac", 2353 1.1 ryo "clk_i2s7_8ch_rx_src", 2354 1.1 ryo CLKGATE_CON(0, 60), 2355 1.1 ryo RK_COMPOSITE_SET_RATE_PARENT), 2356 1.1 ryo RK_MUX(RK3588_CLK_I2S7_8CH_RX, "clk_i2s7_8ch_rx", 2357 1.1 ryo clk_i2s7_8ch_rx_parents, 2358 1.1 ryo CLKSEL_CON(0, 131), __BITS(1,0)), 2359 1.1 ryo RK_GATE(RK3588_MCLK_I2S7_8CH_RX, "mclk_i2s7_8ch_rx", "clk_i2s7_8ch_rx", 2360 1.1 ryo CLKGATE_CON(0, 60), 3), 2361 1.1 ryo RK_COMPOSITE(RK3588_CLK_I2S9_8CH_RX_SRC, "clk_i2s9_8ch_rx_src", 2362 1.1 ryo gpll_aupll_parents, 2363 1.1 ryo CLKSEL_CON(0, 153), __BITS(12,12), __BITS(11,7), 2364 1.1 ryo CLKGATE_CON(0, 65), __BIT(1), 2365 1.1 ryo 0), 2366 1.1 ryo RK_COMPOSITE_FRAC(RK3588_CLK_I2S9_8CH_RX_FRAC, "clk_i2s9_8ch_rx_frac", 2367 1.1 ryo "clk_i2s9_8ch_rx_src", 2368 1.1 ryo CLKGATE_CON(0, 65), 2369 1.1 ryo RK_COMPOSITE_SET_RATE_PARENT), 2370 1.1 ryo RK_MUX(RK3588_CLK_I2S9_8CH_RX, "clk_i2s9_8ch_rx", 2371 1.1 ryo clk_i2s9_8ch_rx_parents, 2372 1.1 ryo CLKSEL_CON(0, 155), __BITS(1,0)), 2373 1.1 ryo RK_GATE(RK3588_MCLK_I2S9_8CH_RX, "mclk_i2s9_8ch_rx", "clk_i2s9_8ch_rx", 2374 1.1 ryo CLKGATE_CON(0, 65), 3), 2375 1.1 ryo RK_COMPOSITE(RK3588_CLK_I2S5_8CH_TX_SRC, "clk_i2s5_8ch_tx_src", 2376 1.1 ryo gpll_aupll_parents, 2377 1.1 ryo CLKSEL_CON(0, 140), __BITS(10,10), __BITS(9,5), 2378 1.1 ryo CLKGATE_CON(0, 62), __BIT(6), 2379 1.1 ryo 0), 2380 1.1 ryo RK_COMPOSITE_FRAC(RK3588_CLK_I2S5_8CH_TX_FRAC, "clk_i2s5_8ch_tx_frac", 2381 1.1 ryo "clk_i2s5_8ch_tx_src", 2382 1.1 ryo CLKGATE_CON(0, 62), 2383 1.1 ryo RK_COMPOSITE_SET_RATE_PARENT), 2384 1.1 ryo RK_MUX(RK3588_CLK_I2S5_8CH_TX, "clk_i2s5_8ch_tx", 2385 1.1 ryo clk_i2s5_8ch_tx_parents, 2386 1.1 ryo CLKSEL_CON(0, 142), __BITS(1,0)), 2387 1.1 ryo RK_GATE(RK3588_MCLK_I2S5_8CH_TX, "mclk_i2s5_8ch_tx", "clk_i2s5_8ch_tx", 2388 1.1 ryo CLKGATE_CON(0, 62), 8), 2389 1.1 ryo RK_COMPOSITE(RK3588_CLK_I2S6_8CH_TX_SRC, "clk_i2s6_8ch_tx_src", 2390 1.1 ryo gpll_aupll_parents, 2391 1.1 ryo CLKSEL_CON(0, 144), __BITS(8,8), __BITS(7,3), 2392 1.1 ryo CLKGATE_CON(0, 62), __BIT(13), 2393 1.1 ryo 0), 2394 1.1 ryo RK_COMPOSITE_FRAC(RK3588_CLK_I2S6_8CH_TX_FRAC, "clk_i2s6_8ch_tx_frac", 2395 1.1 ryo "clk_i2s6_8ch_tx_src", 2396 1.1 ryo CLKGATE_CON(0, 62), 2397 1.1 ryo RK_COMPOSITE_SET_RATE_PARENT), 2398 1.1 ryo RK_MUX(RK3588_CLK_I2S6_8CH_TX, "clk_i2s6_8ch_tx", 2399 1.1 ryo clk_i2s6_8ch_tx_parents, 2400 1.1 ryo CLKSEL_CON(0, 146), __BITS(1,0)), 2401 1.1 ryo RK_GATE(RK3588_MCLK_I2S6_8CH_TX, "mclk_i2s6_8ch_tx", "clk_i2s6_8ch_tx", 2402 1.1 ryo CLKGATE_CON(0, 62), 15), 2403 1.1 ryo RK_COMPOSITE(RK3588_CLK_I2S6_8CH_RX_SRC, "clk_i2s6_8ch_rx_src", 2404 1.1 ryo gpll_aupll_parents, 2405 1.1 ryo CLKSEL_CON(0, 146), __BITS(7,7), __BITS(6,2), 2406 1.1 ryo CLKGATE_CON(0, 63), __BIT(0), 2407 1.1 ryo 0), 2408 1.1 ryo RK_COMPOSITE_FRAC(RK3588_CLK_I2S6_8CH_RX_FRAC, "clk_i2s6_8ch_rx_frac", 2409 1.1 ryo "clk_i2s6_8ch_rx_src", 2410 1.1 ryo CLKGATE_CON(0, 63), 2411 1.1 ryo RK_COMPOSITE_SET_RATE_PARENT), 2412 1.1 ryo RK_MUX(RK3588_CLK_I2S6_8CH_RX, "clk_i2s6_8ch_rx", 2413 1.1 ryo clk_i2s6_8ch_rx_parents, 2414 1.1 ryo CLKSEL_CON(0, 148), __BITS(1,0)), 2415 1.1 ryo RK_GATE(RK3588_MCLK_I2S6_8CH_RX, "mclk_i2s6_8ch_rx", "clk_i2s6_8ch_rx", 2416 1.1 ryo CLKGATE_CON(0, 63), 2), 2417 1.1 ryo RK_MUX(RK3588_I2S6_8CH_MCLKOUT, "i2s6_8ch_mclkout", 2418 1.1 ryo i2s6_8ch_mclkout_parents, 2419 1.1 ryo CLKSEL_CON(0, 148), __BITS(3,2)), 2420 1.1 ryo RK_COMPOSITE(RK3588_CLK_SPDIF3_SRC, "clk_spdif3_src", 2421 1.1 ryo gpll_aupll_parents, 2422 1.1 ryo CLKSEL_CON(0, 148), __BITS(9,9), __BITS(8,4), 2423 1.1 ryo CLKGATE_CON(0, 63), __BIT(5), 2424 1.1 ryo 0), 2425 1.1 ryo RK_COMPOSITE_FRAC(RK3588_CLK_SPDIF3_FRAC, "clk_spdif3_frac", 2426 1.1 ryo "clk_spdif3_src", 2427 1.1 ryo CLKGATE_CON(0, 63), 2428 1.1 ryo RK_COMPOSITE_SET_RATE_PARENT), 2429 1.1 ryo RK_MUX(RK3588_CLK_SPDIF3, "clk_spdif3", clk_spdif3_parents, 2430 1.1 ryo CLKSEL_CON(0, 150), __BITS(1,0)), 2431 1.1 ryo RK_GATE(RK3588_MCLK_SPDIF3, "mclk_spdif3", "clk_spdif3", 2432 1.1 ryo CLKGATE_CON(0, 63), 7), 2433 1.1 ryo RK_COMPOSITE(RK3588_CLK_SPDIF4_SRC, "clk_spdif4_src", 2434 1.1 ryo gpll_aupll_parents, 2435 1.1 ryo CLKSEL_CON(0, 150), __BITS(7,7), __BITS(6,2), 2436 1.1 ryo CLKGATE_CON(0, 63), __BIT(9), 2437 1.1 ryo 0), 2438 1.1 ryo RK_COMPOSITE_FRAC(RK3588_CLK_SPDIF4_FRAC, "clk_spdif4_frac", 2439 1.1 ryo "clk_spdif4_src", 2440 1.1 ryo CLKGATE_CON(0, 63), 2441 1.1 ryo RK_COMPOSITE_SET_RATE_PARENT), 2442 1.1 ryo RK_MUX(RK3588_CLK_SPDIF4, "clk_spdif4", clk_spdif4_parents, 2443 1.1 ryo CLKSEL_CON(0, 152), __BITS(1,0)), 2444 1.1 ryo RK_GATE(RK3588_MCLK_SPDIF4, "mclk_spdif4", "clk_spdif4", 2445 1.1 ryo CLKGATE_CON(0, 63), 11), 2446 1.1 ryo RK_COMPOSITE(RK3588_MCLK_SPDIFRX0, "mclk_spdifrx0", 2447 1.1 ryo gpll_cpll_aupll_parents, 2448 1.1 ryo CLKSEL_CON(0, 152), __BITS(8,7), __BITS(6,2), 2449 1.1 ryo CLKGATE_CON(0, 63), __BIT(13), 2450 1.1 ryo 0), 2451 1.1 ryo RK_COMPOSITE(RK3588_MCLK_SPDIFRX1, "mclk_spdifrx1", 2452 1.1 ryo gpll_cpll_aupll_parents, 2453 1.1 ryo CLKSEL_CON(0, 152), __BITS(15,14), __BITS(13,9), 2454 1.1 ryo CLKGATE_CON(0, 63), __BIT(15), 2455 1.1 ryo 0), 2456 1.1 ryo RK_COMPOSITE(RK3588_MCLK_SPDIFRX2, "mclk_spdifrx2", 2457 1.1 ryo gpll_cpll_aupll_parents, 2458 1.1 ryo CLKSEL_CON(0, 153), __BITS(6,5), __BITS(4,0), 2459 1.1 ryo CLKGATE_CON(0, 64), __BIT(1), 2460 1.1 ryo 0), 2461 1.1 ryo RK_GATE(RK3588_CLK_HDMIHDP0, "clk_hdmihdp0", "xin24m", 2462 1.1 ryo CLKGATE_CON(0, 73), 12), 2463 1.1 ryo RK_GATE(RK3588_CLK_HDMIHDP1, "clk_hdmihdp1", "xin24m", 2464 1.1 ryo CLKGATE_CON(0, 73), 13), 2465 1.1 ryo RK_GATE(RK3588_PCLK_HDPTX0, "pclk_hdptx0", "pclk_top_root", 2466 1.1 ryo CLKGATE_CON(0, 72), 5), 2467 1.1 ryo RK_GATE(RK3588_PCLK_HDPTX1, "pclk_hdptx1", "pclk_top_root", 2468 1.1 ryo CLKGATE_CON(0, 72), 6), 2469 1.1 ryo RK_GATE(RK3588_PCLK_USBDPPHY0, "pclk_usbdpphy0", "pclk_top_root", 2470 1.1 ryo CLKGATE_CON(0, 72), 2), 2471 1.1 ryo RK_GATE(RK3588_PCLK_USBDPPHY1, "pclk_usbdpphy1", "pclk_top_root", 2472 1.1 ryo CLKGATE_CON(0, 72), 4), 2473 1.1 ryo RK_GATE(RK3588_HCLK_VOP, "hclk_vop", "hclk_vop_root", 2474 1.1 ryo CLKGATE_CON(0, 52), 8), 2475 1.1 ryo RK_GATE(RK3588_ACLK_VOP, "aclk_vop", "aclk_vop_sub_src", 2476 1.1 ryo CLKGATE_CON(0, 52), 9), 2477 1.1 ryo RK_COMPOSITE(RK3588_DCLK_VOP0_SRC, "dclk_vop0_src", 2478 1.1 ryo gpll_cpll_v0pll_aupll_parents, 2479 1.1 ryo CLKSEL_CON(0, 111), __BITS(8,7), __BITS(6,0), 2480 1.1 ryo CLKGATE_CON(0, 52), __BIT(10), 2481 1.1 ryo 0), 2482 1.1 ryo RK_COMPOSITE(RK3588_DCLK_VOP1_SRC, "dclk_vop1_src", 2483 1.1 ryo gpll_cpll_v0pll_aupll_parents, 2484 1.1 ryo CLKSEL_CON(0, 111), __BITS(15,14), __BITS(13,9), 2485 1.1 ryo CLKGATE_CON(0, 52), __BIT(11), 2486 1.1 ryo 0), 2487 1.1 ryo RK_COMPOSITE(RK3588_DCLK_VOP2_SRC, "dclk_vop2_src", 2488 1.1 ryo gpll_cpll_v0pll_aupll_parents, 2489 1.1 ryo CLKSEL_CON(0, 112), __BITS(6,5), __BITS(4,0), 2490 1.1 ryo CLKGATE_CON(0, 52), __BIT(12), 2491 1.1 ryo RK_COMPOSITE_SET_RATE_PARENT), 2492 1.1 ryo RK_COMPOSITE_NODIV(RK3588_DCLK_VOP0, "dclk_vop0", 2493 1.1 ryo dclk_vop0_parents, 2494 1.1 ryo CLKSEL_CON(0, 112), __BITS(8,7), 2495 1.1 ryo CLKGATE_CON(0, 52), __BIT(13), 2496 1.1 ryo RK_COMPOSITE_SET_RATE_PARENT), 2497 1.1 ryo RK_COMPOSITE_NODIV(RK3588_DCLK_VOP1, "dclk_vop1", 2498 1.1 ryo dclk_vop1_parents, 2499 1.1 ryo CLKSEL_CON(0, 112), __BITS(10,9), 2500 1.1 ryo CLKGATE_CON(0, 53), __BIT(0), 2501 1.1 ryo RK_COMPOSITE_SET_RATE_PARENT), 2502 1.1 ryo RK_COMPOSITE_NODIV(RK3588_DCLK_VOP2, "dclk_vop2", 2503 1.1 ryo dclk_vop2_parents, 2504 1.1 ryo CLKSEL_CON(0, 112), __BITS(12,11), 2505 1.1 ryo CLKGATE_CON(0, 53), __BIT(1), 2506 1.1 ryo RK_COMPOSITE_SET_RATE_PARENT), 2507 1.1 ryo RK_COMPOSITE(RK3588_DCLK_VOP3, "dclk_vop3", 2508 1.1 ryo gpll_cpll_v0pll_aupll_parents, 2509 1.1 ryo CLKSEL_CON(0, 113), __BITS(8,7), __BITS(6,0), 2510 1.1 ryo CLKGATE_CON(0, 53), __BIT(2), 2511 1.1 ryo 0), 2512 1.1 ryo RK_GATE(RK3588_PCLK_DSIHOST0, "pclk_dsihost0", "pclk_vop_root", 2513 1.1 ryo CLKGATE_CON(0, 53), 4), 2514 1.1 ryo RK_GATE(RK3588_PCLK_DSIHOST1, "pclk_dsihost1", "pclk_vop_root", 2515 1.1 ryo CLKGATE_CON(0, 53), 5), 2516 1.1 ryo RK_COMPOSITE(RK3588_CLK_DSIHOST0, "clk_dsihost0", 2517 1.1 ryo gpll_cpll_v0pll_spll_parents, 2518 1.1 ryo CLKSEL_CON(0, 114), __BITS(8,7), __BITS(6,0), 2519 1.1 ryo CLKGATE_CON(0, 53), __BIT(6), 2520 1.1 ryo 0), 2521 1.1 ryo RK_COMPOSITE(RK3588_CLK_DSIHOST1, "clk_dsihost1", 2522 1.1 ryo gpll_cpll_v0pll_spll_parents, 2523 1.1 ryo CLKSEL_CON(0, 115), __BITS(8,7), __BITS(6,0), 2524 1.1 ryo CLKGATE_CON(0, 53), __BIT(7), 2525 1.1 ryo 0), 2526 1.1 ryo RK_GATE(RK3588_CLK_VOP_PMU, "clk_vop_pmu", "xin24m", 2527 1.1 ryo CLKGATE_CON(0, 53), 8), 2528 1.1 ryo RK_GATE(RK3588_ACLK_VOP_DOBY, "aclk_vop_doby", "aclk_vop_root", 2529 1.1 ryo CLKGATE_CON(0, 53), 10), 2530 1.1 ryo RK_GATE(RK3588_CLK_USBDP_PHY0_IMMORTAL, "clk_usbdp_phy0_immortal", 2531 1.1 ryo "xin24m", 2532 1.1 ryo CLKGATE_CON(0, 2), 8), 2533 1.1 ryo RK_GATE(RK3588_CLK_USBDP_PHY1_IMMORTAL, "clk_usbdp_phy1_immortal", 2534 1.1 ryo "xin24m", 2535 1.1 ryo CLKGATE_CON(0, 2), 15), 2536 1.1 ryo RK_GATE(RK3588_CLK_REF_PIPE_PHY0_OSC_SRC, "clk_ref_pipe_phy0_osc_src", 2537 1.1 ryo "xin24m", 2538 1.1 ryo CLKGATE_CON(0, 77), 0), 2539 1.1 ryo RK_GATE(RK3588_CLK_REF_PIPE_PHY1_OSC_SRC, "clk_ref_pipe_phy1_osc_src", 2540 1.1 ryo "xin24m", 2541 1.1 ryo CLKGATE_CON(0, 77), 1), 2542 1.1 ryo RK_GATE(RK3588_CLK_REF_PIPE_PHY2_OSC_SRC, "clk_ref_pipe_phy2_osc_src", 2543 1.1 ryo "xin24m", 2544 1.1 ryo CLKGATE_CON(0, 77), 2), 2545 1.1 ryo RK_COMPOSITE_NOMUX(RK3588_CLK_REF_PIPE_PHY0_PLL_SRC, 2546 1.1 ryo "clk_ref_pipe_phy0_pll_src", "ppll", 2547 1.1 ryo CLKSEL_CON(0, 176), __BITS(5,0), 2548 1.1 ryo CLKGATE_CON(0, 77), __BIT(3), 2549 1.1 ryo 0), 2550 1.1 ryo RK_COMPOSITE_NOMUX(RK3588_CLK_REF_PIPE_PHY1_PLL_SRC, 2551 1.1 ryo "clk_ref_pipe_phy1_pll_src", "ppll", 2552 1.1 ryo CLKSEL_CON(0, 176), __BITS(11,6), 2553 1.1 ryo CLKGATE_CON(0, 77), __BIT(4), 2554 1.1 ryo 0), 2555 1.1 ryo RK_COMPOSITE_NOMUX(RK3588_CLK_REF_PIPE_PHY2_PLL_SRC, 2556 1.1 ryo "clk_ref_pipe_phy2_pll_src", "ppll", 2557 1.1 ryo CLKSEL_CON(0, 177), __BITS(5,0), 2558 1.1 ryo CLKGATE_CON(0, 77), __BIT(5), 2559 1.1 ryo 0), 2560 1.1 ryo RK_MUX(RK3588_CLK_REF_PIPE_PHY0, "clk_ref_pipe_phy0", 2561 1.1 ryo clk_ref_pipe_phy0_parents, 2562 1.1 ryo CLKSEL_CON(0, 177), __BITS(6,6)), 2563 1.1 ryo RK_MUX(RK3588_CLK_REF_PIPE_PHY1, "clk_ref_pipe_phy1", 2564 1.1 ryo clk_ref_pipe_phy1_parents, 2565 1.1 ryo CLKSEL_CON(0, 177), __BITS(7,7)), 2566 1.1 ryo RK_MUX(RK3588_CLK_REF_PIPE_PHY2, "clk_ref_pipe_phy2", 2567 1.1 ryo clk_ref_pipe_phy2_parents, 2568 1.1 ryo CLKSEL_CON(0, 177), __BITS(8,8)), 2569 1.1 ryo RK_COMPOSITE(RK3588_CLK_PMU1_300M_SRC, "clk_pmu1_300m_src", 2570 1.1 ryo pmu_300m_24m_parents, 2571 1.1 ryo CLKSEL_CON(PMU, 0), __BITS(15,15), __BITS(14,10), 2572 1.1 ryo CLKGATE_CON(PMU, 0), __BIT(3), 2573 1.1 ryo 0), 2574 1.1 ryo RK_COMPOSITE(RK3588_CLK_PMU1_400M_SRC, "clk_pmu1_400m_src", 2575 1.1 ryo pmu_400m_24m_parents, 2576 1.1 ryo CLKSEL_CON(PMU, 1), __BITS(5,5), __BITS(4,0), 2577 1.1 ryo CLKGATE_CON(PMU, 0), __BIT(4), 2578 1.1 ryo 0), 2579 1.1 ryo RK_COMPOSITE_NOMUX(RK3588_CLK_PMU1_50M_SRC, "clk_pmu1_50m_src", 2580 1.1 ryo "clk_pmu1_400m_src", 2581 1.1 ryo CLKSEL_CON(PMU, 0), __BITS(3,0), 2582 1.1 ryo CLKGATE_CON(PMU, 0), __BIT(0), 2583 1.1 ryo 0), 2584 1.1 ryo RK_COMPOSITE_NOMUX(RK3588_CLK_PMU1_100M_SRC, "clk_pmu1_100m_src", 2585 1.1 ryo "clk_pmu1_400m_src", 2586 1.1 ryo CLKSEL_CON(PMU, 0), __BITS(6,4), 2587 1.1 ryo CLKGATE_CON(PMU, 0), __BIT(1), 2588 1.1 ryo 0), 2589 1.1 ryo RK_COMPOSITE_NOMUX(RK3588_CLK_PMU1_200M_SRC, "clk_pmu1_200m_src", 2590 1.1 ryo "clk_pmu1_400m_src", 2591 1.1 ryo CLKSEL_CON(PMU, 0), __BITS(9,7), 2592 1.1 ryo CLKGATE_CON(PMU, 0), __BIT(2), 2593 1.1 ryo 0), 2594 1.1 ryo RK_COMPOSITE_NODIV(RK3588_HCLK_PMU1_ROOT, "hclk_pmu1_root", 2595 1.1 ryo hclk_pmu1_root_parents, 2596 1.1 ryo CLKSEL_CON(PMU, 1), __BITS(7,6), 2597 1.1 ryo CLKGATE_CON(PMU, 0), __BIT(5), 2598 1.1 ryo 0), 2599 1.1 ryo RK_COMPOSITE_NODIV(RK3588_PCLK_PMU1_ROOT, "pclk_pmu1_root", 2600 1.1 ryo pmu_100m_50m_24m_src_parents, 2601 1.1 ryo CLKSEL_CON(PMU, 1), __BITS(9,8), 2602 1.1 ryo CLKGATE_CON(PMU, 0), __BIT(7), 2603 1.1 ryo 0), 2604 1.1 ryo RK_GATE(RK3588_PCLK_PMU0_ROOT, "pclk_pmu0_root", "pclk_pmu1_root", 2605 1.1 ryo CLKGATE_CON(PMU, 5), 0), 2606 1.1 ryo RK_COMPOSITE_NODIV(RK3588_HCLK_PMU_CM0_ROOT, "hclk_pmu_cm0_root", 2607 1.1 ryo hclk_pmu_cm0_root_parents, 2608 1.1 ryo CLKSEL_CON(PMU, 1), __BITS(11,10), 2609 1.1 ryo CLKGATE_CON(PMU, 0), __BIT(8), 2610 1.1 ryo 0), 2611 1.1 ryo RK_GATE(RK3588_CLK_PMU0, "clk_pmu0", "xin24m", 2612 1.1 ryo CLKGATE_CON(PMU, 5), 1), 2613 1.1 ryo RK_GATE(RK3588_PCLK_PMU0, "pclk_pmu0", "pclk_pmu0_root", 2614 1.1 ryo CLKGATE_CON(PMU, 5), 2), 2615 1.1 ryo RK_GATE(RK3588_PCLK_PMU0IOC, "pclk_pmu0ioc", "pclk_pmu0_root", 2616 1.1 ryo CLKGATE_CON(PMU, 5), 4), 2617 1.1 ryo RK_GATE(RK3588_PCLK_GPIO0, "pclk_gpio0", "pclk_pmu0_root", 2618 1.1 ryo CLKGATE_CON(PMU, 5), 5), 2619 1.1 ryo RK_COMPOSITE_NODIV(RK3588_DBCLK_GPIO0, "dbclk_gpio0", 2620 1.1 ryo mux_24m_32k_parents, 2621 1.1 ryo CLKSEL_CON(PMU, 17), __BITS(0,0), 2622 1.1 ryo CLKGATE_CON(PMU, 5), __BIT(6), 2623 1.1 ryo 0), 2624 1.1 ryo RK_GATE(RK3588_PCLK_I2C0, "pclk_i2c0", "pclk_pmu0_root", 2625 1.1 ryo CLKGATE_CON(PMU, 2), 1), 2626 1.1 ryo RK_COMPOSITE_NODIV(RK3588_CLK_I2C0, "clk_i2c0", 2627 1.1 ryo pmu_200m_100m_parents, 2628 1.1 ryo CLKSEL_CON(PMU, 3), __BITS(6,6), 2629 1.1 ryo CLKGATE_CON(PMU, 2), __BIT(2), 2630 1.1 ryo 0), 2631 1.1 ryo RK_GATE(RK3588_HCLK_I2S1_8CH, "hclk_i2s1_8ch", "hclk_pmu1_root", 2632 1.1 ryo CLKGATE_CON(PMU, 2), 7), 2633 1.1 ryo RK_COMPOSITE_NOMUX(RK3588_CLK_I2S1_8CH_TX_SRC, "clk_i2s1_8ch_tx_src", 2634 1.1 ryo "cpll", 2635 1.1 ryo CLKSEL_CON(PMU, 5), __BITS(6,2), 2636 1.1 ryo CLKGATE_CON(PMU, 2), __BIT(8), 2637 1.1 ryo 0), 2638 1.1 ryo RK_COMPOSITE_FRAC(RK3588_CLK_I2S1_8CH_TX_FRAC, "clk_i2s1_8ch_tx_frac", 2639 1.1 ryo "clk_i2s1_8ch_tx_src", 2640 1.1 ryo CLKGATE_CON(PMU, 2), 2641 1.1 ryo RK_COMPOSITE_SET_RATE_PARENT), 2642 1.1 ryo RK_MUX(RK3588_CLK_I2S1_8CH_TX, "clk_i2s1_8ch_tx", 2643 1.1 ryo clk_i2s1_8ch_tx_parents, 2644 1.1 ryo CLKSEL_CON(PMU, 7), __BITS(1,0)), 2645 1.1 ryo RK_GATE(RK3588_MCLK_I2S1_8CH_TX, "mclk_i2s1_8ch_tx", "clk_i2s1_8ch_tx", 2646 1.1 ryo CLKGATE_CON(PMU, 2), 10), 2647 1.1 ryo RK_COMPOSITE_NOMUX(RK3588_CLK_I2S1_8CH_RX_SRC, "clk_i2s1_8ch_rx_src", 2648 1.1 ryo "cpll", 2649 1.1 ryo CLKSEL_CON(PMU, 7), __BITS(6,2), 2650 1.1 ryo CLKGATE_CON(PMU, 2), __BIT(11), 2651 1.1 ryo 0), 2652 1.1 ryo RK_COMPOSITE_FRAC(RK3588_CLK_I2S1_8CH_RX_FRAC, "clk_i2s1_8ch_rx_frac", 2653 1.1 ryo "clk_i2s1_8ch_rx_src", 2654 1.1 ryo CLKGATE_CON(PMU, 2), 2655 1.1 ryo RK_COMPOSITE_SET_RATE_PARENT), 2656 1.1 ryo RK_MUX(RK3588_CLK_I2S1_8CH_RX, "clk_i2s1_8ch_rx", 2657 1.1 ryo clk_i2s1_8ch_rx_parents, 2658 1.1 ryo CLKSEL_CON(PMU, 9), __BITS(1,0)), 2659 1.1 ryo RK_GATE(RK3588_MCLK_I2S1_8CH_RX, "mclk_i2s1_8ch_rx", "clk_i2s1_8ch_rx", 2660 1.1 ryo CLKGATE_CON(PMU, 2), 13), 2661 1.1 ryo RK_MUX(RK3588_I2S1_8CH_MCLKOUT, "i2s1_8ch_mclkout", 2662 1.1 ryo i2s1_8ch_mclkout_parents, 2663 1.1 ryo CLKSEL_CON(PMU, 9), __BITS(3,2)), 2664 1.1 ryo RK_GATE(RK3588_PCLK_PMU1, "pclk_pmu1", "pclk_pmu0_root", 2665 1.1 ryo CLKGATE_CON(PMU, 1), 0), 2666 1.1 ryo RK_GATE(RK3588_CLK_DDR_FAIL_SAFE, "clk_ddr_fail_safe", "clk_pmu0", 2667 1.1 ryo CLKGATE_CON(PMU, 1), 1), 2668 1.1 ryo RK_GATE(RK3588_CLK_PMU1, "clk_pmu1", "clk_pmu0", 2669 1.1 ryo CLKGATE_CON(PMU, 1), 3), 2670 1.1 ryo RK_GATE(RK3588_HCLK_PDM0, "hclk_pdm0", "hclk_pmu1_root", 2671 1.1 ryo CLKGATE_CON(PMU, 2), 14), 2672 1.1 ryo RK_COMPOSITE_NODIV(RK3588_MCLK_PDM0, "mclk_pdm0", 2673 1.1 ryo mclk_pdm0_parents, 2674 1.1 ryo CLKSEL_CON(PMU, 9), __BITS(4,4), 2675 1.1 ryo CLKGATE_CON(PMU, 2), __BIT(15), 2676 1.1 ryo 0), 2677 1.1 ryo RK_GATE(RK3588_HCLK_VAD, "hclk_vad", "hclk_pmu1_root", 2678 1.1 ryo CLKGATE_CON(PMU, 3), 0), 2679 1.1 ryo RK_GATE(RK3588_FCLK_PMU_CM0_CORE, "fclk_pmu_cm0_core", 2680 1.1 ryo "hclk_pmu_cm0_root", 2681 1.1 ryo CLKGATE_CON(PMU, 0), 13), 2682 1.1 ryo RK_COMPOSITE(RK3588_CLK_PMU_CM0_RTC, "clk_pmu_cm0_rtc", 2683 1.1 ryo mux_24m_32k_parents, 2684 1.1 ryo CLKSEL_CON(PMU, 2), __BITS(5,5), __BITS(4,0), 2685 1.1 ryo CLKGATE_CON(PMU, 0), __BIT(15), 2686 1.1 ryo 0), 2687 1.1 ryo RK_GATE(RK3588_PCLK_PMU1_IOC, "pclk_pmu1_ioc", "pclk_pmu0_root", 2688 1.1 ryo CLKGATE_CON(PMU, 1), 5), 2689 1.1 ryo RK_GATE(RK3588_PCLK_PMU1PWM, "pclk_pmu1pwm", "pclk_pmu0_root", 2690 1.1 ryo CLKGATE_CON(PMU, 1), 12), 2691 1.1 ryo RK_COMPOSITE_NODIV(RK3588_CLK_PMU1PWM, "clk_pmu1pwm", 2692 1.1 ryo pmu_100m_50m_24m_src_parents, 2693 1.1 ryo CLKSEL_CON(PMU, 2), __BITS(10,9), 2694 1.1 ryo CLKGATE_CON(PMU, 1), __BIT(13), 2695 1.1 ryo 0), 2696 1.1 ryo RK_GATE(RK3588_CLK_PMU1PWM_CAPTURE, "clk_pmu1pwm_capture", "xin24m", 2697 1.1 ryo CLKGATE_CON(PMU, 1), 14), 2698 1.1 ryo RK_GATE(RK3588_PCLK_PMU1TIMER, "pclk_pmu1timer", "pclk_pmu0_root", 2699 1.1 ryo CLKGATE_CON(PMU, 1), 8), 2700 1.1 ryo RK_COMPOSITE_NODIV(RK3588_CLK_PMU1TIMER_ROOT, "clk_pmu1timer_root", 2701 1.1 ryo pmu_24m_32k_100m_src_parents, 2702 1.1 ryo CLKSEL_CON(PMU, 2), __BITS(8,7), 2703 1.1 ryo CLKGATE_CON(PMU, 1), __BIT(9), 2704 1.1 ryo 0), 2705 1.1 ryo RK_GATE(RK3588_CLK_PMU1TIMER0, "clk_pmu1timer0", "clk_pmu1timer_root", 2706 1.1 ryo CLKGATE_CON(PMU, 1), 10), 2707 1.1 ryo RK_GATE(RK3588_CLK_PMU1TIMER1, "clk_pmu1timer1", "clk_pmu1timer_root", 2708 1.1 ryo CLKGATE_CON(PMU, 1), 11), 2709 1.1 ryo RK_COMPOSITE_NOMUX(RK3588_CLK_UART0_SRC, "clk_uart0_src", "cpll", 2710 1.1 ryo CLKSEL_CON(PMU, 3), __BITS(11,7), 2711 1.1 ryo CLKGATE_CON(PMU, 2), __BIT(3), 2712 1.1 ryo 0), 2713 1.1 ryo RK_COMPOSITE_FRAC(RK3588_CLK_UART0_FRAC, "clk_uart0_frac", 2714 1.1 ryo "clk_uart0_src", 2715 1.1 ryo CLKGATE_CON(PMU, 2), 2716 1.1 ryo RK_COMPOSITE_SET_RATE_PARENT), 2717 1.1 ryo RK_MUX(RK3588_CLK_UART0, "clk_uart0", clk_uart0_parents, 2718 1.1 ryo CLKSEL_CON(PMU, 5), __BITS(1,0)), 2719 1.1 ryo RK_GATE(RK3588_SCLK_UART0, "sclk_uart0", "clk_uart0", 2720 1.1 ryo CLKGATE_CON(PMU, 2), 5), 2721 1.1 ryo RK_GATE(RK3588_PCLK_UART0, "pclk_uart0", "pclk_pmu0_root", 2722 1.1 ryo CLKGATE_CON(PMU, 2), 6), 2723 1.1 ryo RK_GATE(RK3588_PCLK_PMU1WDT, "pclk_pmu1wdt", "pclk_pmu0_root", 2724 1.1 ryo CLKGATE_CON(PMU, 1), 6), 2725 1.1 ryo RK_COMPOSITE_NODIV(RK3588_TCLK_PMU1WDT, "tclk_pmu1wdt", 2726 1.1 ryo mux_24m_32k_parents, 2727 1.1 ryo CLKSEL_CON(PMU, 2), __BITS(6,6), 2728 1.1 ryo CLKGATE_CON(PMU, 1), __BIT(7), 2729 1.1 ryo 0), 2730 1.1 ryo RK_COMPOSITE(RK3588_CLK_CR_PARA, "clk_cr_para", 2731 1.1 ryo mux_24m_ppll_spll_parents, 2732 1.1 ryo CLKSEL_CON(PMU, 15), __BITS(6,5), __BITS(4,0), 2733 1.1 ryo CLKGATE_CON(PMU, 4), __BIT(11), 2734 1.1 ryo 0), 2735 1.1 ryo RK_COMPOSITE(RK3588_CLK_USB2PHY_HDPTXRXPHY_REF, 2736 1.1 ryo "clk_usb2phy_hdptxrxphy_ref", mux_24m_ppll_parents, 2737 1.1 ryo CLKSEL_CON(PMU, 14), __BITS(14,14), __BITS(13,9), 2738 1.1 ryo CLKGATE_CON(PMU, 4), __BIT(7), 2739 1.1 ryo 0), 2740 1.1 ryo RK_COMPOSITE(RK3588_CLK_USBDPPHY_MIPIDCPPHY_REF, 2741 1.1 ryo "clk_usbdpphy_mipidcpphy_ref", mux_24m_ppll_spll_parents, 2742 1.1 ryo CLKSEL_CON(PMU, 14), __BITS(8,7), __BITS(6,0), 2743 1.1 ryo CLKGATE_CON(PMU, 4), __BIT(3), 2744 1.1 ryo 0), 2745 1.1 ryo RK_GATE(RK3588_CLK_PHY0_REF_ALT_P, "clk_phy0_ref_alt_p", "ppll", 2746 1.1 ryo RK3588_PHYREF_ALT_GATE, 0), 2747 1.1 ryo RK_GATE(RK3588_CLK_PHY0_REF_ALT_M, "clk_phy0_ref_alt_m", "ppll", 2748 1.1 ryo RK3588_PHYREF_ALT_GATE, 1), 2749 1.1 ryo RK_GATE(RK3588_CLK_PHY1_REF_ALT_P, "clk_phy1_ref_alt_p", "ppll", 2750 1.1 ryo RK3588_PHYREF_ALT_GATE, 2), 2751 1.1 ryo RK_GATE(RK3588_CLK_PHY1_REF_ALT_M, "clk_phy1_ref_alt_m", "ppll", 2752 1.1 ryo RK3588_PHYREF_ALT_GATE, 3), 2753 1.1 ryo RK_GATE(RK3588_HCLK_SPDIFRX0, "hclk_spdifrx0", "hclk_vo1", 2754 1.1 ryo CLKGATE_CON(0, 63), 12), 2755 1.1 ryo RK_GATE(RK3588_HCLK_SPDIFRX1, "hclk_spdifrx1", "hclk_vo1", 2756 1.1 ryo CLKGATE_CON(0, 63), 14), 2757 1.1 ryo RK_GATE(RK3588_HCLK_SPDIFRX2, "hclk_spdifrx2", "hclk_vo1", 2758 1.1 ryo CLKGATE_CON(0, 64), 0), 2759 1.1 ryo RK_GATE(RK3588_HCLK_SPDIF4, "hclk_spdif4", "hclk_vo1", 2760 1.1 ryo CLKGATE_CON(0, 63), 8), 2761 1.1 ryo RK_GATE(RK3588_HCLK_SPDIF3, "hclk_spdif3", "hclk_vo1", 2762 1.1 ryo CLKGATE_CON(0, 63), 4), 2763 1.1 ryo RK_GATE(RK3588_HCLK_I2S6_8CH, "hclk_i2s6_8ch", "hclk_vo1", 2764 1.1 ryo CLKGATE_CON(0, 63), 3), 2765 1.1 ryo RK_GATE(RK3588_HCLK_I2S5_8CH, "hclk_i2s5_8ch", "hclk_vo1", 2766 1.1 ryo CLKGATE_CON(0, 62), 12), 2767 1.1 ryo RK_GATE(RK3588_HCLK_I2S9_8CH, "hclk_i2s9_8ch", "hclk_vo1", 2768 1.1 ryo CLKGATE_CON(0, 65), 0), 2769 1.1 ryo RK_GATE(RK3588_HCLK_I2S7_8CH, "hclk_i2s7_8ch", "hclk_vo1", 2770 1.1 ryo CLKGATE_CON(0, 60), 0), 2771 1.1 ryo RK_GATE(RK3588_HCLK_I2S10_8CH, "hclk_i2s10_8ch", "hclk_vo1", 2772 1.1 ryo CLKGATE_CON(0, 65), 4), 2773 1.1 ryo RK_GATE(RK3588_ACLK_HDCP1, "aclk_hdcp1", "aclk_hdcp1_pre", 2774 1.1 ryo CLKGATE_CON(0, 60), 5), 2775 1.1 ryo RK_GATE(RK3588_HCLK_HDCP1, "hclk_hdcp1", "hclk_vo1", 2776 1.1 ryo CLKGATE_CON(0, 60), 6), 2777 1.1 ryo RK_GATE(RK3588_HCLK_SPDIF5_DP1, "hclk_spdif5_dp1", "hclk_vo0", 2778 1.1 ryo CLKGATE_CON(0, 57), 7), 2779 1.1 ryo RK_GATE(RK3588_HCLK_SPDIF2_DP0, "hclk_spdif2_dp0", "hclk_vo0", 2780 1.1 ryo CLKGATE_CON(0, 57), 2), 2781 1.1 ryo RK_GATE(RK3588_HCLK_I2S8_8CH, "hclk_i2s8_8ch", "hclk_vo0", 2782 1.1 ryo CLKGATE_CON(0, 56), 14), 2783 1.1 ryo RK_GATE(RK3588_HCLK_I2S4_8CH, "hclk_i2s4_8ch", "hclk_vo0", 2784 1.1 ryo CLKGATE_CON(0, 56), 10), 2785 1.1 ryo RK_GATE(RK3588_ACLK_HDCP0, "aclk_hdcp0", "aclk_hdcp0_pre", 2786 1.1 ryo CLKGATE_CON(0, 55), 12), 2787 1.1 ryo RK_GATE(RK3588_HCLK_HDCP0, "hclk_hdcp0", "hclk_vo0", 2788 1.1 ryo CLKGATE_CON(0, 55), 13), 2789 1.1 ryo RK_GATE(RK3588_HCLK_RKVENC1, "hclk_rkvenc1", "hclk_rkvenc1_pre", 2790 1.1 ryo CLKGATE_CON(0, 48), 4), 2791 1.1 ryo RK_GATE(RK3588_ACLK_RKVENC1, "aclk_rkvenc1", "aclk_rkvenc1_pre", 2792 1.1 ryo CLKGATE_CON(0, 48), 5), 2793 1.1 ryo RK_GATE(RK3588_ACLK_VPU, "aclk_vpu", "aclk_vdpu_low_pre", 2794 1.1 ryo CLKGATE_CON(0, 44), 8), 2795 1.1 ryo RK_GATE(RK3588_ACLK_IEP2P0, "aclk_iep2p0", "aclk_vdpu_low_pre", 2796 1.1 ryo CLKGATE_CON(0, 45), 5), 2797 1.1 ryo RK_GATE(RK3588_ACLK_JPEG_ENCODER0, "aclk_jpeg_encoder0", 2798 1.1 ryo "aclk_vdpu_low_pre", 2799 1.1 ryo CLKGATE_CON(0, 44), 10), 2800 1.1 ryo RK_GATE(RK3588_ACLK_JPEG_ENCODER1, "aclk_jpeg_encoder1", 2801 1.1 ryo "aclk_vdpu_low_pre", 2802 1.1 ryo CLKGATE_CON(0, 44), 12), 2803 1.1 ryo RK_GATE(RK3588_ACLK_JPEG_ENCODER2, "aclk_jpeg_encoder2", 2804 1.1 ryo "aclk_vdpu_low_pre", 2805 1.1 ryo CLKGATE_CON(0, 44), 14), 2806 1.1 ryo RK_GATE(RK3588_ACLK_JPEG_ENCODER3, "aclk_jpeg_encoder3", 2807 1.1 ryo "aclk_vdpu_low_pre", 2808 1.1 ryo CLKGATE_CON(0, 45), 0), 2809 1.1 ryo RK_GATE(RK3588_ACLK_JPEG_DECODER, "aclk_jpeg_decoder", 2810 1.1 ryo "aclk_jpeg_decoder_pre", 2811 1.1 ryo CLKGATE_CON(0, 45), 2), 2812 1.1 ryo RK_GATE(RK3588_ACLK_USB3OTG1, "aclk_usb3otg1", "aclk_usb", 2813 1.1 ryo CLKGATE_CON(0, 42), 7), 2814 1.1 ryo RK_GATE(RK3588_HCLK_HOST0, "hclk_host0", "hclk_usb", 2815 1.1 ryo CLKGATE_CON(0, 42), 10), 2816 1.1 ryo RK_GATE(RK3588_HCLK_HOST_ARB0, "hclk_host_arb0", "hclk_usb", 2817 1.1 ryo CLKGATE_CON(0, 42), 11), 2818 1.1 ryo RK_GATE(RK3588_HCLK_HOST1, "hclk_host1", "hclk_usb", 2819 1.1 ryo CLKGATE_CON(0, 42), 12), 2820 1.1 ryo RK_GATE(RK3588_HCLK_HOST_ARB1, "hclk_host_arb1", "hclk_usb", 2821 1.1 ryo CLKGATE_CON(0, 42), 13), 2822 1.1 ryo RK_GATE(RK3588_ACLK_USB3OTG0, "aclk_usb3otg0", "aclk_usb", 2823 1.1 ryo CLKGATE_CON(0, 42), 4), 2824 1.1 ryo RK_GATE(RK3588_HCLK_SDIO, "hclk_sdio", "hclk_sdio_pre", 2825 1.1 ryo CLKGATE_CON(0, 75), 2), 2826 1.1 ryo RK_GATE(RK3588_HCLK_RKVDEC1, "hclk_rkvdec1", "hclk_rkvdec1_pre", 2827 1.1 ryo CLKGATE_CON(0, 41), 2), 2828 1.1 ryo RK_GATE(RK3588_ACLK_RKVDEC1, "aclk_rkvdec1", "aclk_rkvdec1_pre", 2829 1.1 ryo CLKGATE_CON(0, 41), 3), 2830 1.1 ryo RK_GATE(RK3588_HCLK_RKVDEC0, "hclk_rkvdec0", "hclk_rkvdec0_pre", 2831 1.1 ryo CLKGATE_CON(0, 40), 3), 2832 1.1 ryo RK_GATE(RK3588_ACLK_RKVDEC0, "aclk_rkvdec0", "aclk_rkvdec0_pre", 2833 1.1 ryo CLKGATE_CON(0, 40), 4), 2834 1.1 ryo RK_GATE(RK3588_CLK_PCIE4L_PIPE, "clk_pcie4l_pipe", 2835 1.1 ryo "clk_pipe30phy_pipe0_i", 2836 1.1 ryo CLKGATE_CON(0, 39), 0), 2837 1.1 ryo RK_GATE(RK3588_CLK_PCIE2L_PIPE, "clk_pcie2l_pipe", 2838 1.1 ryo "clk_pipe30phy_pipe2_i", 2839 1.1 ryo CLKGATE_CON(0, 39), 1), 2840 1.1 ryo RK_GATE(RK3588_CLK_PIPEPHY0_PIPE_G, "clk_pipephy0_pipe_g", 2841 1.1 ryo "clk_pipephy0_pipe_i", 2842 1.1 ryo CLKGATE_CON(0, 38), 3), 2843 1.1 ryo RK_GATE(RK3588_CLK_PIPEPHY1_PIPE_G, "clk_pipephy1_pipe_g", 2844 1.1 ryo "clk_pipephy1_pipe_i", 2845 1.1 ryo CLKGATE_CON(0, 38), 4), 2846 1.1 ryo RK_GATE(RK3588_CLK_PIPEPHY2_PIPE_G, "clk_pipephy2_pipe_g", 2847 1.1 ryo "clk_pipephy2_pipe_i", 2848 1.1 ryo CLKGATE_CON(0, 38), 5), 2849 1.1 ryo RK_GATE(RK3588_CLK_PIPEPHY0_PIPE_ASIC_G, "clk_pipephy0_pipe_asic_g", 2850 1.1 ryo "clk_pipephy0_pipe_i", 2851 1.1 ryo CLKGATE_CON(0, 38), 6), 2852 1.1 ryo RK_GATE(RK3588_CLK_PIPEPHY1_PIPE_ASIC_G, "clk_pipephy1_pipe_asic_g", 2853 1.1 ryo "clk_pipephy1_pipe_i", 2854 1.1 ryo CLKGATE_CON(0, 38), 7), 2855 1.1 ryo RK_GATE(RK3588_CLK_PIPEPHY2_PIPE_ASIC_G, "clk_pipephy2_pipe_asic_g", 2856 1.1 ryo "clk_pipephy2_pipe_i", 2857 1.1 ryo CLKGATE_CON(0, 38), 8), 2858 1.1 ryo RK_GATE(RK3588_CLK_PIPEPHY2_PIPE_U3_G, "clk_pipephy2_pipe_u3_g", 2859 1.1 ryo "clk_pipephy2_pipe_i", 2860 1.1 ryo CLKGATE_CON(0, 38), 9), 2861 1.1 ryo RK_GATE(RK3588_CLK_PCIE1L2_PIPE, "clk_pcie1l2_pipe", 2862 1.1 ryo "clk_pipephy0_pipe_g", 2863 1.1 ryo CLKGATE_CON(0, 38), 13), 2864 1.1 ryo RK_GATE(RK3588_CLK_PCIE1L0_PIPE, "clk_pcie1l0_pipe", 2865 1.1 ryo "clk_pipephy1_pipe_g", 2866 1.1 ryo CLKGATE_CON(0, 38), 14), 2867 1.1 ryo RK_GATE(RK3588_CLK_PCIE1L1_PIPE, "clk_pcie1l1_pipe", 2868 1.1 ryo "clk_pipephy2_pipe_g", 2869 1.1 ryo CLKGATE_CON(0, 38), 15), 2870 1.1 ryo RK_GATE(RK3588_HCLK_SFC, "hclk_sfc", "hclk_nvm", 2871 1.1 ryo CLKGATE_CON(0, 31), 10), 2872 1.1 ryo RK_GATE(RK3588_HCLK_SFC_XIP, "hclk_sfc_xip", "hclk_nvm", 2873 1.1 ryo CLKGATE_CON(0, 31), 11), 2874 1.1 ryo RK_GATE(RK3588_HCLK_EMMC, "hclk_emmc", "hclk_nvm", 2875 1.1 ryo CLKGATE_CON(0, 31), 4), 2876 1.1 ryo RK_GATE(RK3588_ACLK_ISP1, "aclk_isp1", "aclk_isp1_pre", 2877 1.1 ryo CLKGATE_CON(0, 26), 5), 2878 1.1 ryo RK_GATE(RK3588_HCLK_ISP1, "hclk_isp1", "hclk_isp1_pre", 2879 1.1 ryo CLKGATE_CON(0, 26), 7), 2880 1.1 ryo RK_GATE(RK3588_PCLK_AV1, "pclk_av1", "pclk_av1_pre", 2881 1.1 ryo CLKGATE_CON(0, 68), 5), 2882 1.1 ryo RK_GATE(RK3588_ACLK_AV1, "aclk_av1", "aclk_av1_pre", 2883 1.1 ryo CLKGATE_CON(0, 68), 2), 2884 1.1 ryo 2885 1.1 ryo #if 0 2886 1.1 ryo notyet 2887 1.1 ryo #define RK3588_SDIO_CON0 0x0c24 2888 1.1 ryo #define RK3588_SDIO_CON1 0x0c28 2889 1.1 ryo #define RK3588_SDMMC_CON0 0x0c30 2890 1.1 ryo #define RK3588_SDMMC_CON1 0x0c34 2891 1.1 ryo SCLK_SDIO_DRV, "sdio_drv","cclk_src_sdio", RK3588_SDIO_CON0 2892 1.1 ryo SCLK_SDIO_SAMPLE, "sdio_sample", "cclk_src_sdio", RK3588_SDIO_CON1 2893 1.1 ryo SCLK_SDMMC_DRV, "sdmmc_drv", "scmi_cclk_sd", RK3588_SDMMC_CON0 2894 1.1 ryo SCLK_SDMMC_SAMPLE, "sdmmc_sample", "scmi_cclk_sd", RK3588_SDMMC_CON1 2895 1.1 ryo #endif 2896 1.1 ryo 2897 1.1 ryo }; 2898 1.1 ryo 2899 1.1 ryo static void 2900 1.1 ryo rk3588_cru_init(struct rk_cru_softc *sc) 2901 1.1 ryo { 2902 1.1 ryo } 2903 1.1 ryo 2904 1.1 ryo static int 2905 1.1 ryo rk3588_cru_match(device_t parent, cfdata_t cf, void *aux) 2906 1.1 ryo { 2907 1.1 ryo struct fdt_attach_args * const faa = aux; 2908 1.1 ryo return of_compatible_match(faa->faa_phandle, compat_data); 2909 1.1 ryo } 2910 1.1 ryo 2911 1.1 ryo static void 2912 1.1 ryo rk3588_cru_attach(device_t parent, device_t self, void *aux) 2913 1.1 ryo { 2914 1.1 ryo struct rk_cru_softc * const sc = device_private(self); 2915 1.1 ryo struct fdt_attach_args * const faa = aux; 2916 1.1 ryo 2917 1.1 ryo sc->sc_dev = self; 2918 1.1 ryo sc->sc_phandle = faa->faa_phandle; 2919 1.1 ryo sc->sc_bst = faa->faa_bst; 2920 1.1 ryo sc->sc_clks = rk3588_cru_clks; 2921 1.1 ryo sc->sc_nclks = __arraycount(rk3588_cru_clks); 2922 1.1 ryo 2923 1.1 ryo sc->sc_grf_soc_status = 0x0480; /* XXX */ 2924 1.1 ryo sc->sc_softrst_base = SOFTRST_CON(0, 0); /* XXX */ 2925 1.1 ryo 2926 1.1 ryo if (rk_cru_attach(sc) != 0) 2927 1.1 ryo return; 2928 1.1 ryo 2929 1.1 ryo aprint_naive("\n"); 2930 1.1 ryo aprint_normal(": RK3588 CRU\n"); 2931 1.1 ryo 2932 1.1 ryo rk3588_cru_init(sc); 2933 1.1 ryo 2934 1.1 ryo rk_cru_print(sc); 2935 1.1 ryo } 2936
Indexes created Sun Sep 28 07:09:56 GMT 2025