rk_cru.h revision 1.3
1 /* $NetBSD: rk_cru.h,v 1.3 2018/08/12 16:48:05 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2018 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #ifndef _ARM_RK_CRU_H 30 #define _ARM_RK_CRU_H 31 32 #include <dev/clk/clk_backend.h> 33 #include <dev/fdt/syscon.h> 34 35 struct rk_cru_softc; 36 struct rk_cru_clk; 37 38 /* 39 * Clocks 40 */ 41 42 enum rk_cru_clktype { 43 RK_CRU_UNKNOWN, 44 RK_CRU_PLL, 45 RK_CRU_ARM, 46 RK_CRU_COMPOSITE, 47 RK_CRU_GATE, 48 RK_CRU_MUX, 49 }; 50 51 /* PLL clocks */ 52 53 struct rk_cru_pll_rate { 54 u_int rate; 55 u_int refdiv; 56 u_int fbdiv; 57 u_int postdiv1; 58 u_int postdiv2; 59 u_int dsmpd; 60 u_int fracdiv; 61 }; 62 63 #define RK_PLL_RATE(_rate, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _fracdiv) \ 64 { \ 65 .rate = (_rate), \ 66 .refdiv = (_refdiv), \ 67 .fbdiv = (_fbdiv), \ 68 .postdiv1 = (_postdiv1), \ 69 .postdiv2 = (_postdiv2), \ 70 .dsmpd = (_dsmpd), \ 71 .fracdiv = (_fracdiv), \ 72 } 73 74 struct rk_cru_pll { 75 bus_size_t con_base; 76 bus_size_t mode_reg; 77 uint32_t mode_mask; 78 uint32_t lock_mask; 79 const struct rk_cru_pll_rate *rates; 80 u_int nrates; 81 const char **parents; 82 u_int nparents; 83 }; 84 85 u_int rk_cru_pll_get_rate(struct rk_cru_softc *, struct rk_cru_clk *); 86 int rk_cru_pll_set_rate(struct rk_cru_softc *, struct rk_cru_clk *, u_int); 87 const char *rk_cru_pll_get_parent(struct rk_cru_softc *, struct rk_cru_clk *); 88 89 #define RK_PLL(_id, _name, _parents, _con_base, _mode_reg, _mode_mask, _lock_mask, _rates) \ 90 { \ 91 .id = (_id), \ 92 .type = RK_CRU_PLL, \ 93 .base.name = (_name), \ 94 .base.flags = 0, \ 95 .u.pll.parents = (_parents), \ 96 .u.pll.nparents = __arraycount(_parents), \ 97 .u.pll.con_base = (_con_base), \ 98 .u.pll.mode_reg = (_mode_reg), \ 99 .u.pll.mode_mask = (_mode_mask), \ 100 .u.pll.lock_mask = (_lock_mask), \ 101 .u.pll.rates = (_rates), \ 102 .u.pll.nrates = __arraycount(_rates), \ 103 .get_rate = rk_cru_pll_get_rate, \ 104 .set_rate = rk_cru_pll_set_rate, \ 105 .get_parent = rk_cru_pll_get_parent, \ 106 } 107 108 /* ARM clocks */ 109 110 struct rk_cru_arm_rate { 111 u_int rate; 112 u_int div; 113 }; 114 115 #define RK_ARM_RATE(_rate, _div) \ 116 { \ 117 .rate = (_rate), \ 118 .div = (_div), \ 119 } 120 121 struct rk_cru_arm { 122 bus_size_t reg; 123 uint32_t mux_mask; 124 u_int mux_main; 125 u_int mux_alt; 126 uint32_t div_mask; 127 const char **parents; 128 u_int nparents; 129 const struct rk_cru_arm_rate *rates; 130 u_int nrates; 131 }; 132 133 u_int rk_cru_arm_get_rate(struct rk_cru_softc *, struct rk_cru_clk *); 134 int rk_cru_arm_set_rate(struct rk_cru_softc *, struct rk_cru_clk *, u_int); 135 const char *rk_cru_arm_get_parent(struct rk_cru_softc *, struct rk_cru_clk *); 136 int rk_cru_arm_set_parent(struct rk_cru_softc *, struct rk_cru_clk *, const char *); 137 138 #define RK_ARM(_id, _name, _parents, _reg, _mux_mask, _mux_main, _mux_alt, _div_mask, _rates) \ 139 { \ 140 .id = (_id), \ 141 .type = RK_CRU_ARM, \ 142 .base.name = (_name), \ 143 .base.flags = 0, \ 144 .u.arm.parents = (_parents), \ 145 .u.arm.nparents = __arraycount(_parents), \ 146 .u.arm.reg = (_reg), \ 147 .u.arm.mux_mask = (_mux_mask), \ 148 .u.arm.mux_main = (_mux_main), \ 149 .u.arm.mux_alt = (_mux_alt), \ 150 .u.arm.div_mask = (_div_mask), \ 151 .u.arm.rates = (_rates), \ 152 .u.arm.nrates = __arraycount(_rates), \ 153 .get_rate = rk_cru_arm_get_rate, \ 154 .set_rate = rk_cru_arm_set_rate, \ 155 .get_parent = rk_cru_arm_get_parent, \ 156 .set_parent = rk_cru_arm_set_parent, \ 157 } 158 159 /* Composite clocks */ 160 161 struct rk_cru_composite { 162 bus_size_t muxdiv_reg; 163 uint32_t mux_mask; 164 uint32_t div_mask; 165 bus_size_t gate_reg; 166 uint32_t gate_mask; 167 const char **parents; 168 u_int nparents; 169 u_int flags; 170 #define RK_COMPOSITE_ROUND_DOWN 0x01 171 }; 172 173 int rk_cru_composite_enable(struct rk_cru_softc *, struct rk_cru_clk *, int); 174 u_int rk_cru_composite_get_rate(struct rk_cru_softc *, struct rk_cru_clk *); 175 int rk_cru_composite_set_rate(struct rk_cru_softc *, struct rk_cru_clk *, u_int); 176 const char *rk_cru_composite_get_parent(struct rk_cru_softc *, struct rk_cru_clk *); 177 int rk_cru_composite_set_parent(struct rk_cru_softc *, struct rk_cru_clk *, const char *); 178 179 #define RK_COMPOSITE(_id, _name, _parents, _muxdiv_reg, _mux_mask, _div_mask, _gate_reg, _gate_mask, _flags) \ 180 { \ 181 .id = (_id), \ 182 .type = RK_CRU_COMPOSITE, \ 183 .base.name = (_name), \ 184 .base.flags = 0, \ 185 .u.composite.parents = (_parents), \ 186 .u.composite.nparents = __arraycount(_parents), \ 187 .u.composite.muxdiv_reg = (_muxdiv_reg), \ 188 .u.composite.mux_mask = (_mux_mask), \ 189 .u.composite.div_mask = (_div_mask), \ 190 .u.composite.gate_reg = (_gate_reg), \ 191 .u.composite.gate_mask = (_gate_mask), \ 192 .u.composite.flags = (_flags), \ 193 .enable = rk_cru_composite_enable, \ 194 .get_rate = rk_cru_composite_get_rate, \ 195 .set_rate = rk_cru_composite_set_rate, \ 196 .get_parent = rk_cru_composite_get_parent, \ 197 .set_parent = rk_cru_composite_set_parent, \ 198 } 199 200 #define RK_COMPOSITE_NOMUX(_id, _name, _parent, _div_reg, _div_mask, _gate_reg, _gate_mask, _flags) \ 201 RK_COMPOSITE(_id, _name, (const char *[]){ _parent }, _div_reg, 0, _div_mask, _gate_reg, _gate_mask, _flags) 202 203 #define RK_COMPOSITE_NOGATE(_id, _name, _parents, _muxdiv_reg, _mux_mask, _div_mask, _flags) \ 204 RK_COMPOSITE(_id, _name, _parents, _muxdiv_reg, _mux_mask, _div_mask, 0, 0, _flags) 205 206 #define RK_DIV(_id, _name, _parent, _div_reg, _div_mask, _flags) \ 207 RK_COMPOSITE(_id, _name, (const char *[]){ _parent }, _div_reg, 0, _div_mask, 0, 0, _flags) 208 209 /* Gate clocks */ 210 211 struct rk_cru_gate { 212 bus_size_t reg; 213 uint32_t mask; 214 const char *parent; 215 }; 216 217 int rk_cru_gate_enable(struct rk_cru_softc *, 218 struct rk_cru_clk *, int); 219 const char *rk_cru_gate_get_parent(struct rk_cru_softc *, 220 struct rk_cru_clk *); 221 222 #define RK_GATE(_id, _name, _pname, _reg, _bit) \ 223 { \ 224 .id = (_id), \ 225 .type = RK_CRU_GATE, \ 226 .base.name = (_name), \ 227 .base.flags = CLK_SET_RATE_PARENT, \ 228 .u.gate.parent = (_pname), \ 229 .u.gate.reg = (_reg), \ 230 .u.gate.mask = __BIT(_bit), \ 231 .enable = rk_cru_gate_enable, \ 232 .get_parent = rk_cru_gate_get_parent, \ 233 } 234 235 /* Mux clocks */ 236 237 struct rk_cru_mux { 238 bus_size_t reg; 239 uint32_t mask; 240 const char **parents; 241 u_int nparents; 242 u_int flags; 243 #define RK_MUX_GRF 0x01 244 }; 245 246 const char *rk_cru_mux_get_parent(struct rk_cru_softc *, struct rk_cru_clk *); 247 int rk_cru_mux_set_parent(struct rk_cru_softc *, struct rk_cru_clk *, const char *); 248 249 #define RK_MUX_FLAGS(_id, _name, _parents, _reg, _mask, _flags) \ 250 { \ 251 .id = (_id), \ 252 .type = RK_CRU_MUX, \ 253 .base.name = (_name), \ 254 .base.flags = CLK_SET_RATE_PARENT, \ 255 .u.mux.parents = (_parents), \ 256 .u.mux.nparents = __arraycount(_parents), \ 257 .u.mux.reg = (_reg), \ 258 .u.mux.mask = (_mask), \ 259 .u.mux.flags = (_flags), \ 260 .set_parent = rk_cru_mux_set_parent, \ 261 .get_parent = rk_cru_mux_get_parent, \ 262 } 263 #define RK_MUX(_id, _name, _parents, _reg, _mask) \ 264 RK_MUX_FLAGS(_id, _name, _parents, _reg, _mask, 0) 265 #define RK_MUXGRF(_id, _name, _parents, _reg, _mask) \ 266 RK_MUX_FLAGS(_id, _name, _parents, _reg, _mask, RK_MUX_GRF) 267 268 /* 269 * Rockchip clock definition 270 */ 271 272 struct rk_cru_clk { 273 struct clk base; 274 u_int id; 275 enum rk_cru_clktype type; 276 union { 277 struct rk_cru_pll pll; 278 struct rk_cru_arm arm; 279 struct rk_cru_composite composite; 280 struct rk_cru_gate gate; 281 struct rk_cru_mux mux; 282 } u; 283 284 int (*enable)(struct rk_cru_softc *, 285 struct rk_cru_clk *, int); 286 u_int (*get_rate)(struct rk_cru_softc *, 287 struct rk_cru_clk *); 288 int (*set_rate)(struct rk_cru_softc *, 289 struct rk_cru_clk *, u_int); 290 u_int (*round_rate)(struct rk_cru_softc *, 291 struct rk_cru_clk *, u_int); 292 const char * (*get_parent)(struct rk_cru_softc *, 293 struct rk_cru_clk *); 294 int (*set_parent)(struct rk_cru_softc *, 295 struct rk_cru_clk *, 296 const char *); 297 }; 298 299 /* 300 * Driver state 301 */ 302 303 struct rk_cru_softc { 304 device_t sc_dev; 305 int sc_phandle; 306 bus_space_tag_t sc_bst; 307 bus_space_handle_t sc_bsh; 308 struct syscon *sc_grf; 309 310 struct clk_domain sc_clkdom; 311 312 struct rk_cru_clk *sc_clks; 313 u_int sc_nclks; 314 315 bus_size_t sc_softrst_base; 316 }; 317 318 int rk_cru_attach(struct rk_cru_softc *); 319 struct rk_cru_clk *rk_cru_clock_find(struct rk_cru_softc *, 320 const char *); 321 void rk_cru_print(struct rk_cru_softc *); 322 323 #define CRU_READ(sc, reg) \ 324 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg)) 325 #define CRU_WRITE(sc, reg, val) \ 326 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)) 327 328 #define HAS_GRF(sc) ((sc)->sc_grf != NULL) 329 330 #endif /* _ARM_RK_CRU_H */ 331
Indexes created Sun Sep 28 16:09:52 GMT 2025