rk_cru.h revision 1.4
1 /* $NetBSD: rk_cru.h,v 1.4 2018/09/01 19:35:53 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2018 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #ifndef _ARM_RK_CRU_H 30 #define _ARM_RK_CRU_H 31 32 #include <dev/clk/clk_backend.h> 33 #include <dev/fdt/syscon.h> 34 35 struct rk_cru_softc; 36 struct rk_cru_clk; 37 38 /* 39 * Clocks 40 */ 41 42 enum rk_cru_clktype { 43 RK_CRU_UNKNOWN, 44 RK_CRU_PLL, 45 RK_CRU_ARM, 46 RK_CRU_COMPOSITE, 47 RK_CRU_GATE, 48 RK_CRU_MUX, 49 }; 50 51 /* PLL clocks */ 52 53 struct rk_cru_pll_rate { 54 u_int rate; 55 u_int refdiv; 56 u_int fbdiv; 57 u_int postdiv1; 58 u_int postdiv2; 59 u_int dsmpd; 60 u_int fracdiv; 61 }; 62 63 #define RK_PLL_RATE(_rate, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _fracdiv) \ 64 { \ 65 .rate = (_rate), \ 66 .refdiv = (_refdiv), \ 67 .fbdiv = (_fbdiv), \ 68 .postdiv1 = (_postdiv1), \ 69 .postdiv2 = (_postdiv2), \ 70 .dsmpd = (_dsmpd), \ 71 .fracdiv = (_fracdiv), \ 72 } 73 74 struct rk_cru_pll { 75 bus_size_t con_base; 76 bus_size_t mode_reg; 77 uint32_t mode_mask; 78 uint32_t lock_mask; 79 const struct rk_cru_pll_rate *rates; 80 u_int nrates; 81 const char **parents; 82 u_int nparents; 83 }; 84 85 u_int rk_cru_pll_get_rate(struct rk_cru_softc *, struct rk_cru_clk *); 86 int rk_cru_pll_set_rate(struct rk_cru_softc *, struct rk_cru_clk *, u_int); 87 const char *rk_cru_pll_get_parent(struct rk_cru_softc *, struct rk_cru_clk *); 88 89 #define RK_PLL(_id, _name, _parents, _con_base, _mode_reg, _mode_mask, _lock_mask, _rates) \ 90 { \ 91 .id = (_id), \ 92 .type = RK_CRU_PLL, \ 93 .base.name = (_name), \ 94 .base.flags = 0, \ 95 .u.pll.parents = (_parents), \ 96 .u.pll.nparents = __arraycount(_parents), \ 97 .u.pll.con_base = (_con_base), \ 98 .u.pll.mode_reg = (_mode_reg), \ 99 .u.pll.mode_mask = (_mode_mask), \ 100 .u.pll.lock_mask = (_lock_mask), \ 101 .u.pll.rates = (_rates), \ 102 .u.pll.nrates = __arraycount(_rates), \ 103 .get_rate = rk_cru_pll_get_rate, \ 104 .set_rate = rk_cru_pll_set_rate, \ 105 .get_parent = rk_cru_pll_get_parent, \ 106 } 107 108 /* ARM clocks */ 109 110 struct rk_cru_arm_rate { 111 u_int rate; 112 u_int div; 113 }; 114 115 #define RK_ARM_RATE(_rate, _div) \ 116 { \ 117 .rate = (_rate), \ 118 .div = (_div), \ 119 } 120 121 struct rk_cru_cpu_rate { 122 u_int rate; 123 u_int reg1, reg1_mask, reg1_val; 124 u_int reg2, reg2_mask, reg2_val; 125 }; 126 127 #define RK_CPU_RATE(_rate, _reg1, _reg1_mask, _reg1_val, _reg2, _reg2_mask, _reg2_val) \ 128 { \ 129 .rate = (_rate), \ 130 .reg1 = (_reg1), .reg1_mask = (_reg1_mask), .reg1_val = (_reg1_val), \ 131 .reg2 = (_reg2), .reg2_mask = (_reg2_mask), .reg2_val = (_reg2_val), \ 132 } 133 134 struct rk_cru_arm { 135 bus_size_t reg; 136 uint32_t mux_mask; 137 u_int mux_main; 138 u_int mux_alt; 139 uint32_t div_mask; 140 const char **parents; 141 u_int nparents; 142 const struct rk_cru_arm_rate *rates; 143 const struct rk_cru_cpu_rate *cpurates; 144 u_int nrates; 145 }; 146 147 u_int rk_cru_arm_get_rate(struct rk_cru_softc *, struct rk_cru_clk *); 148 int rk_cru_arm_set_rate(struct rk_cru_softc *, struct rk_cru_clk *, u_int); 149 int rk_cru_arm_set_rate(struct rk_cru_softc *, struct rk_cru_clk *, u_int); 150 const char *rk_cru_arm_get_parent(struct rk_cru_softc *, struct rk_cru_clk *); 151 int rk_cru_arm_set_parent(struct rk_cru_softc *, struct rk_cru_clk *, const char *); 152 153 #define RK_ARM(_id, _name, _parents, _reg, _mux_mask, _mux_main, _mux_alt, _div_mask, _rates) \ 154 { \ 155 .id = (_id), \ 156 .type = RK_CRU_ARM, \ 157 .base.name = (_name), \ 158 .base.flags = 0, \ 159 .u.arm.parents = (_parents), \ 160 .u.arm.nparents = __arraycount(_parents), \ 161 .u.arm.reg = (_reg), \ 162 .u.arm.mux_mask = (_mux_mask), \ 163 .u.arm.mux_main = (_mux_main), \ 164 .u.arm.mux_alt = (_mux_alt), \ 165 .u.arm.div_mask = (_div_mask), \ 166 .u.arm.rates = (_rates), \ 167 .u.arm.nrates = __arraycount(_rates), \ 168 .get_rate = rk_cru_arm_get_rate, \ 169 .set_rate = rk_cru_arm_set_rate, \ 170 .get_parent = rk_cru_arm_get_parent, \ 171 .set_parent = rk_cru_arm_set_parent, \ 172 } 173 174 #define RK_CPU(_id, _name, _parents, _reg, _mux_mask, _mux_main, _mux_alt, _div_mask, _cpurates) \ 175 { \ 176 .id = (_id), \ 177 .type = RK_CRU_ARM, \ 178 .base.name = (_name), \ 179 .base.flags = 0, \ 180 .u.arm.parents = (_parents), \ 181 .u.arm.nparents = __arraycount(_parents), \ 182 .u.arm.reg = (_reg), \ 183 .u.arm.mux_mask = (_mux_mask), \ 184 .u.arm.mux_main = (_mux_main), \ 185 .u.arm.mux_alt = (_mux_alt), \ 186 .u.arm.div_mask = (_div_mask), \ 187 .u.arm.cpurates = (_cpurates), \ 188 .u.arm.nrates = __arraycount(_cpurates), \ 189 .get_rate = rk_cru_arm_get_rate, \ 190 .set_rate = rk_cru_arm_set_rate, \ 191 .get_parent = rk_cru_arm_get_parent, \ 192 .set_parent = rk_cru_arm_set_parent, \ 193 } 194 195 /* Composite clocks */ 196 197 struct rk_cru_composite { 198 bus_size_t muxdiv_reg; 199 uint32_t mux_mask; 200 uint32_t div_mask; 201 bus_size_t gate_reg; 202 uint32_t gate_mask; 203 const char **parents; 204 u_int nparents; 205 u_int flags; 206 #define RK_COMPOSITE_ROUND_DOWN 0x01 207 }; 208 209 int rk_cru_composite_enable(struct rk_cru_softc *, struct rk_cru_clk *, int); 210 u_int rk_cru_composite_get_rate(struct rk_cru_softc *, struct rk_cru_clk *); 211 int rk_cru_composite_set_rate(struct rk_cru_softc *, struct rk_cru_clk *, u_int); 212 const char *rk_cru_composite_get_parent(struct rk_cru_softc *, struct rk_cru_clk *); 213 int rk_cru_composite_set_parent(struct rk_cru_softc *, struct rk_cru_clk *, const char *); 214 215 #define RK_COMPOSITE(_id, _name, _parents, _muxdiv_reg, _mux_mask, _div_mask, _gate_reg, _gate_mask, _flags) \ 216 { \ 217 .id = (_id), \ 218 .type = RK_CRU_COMPOSITE, \ 219 .base.name = (_name), \ 220 .base.flags = 0, \ 221 .u.composite.parents = (_parents), \ 222 .u.composite.nparents = __arraycount(_parents), \ 223 .u.composite.muxdiv_reg = (_muxdiv_reg), \ 224 .u.composite.mux_mask = (_mux_mask), \ 225 .u.composite.div_mask = (_div_mask), \ 226 .u.composite.gate_reg = (_gate_reg), \ 227 .u.composite.gate_mask = (_gate_mask), \ 228 .u.composite.flags = (_flags), \ 229 .enable = rk_cru_composite_enable, \ 230 .get_rate = rk_cru_composite_get_rate, \ 231 .set_rate = rk_cru_composite_set_rate, \ 232 .get_parent = rk_cru_composite_get_parent, \ 233 .set_parent = rk_cru_composite_set_parent, \ 234 } 235 236 #define RK_COMPOSITE_NOMUX(_id, _name, _parent, _div_reg, _div_mask, _gate_reg, _gate_mask, _flags) \ 237 RK_COMPOSITE(_id, _name, (const char *[]){ _parent }, _div_reg, 0, _div_mask, _gate_reg, _gate_mask, _flags) 238 239 #define RK_COMPOSITE_NOGATE(_id, _name, _parents, _muxdiv_reg, _mux_mask, _div_mask, _flags) \ 240 RK_COMPOSITE(_id, _name, _parents, _muxdiv_reg, _mux_mask, _div_mask, 0, 0, _flags) 241 242 #define RK_DIV(_id, _name, _parent, _div_reg, _div_mask, _flags) \ 243 RK_COMPOSITE(_id, _name, (const char *[]){ _parent }, _div_reg, 0, _div_mask, 0, 0, _flags) 244 245 /* Gate clocks */ 246 247 struct rk_cru_gate { 248 bus_size_t reg; 249 uint32_t mask; 250 const char *parent; 251 }; 252 253 int rk_cru_gate_enable(struct rk_cru_softc *, 254 struct rk_cru_clk *, int); 255 const char *rk_cru_gate_get_parent(struct rk_cru_softc *, 256 struct rk_cru_clk *); 257 258 #define RK_GATE(_id, _name, _pname, _reg, _bit) \ 259 { \ 260 .id = (_id), \ 261 .type = RK_CRU_GATE, \ 262 .base.name = (_name), \ 263 .base.flags = CLK_SET_RATE_PARENT, \ 264 .u.gate.parent = (_pname), \ 265 .u.gate.reg = (_reg), \ 266 .u.gate.mask = __BIT(_bit), \ 267 .enable = rk_cru_gate_enable, \ 268 .get_parent = rk_cru_gate_get_parent, \ 269 } 270 271 /* Mux clocks */ 272 273 struct rk_cru_mux { 274 bus_size_t reg; 275 uint32_t mask; 276 const char **parents; 277 u_int nparents; 278 u_int flags; 279 #define RK_MUX_GRF 0x01 280 }; 281 282 const char *rk_cru_mux_get_parent(struct rk_cru_softc *, struct rk_cru_clk *); 283 int rk_cru_mux_set_parent(struct rk_cru_softc *, struct rk_cru_clk *, const char *); 284 285 #define RK_MUX_FLAGS(_id, _name, _parents, _reg, _mask, _flags) \ 286 { \ 287 .id = (_id), \ 288 .type = RK_CRU_MUX, \ 289 .base.name = (_name), \ 290 .base.flags = CLK_SET_RATE_PARENT, \ 291 .u.mux.parents = (_parents), \ 292 .u.mux.nparents = __arraycount(_parents), \ 293 .u.mux.reg = (_reg), \ 294 .u.mux.mask = (_mask), \ 295 .u.mux.flags = (_flags), \ 296 .set_parent = rk_cru_mux_set_parent, \ 297 .get_parent = rk_cru_mux_get_parent, \ 298 } 299 #define RK_MUX(_id, _name, _parents, _reg, _mask) \ 300 RK_MUX_FLAGS(_id, _name, _parents, _reg, _mask, 0) 301 #define RK_MUXGRF(_id, _name, _parents, _reg, _mask) \ 302 RK_MUX_FLAGS(_id, _name, _parents, _reg, _mask, RK_MUX_GRF) 303 304 /* 305 * Rockchip clock definition 306 */ 307 308 struct rk_cru_clk { 309 struct clk base; 310 u_int id; 311 enum rk_cru_clktype type; 312 union { 313 struct rk_cru_pll pll; 314 struct rk_cru_arm arm; 315 struct rk_cru_composite composite; 316 struct rk_cru_gate gate; 317 struct rk_cru_mux mux; 318 } u; 319 320 int (*enable)(struct rk_cru_softc *, 321 struct rk_cru_clk *, int); 322 u_int (*get_rate)(struct rk_cru_softc *, 323 struct rk_cru_clk *); 324 int (*set_rate)(struct rk_cru_softc *, 325 struct rk_cru_clk *, u_int); 326 u_int (*round_rate)(struct rk_cru_softc *, 327 struct rk_cru_clk *, u_int); 328 const char * (*get_parent)(struct rk_cru_softc *, 329 struct rk_cru_clk *); 330 int (*set_parent)(struct rk_cru_softc *, 331 struct rk_cru_clk *, 332 const char *); 333 }; 334 335 /* 336 * Driver state 337 */ 338 339 struct rk_cru_softc { 340 device_t sc_dev; 341 int sc_phandle; 342 bus_space_tag_t sc_bst; 343 bus_space_handle_t sc_bsh; 344 struct syscon *sc_grf; 345 346 struct clk_domain sc_clkdom; 347 348 struct rk_cru_clk *sc_clks; 349 u_int sc_nclks; 350 351 bus_size_t sc_softrst_base; 352 }; 353 354 int rk_cru_attach(struct rk_cru_softc *); 355 struct rk_cru_clk *rk_cru_clock_find(struct rk_cru_softc *, 356 const char *); 357 void rk_cru_print(struct rk_cru_softc *); 358 359 #define CRU_READ(sc, reg) \ 360 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg)) 361 #define CRU_WRITE(sc, reg, val) \ 362 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)) 363 364 #define HAS_GRF(sc) ((sc)->sc_grf != NULL) 365 366 #endif /* _ARM_RK_CRU_H */ 367
Indexes created Sat Sep 27 22:09:54 GMT 2025