rk_emmcphy.c revision 1.2
1 /* $NetBSD: rk_emmcphy.c,v 1.2 2019/03/10 19:47:03 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2019 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: rk_emmcphy.c,v 1.2 2019/03/10 19:47:03 jmcneill Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/bus.h> 34 #include <sys/device.h> 35 #include <sys/intr.h> 36 #include <sys/systm.h> 37 #include <sys/mutex.h> 38 #include <sys/kmem.h> 39 40 #include <dev/fdt/fdtvar.h> 41 #include <dev/fdt/syscon.h> 42 43 #define GRF_EMMCPHY_CON0 0x00 44 #define PHYCTRL_FRQSEL __BITS(13,12) 45 #define PHYCTRL_FRQSEL_200M 0 46 #define PHYCTRL_FRQSEL_50M 1 47 #define PHYCTRL_FRQSEL_100M 2 48 #define PHYCTRL_FRQSEL_150M 3 49 #define PHYCTRL_OTAPDLYENA __BIT(11) 50 #define PHYCTRL_OTAPDLYSEL __BITS(10,7) 51 #define PHYCTRL_ITAPCHGWIN __BIT(6) 52 #define PHYCTRL_ITAPDLYSEL __BITS(5,1) 53 #define PHYCTRL_ITAPDLYENA __BIT(0) 54 #define GRF_EMMCPHY_CON1 0x04 55 #define PHYCTRL_CLKBUFSEL __BITS(8,6) 56 #define PHYCTRL_SELDLYTXCLK __BIT(5) 57 #define PHYCTRL_SELDLYRXCLK __BIT(4) 58 #define PHYCTRL_STRBSEL __BITS(3,0) 59 #define GRF_EMMCPHY_CON2 0x08 60 #define PHYCTRL_REN_STRB __BIT(9) 61 #define PHYCTRL_REN_CMD __BIT(8) 62 #define PHYCTRL_REN_DAT __BITS(7,0) 63 #define GRF_EMMCPHY_CON3 0x0c 64 #define PHYCTRL_PU_STRB __BIT(9) 65 #define PHYCTRL_PU_CMD __BIT(8) 66 #define PHYCTRL_PU_DAT __BITS(7,0) 67 #define GRF_EMMCPHY_CON4 0x10 68 #define PHYCTRL_OD_RELEASE_CMD __BIT(9) 69 #define PHYCTRL_OD_RELEASE_STRB __BIT(8) 70 #define PHYCTRL_OD_RELEASE_DAT __BITS(7,0) 71 #define GRF_EMMCPHY_CON5 0x14 72 #define PHYCTRL_ODEN_STRB __BIT(9) 73 #define PHYCTRL_ODEN_CMD __BIT(8) 74 #define PHYCTRL_ODEN_DAT __BITS(7,0) 75 #define GRF_EMMCPHY_CON6 0x18 76 #define PHYCTRL_DLL_TRM_ICP __BITS(12,9) 77 #define PHYCTRL_EN_RTRIM __BIT(8) 78 #define PHYCTRL_RETRIM __BIT(7) 79 #define PHYCTRL_DR_TY __BITS(6,4) 80 #define PHYCTRL_RETENB __BIT(3) 81 #define PHYCTRL_RETEN __BIT(2) 82 #define PHYCTRL_ENDLL __BIT(1) 83 #define PHYCTRL_PDB __BIT(0) 84 #define GRF_EMMCPHY_STATUS 0x20 85 #define PHYCTRL_CALDONE __BIT(6) 86 #define PHYCTRL_DLLRDY __BIT(5) 87 #define PHYCTRL_RTRIM __BITS(4,1) 88 #define PHYCTRL_EXR_NINST __BIT(0) 89 90 static const char * const compatible[] = { 91 "rockchip,rk3399-emmc-phy", 92 NULL 93 }; 94 95 struct rk_emmcphy_softc { 96 device_t sc_dev; 97 struct syscon *sc_syscon; 98 bus_addr_t sc_regbase; 99 int sc_phandle; 100 struct clk *sc_clk; 101 }; 102 103 #define RD4(sc, reg) \ 104 syscon_read_4((sc)->sc_syscon, (sc)->sc_regbase + (reg)) 105 #define WR4(sc, reg, val) \ 106 syscon_write_4((sc)->sc_syscon, (sc)->sc_regbase + (reg), (val)) 107 108 static int rk_emmcphy_match(device_t, cfdata_t, void *); 109 static void rk_emmcphy_attach(device_t, device_t, void *); 110 111 CFATTACH_DECL_NEW(rkemmcphy, sizeof(struct rk_emmcphy_softc), 112 rk_emmcphy_match, rk_emmcphy_attach, NULL, NULL); 113 114 static void * 115 rk_emmcphy_acquire(device_t dev, const void *data, size_t len) 116 { 117 struct rk_emmcphy_softc * const sc = device_private(dev); 118 119 if (len != 0) 120 return NULL; 121 122 if (sc->sc_clk == NULL) 123 sc->sc_clk = fdtbus_clock_get(sc->sc_phandle, "emmcclk"); 124 125 return sc; 126 } 127 128 static void 129 rk_emmcphy_release(device_t dev, void *priv) 130 { 131 } 132 133 static int 134 rk_emmcphy_enable(device_t dev, void *priv, bool enable) 135 { 136 struct rk_emmcphy_softc * const sc = device_private(dev); 137 uint32_t mask, val; 138 u_int rate, frqsel; 139 140 syscon_lock(sc->sc_syscon); 141 142 /* Power down PHY and disable DLL before making changes */ 143 mask = PHYCTRL_ENDLL | PHYCTRL_PDB; 144 val = 0; 145 WR4(sc, GRF_EMMCPHY_CON6, (mask << 16) | val); 146 147 if (enable == false) { 148 syscon_unlock(sc->sc_syscon); 149 return 0; 150 } 151 152 rate = sc->sc_clk ? clk_get_rate(sc->sc_clk) : 0; 153 154 if (rate != 0) { 155 if (rate < 75000000) 156 frqsel = PHYCTRL_FRQSEL_50M; 157 else if (rate < 125000000) 158 frqsel = PHYCTRL_FRQSEL_100M; 159 else if (rate < 175000000) 160 frqsel = PHYCTRL_FRQSEL_150M; 161 else 162 frqsel = PHYCTRL_FRQSEL_200M; 163 } else { 164 frqsel = PHYCTRL_FRQSEL_200M; 165 } 166 167 delay(3); 168 169 /* Power up PHY */ 170 mask = PHYCTRL_PDB; 171 val = PHYCTRL_PDB; 172 WR4(sc, GRF_EMMCPHY_CON6, (mask << 16) | val); 173 174 /* Wait for calibration */ 175 delay(10); 176 val = RD4(sc, GRF_EMMCPHY_STATUS); 177 if ((val & PHYCTRL_CALDONE) == 0) { 178 device_printf(dev, "PHY calibration did not complete\n"); 179 syscon_unlock(sc->sc_syscon); 180 return EIO; 181 } 182 183 /* Set DLL frequency */ 184 mask = PHYCTRL_FRQSEL; 185 val = __SHIFTIN(frqsel, PHYCTRL_FRQSEL); 186 WR4(sc, GRF_EMMCPHY_CON0, (mask << 16) | val); 187 188 /* Enable DLL */ 189 mask = PHYCTRL_ENDLL; 190 val = PHYCTRL_ENDLL; 191 WR4(sc, GRF_EMMCPHY_CON6, (mask << 16) | val); 192 193 if (rate != 0) { 194 /* Wait for DLL ready */ 195 delay(50000); 196 val = RD4(sc, GRF_EMMCPHY_STATUS); 197 if ((val & PHYCTRL_DLLRDY) == 0) { 198 device_printf(dev, "DLL loop failed to lock\n"); 199 syscon_unlock(sc->sc_syscon); 200 return EIO; 201 } 202 } 203 204 syscon_unlock(sc->sc_syscon); 205 206 return 0; 207 } 208 209 static const struct fdtbus_phy_controller_func rk_emmcphy_funcs = { 210 .acquire = rk_emmcphy_acquire, 211 .release = rk_emmcphy_release, 212 .enable = rk_emmcphy_enable, 213 }; 214 215 static int 216 rk_emmcphy_match(device_t parent, cfdata_t cf, void *aux) 217 { 218 struct fdt_attach_args * const faa = aux; 219 220 return of_match_compatible(faa->faa_phandle, compatible); 221 } 222 223 static void 224 rk_emmcphy_attach(device_t parent, device_t self, void *aux) 225 { 226 struct rk_emmcphy_softc * const sc = device_private(self); 227 struct fdt_attach_args * const faa = aux; 228 const int phandle = faa->faa_phandle; 229 bus_addr_t addr; 230 bus_size_t size; 231 232 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 233 aprint_error(": couldn't get registers\n"); 234 return; 235 } 236 237 sc->sc_dev = self; 238 sc->sc_phandle = phandle; 239 sc->sc_syscon = fdtbus_syscon_lookup(OF_parent(phandle)); 240 if (sc->sc_syscon == NULL) { 241 aprint_error(": couldn't get syscon\n"); 242 return; 243 } 244 sc->sc_regbase = addr; 245 246 aprint_naive("\n"); 247 aprint_normal(": eMMC PHY\n"); 248 249 fdtbus_register_phy_controller(self, phandle, &rk_emmcphy_funcs); 250 } 251
Indexes created Thu Oct 02 07:10:07 GMT 2025