rk_gmac.c revision 1.3.2.3
1 1.3.2.3 pgoyette /* $NetBSD: rk_gmac.c,v 1.3.2.3 2018/07/28 04:37:29 pgoyette Exp $ */ 2 1.3.2.2 pgoyette 3 1.3.2.2 pgoyette /*- 4 1.3.2.2 pgoyette * Copyright (c) 2018 Jared McNeill <jmcneill (at) invisible.ca> 5 1.3.2.2 pgoyette * All rights reserved. 6 1.3.2.2 pgoyette * 7 1.3.2.2 pgoyette * Redistribution and use in source and binary forms, with or without 8 1.3.2.2 pgoyette * modification, are permitted provided that the following conditions 9 1.3.2.2 pgoyette * are met: 10 1.3.2.2 pgoyette * 1. Redistributions of source code must retain the above copyright 11 1.3.2.2 pgoyette * notice, this list of conditions and the following disclaimer. 12 1.3.2.2 pgoyette * 2. Redistributions in binary form must reproduce the above copyright 13 1.3.2.2 pgoyette * notice, this list of conditions and the following disclaimer in the 14 1.3.2.2 pgoyette * documentation and/or other materials provided with the distribution. 15 1.3.2.2 pgoyette * 16 1.3.2.2 pgoyette * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 17 1.3.2.2 pgoyette * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 1.3.2.2 pgoyette * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 1.3.2.2 pgoyette * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 20 1.3.2.2 pgoyette * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 1.3.2.2 pgoyette * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 1.3.2.2 pgoyette * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 1.3.2.2 pgoyette * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 1.3.2.2 pgoyette * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 1.3.2.2 pgoyette * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 1.3.2.2 pgoyette * POSSIBILITY OF SUCH DAMAGE. 27 1.3.2.2 pgoyette */ 28 1.3.2.2 pgoyette 29 1.3.2.2 pgoyette #include <sys/cdefs.h> 30 1.3.2.2 pgoyette 31 1.3.2.3 pgoyette __KERNEL_RCSID(0, "$NetBSD: rk_gmac.c,v 1.3.2.3 2018/07/28 04:37:29 pgoyette Exp $"); 32 1.3.2.2 pgoyette 33 1.3.2.2 pgoyette #include <sys/param.h> 34 1.3.2.2 pgoyette #include <sys/bus.h> 35 1.3.2.2 pgoyette #include <sys/device.h> 36 1.3.2.2 pgoyette #include <sys/intr.h> 37 1.3.2.2 pgoyette #include <sys/systm.h> 38 1.3.2.2 pgoyette #include <sys/gpio.h> 39 1.3.2.2 pgoyette 40 1.3.2.2 pgoyette #include <net/if.h> 41 1.3.2.2 pgoyette #include <net/if_ether.h> 42 1.3.2.2 pgoyette #include <net/if_media.h> 43 1.3.2.2 pgoyette 44 1.3.2.2 pgoyette #include <dev/mii/miivar.h> 45 1.3.2.2 pgoyette 46 1.3.2.2 pgoyette #include <dev/ic/dwc_gmac_var.h> 47 1.3.2.2 pgoyette #include <dev/ic/dwc_gmac_reg.h> 48 1.3.2.2 pgoyette 49 1.3.2.2 pgoyette #include <dev/fdt/fdtvar.h> 50 1.3.2.3 pgoyette #include <dev/fdt/syscon.h> 51 1.3.2.2 pgoyette 52 1.3.2.2 pgoyette #define RK3328_GRF_MAC_CON0 0x0900 53 1.3.2.2 pgoyette #define RK3328_GRF_MAC_CON0_RXDLY __BITS(13,7) 54 1.3.2.2 pgoyette #define RK3328_GRF_MAC_CON0_TXDLY __BITS(6,0) 55 1.3.2.2 pgoyette 56 1.3.2.2 pgoyette #define RK3328_GRF_MAC_CON1 0x0904 57 1.3.2.2 pgoyette #define RK3328_GRF_MAC_CON1_CLKSEL __BITS(12,11) 58 1.3.2.2 pgoyette #define RK3328_GRF_MAC_CON1_CLKSEL_125M 0 59 1.3.2.2 pgoyette #define RK3328_GRF_MAC_CON1_CLKSEL_2_5M 2 60 1.3.2.2 pgoyette #define RK3328_GRF_MAC_CON1_CLKSEL_25M 3 61 1.3.2.2 pgoyette #define RK3328_GRF_MAC_CON1_MODE __BIT(9) 62 1.3.2.2 pgoyette #define RK3328_GRF_MAC_CON1_SEL __BITS(6,4) 63 1.3.2.2 pgoyette #define RK3328_GRF_MAC_CON1_SEL_RGMII 1 64 1.3.2.2 pgoyette #define RK3328_GRF_MAC_CON1_RXDLY_EN __BIT(1) 65 1.3.2.2 pgoyette #define RK3328_GRF_MAC_CON1_TXDLY_EN __BIT(0) 66 1.3.2.2 pgoyette 67 1.3.2.2 pgoyette #define RK_GMAC_TXDLY_DEFAULT 0x30 68 1.3.2.2 pgoyette #define RK_GMAC_RXDLY_DEFAULT 0x10 69 1.3.2.2 pgoyette 70 1.3.2.2 pgoyette static const char * compatible[] = { 71 1.3.2.2 pgoyette "rockchip,rk3328-gmac", 72 1.3.2.2 pgoyette NULL 73 1.3.2.2 pgoyette }; 74 1.3.2.2 pgoyette 75 1.3.2.2 pgoyette struct rk_gmac_softc { 76 1.3.2.2 pgoyette struct dwc_gmac_softc sc_base; 77 1.3.2.3 pgoyette struct syscon *sc_syscon; 78 1.3.2.2 pgoyette }; 79 1.3.2.2 pgoyette 80 1.3.2.2 pgoyette static int 81 1.3.2.2 pgoyette rk_gmac_reset(const int phandle) 82 1.3.2.2 pgoyette { 83 1.3.2.2 pgoyette struct fdtbus_gpio_pin *pin_reset; 84 1.3.2.2 pgoyette const u_int *reset_delay_us; 85 1.3.2.2 pgoyette bool reset_active_low; 86 1.3.2.2 pgoyette int len; 87 1.3.2.2 pgoyette 88 1.3.2.2 pgoyette if (!of_hasprop(phandle, "snps,reset-gpio")) 89 1.3.2.2 pgoyette return 0; 90 1.3.2.2 pgoyette 91 1.3.2.2 pgoyette pin_reset = fdtbus_gpio_acquire(phandle, "snps,reset-gpio", GPIO_PIN_OUTPUT); 92 1.3.2.2 pgoyette if (pin_reset == NULL) 93 1.3.2.2 pgoyette return ENOENT; 94 1.3.2.2 pgoyette 95 1.3.2.2 pgoyette reset_delay_us = fdtbus_get_prop(phandle, "snps,reset-delays-us", &len); 96 1.3.2.2 pgoyette if (reset_delay_us == NULL || len != 12) 97 1.3.2.2 pgoyette return ENXIO; 98 1.3.2.2 pgoyette 99 1.3.2.2 pgoyette reset_active_low = of_hasprop(phandle, "snps,reset-active-low"); 100 1.3.2.2 pgoyette 101 1.3.2.2 pgoyette fdtbus_gpio_write_raw(pin_reset, reset_active_low ? 1 : 0); 102 1.3.2.2 pgoyette delay(be32toh(reset_delay_us[0])); 103 1.3.2.2 pgoyette fdtbus_gpio_write_raw(pin_reset, reset_active_low ? 0 : 1); 104 1.3.2.2 pgoyette delay(be32toh(reset_delay_us[1])); 105 1.3.2.2 pgoyette fdtbus_gpio_write_raw(pin_reset, reset_active_low ? 1 : 0); 106 1.3.2.2 pgoyette delay(be32toh(reset_delay_us[2])); 107 1.3.2.2 pgoyette 108 1.3.2.2 pgoyette return 0; 109 1.3.2.2 pgoyette } 110 1.3.2.2 pgoyette 111 1.3.2.2 pgoyette static int 112 1.3.2.2 pgoyette rk_gmac_intr(void *arg) 113 1.3.2.2 pgoyette { 114 1.3.2.2 pgoyette return dwc_gmac_intr(arg); 115 1.3.2.2 pgoyette } 116 1.3.2.2 pgoyette 117 1.3.2.2 pgoyette static void 118 1.3.2.2 pgoyette rk3328_gmac_set_mode_rgmii(struct dwc_gmac_softc *sc, u_int tx_delay, u_int rx_delay) 119 1.3.2.2 pgoyette { 120 1.3.2.2 pgoyette struct rk_gmac_softc * const rk_sc = (struct rk_gmac_softc *)sc; 121 1.3.2.2 pgoyette uint32_t write_mask, write_val; 122 1.3.2.2 pgoyette 123 1.3.2.3 pgoyette syscon_lock(rk_sc->sc_syscon); 124 1.3.2.3 pgoyette 125 1.3.2.2 pgoyette write_mask = (RK3328_GRF_MAC_CON1_MODE | RK3328_GRF_MAC_CON1_SEL) << 16; 126 1.3.2.2 pgoyette write_val = __SHIFTIN(RK3328_GRF_MAC_CON1_SEL_RGMII, RK3328_GRF_MAC_CON1_SEL); 127 1.3.2.3 pgoyette syscon_write_4(rk_sc->sc_syscon, RK3328_GRF_MAC_CON1, write_mask | write_val); 128 1.3.2.2 pgoyette 129 1.3.2.2 pgoyette #if notyet 130 1.3.2.2 pgoyette write_mask = (RK3328_GRF_MAC_CON0_TXDLY | RK3328_GRF_MAC_CON0_RXDLY) << 16; 131 1.3.2.2 pgoyette write_val = __SHIFTIN(tx_delay, RK3328_GRF_MAC_CON0_TXDLY) | 132 1.3.2.2 pgoyette __SHIFTIN(rx_delay, RK3328_GRF_MAC_CON0_RXDLY); 133 1.3.2.3 pgoyette syscon_write_4(rk_sc->sc_syscon, RK3328_GRF_MAC_CON0, write_mask | write_val); 134 1.3.2.2 pgoyette 135 1.3.2.2 pgoyette write_mask = (RK3328_GRF_MAC_CON1_RXDLY_EN | RK3328_GRF_MAC_CON1_TXDLY_EN) << 16; 136 1.3.2.2 pgoyette write_val = RK3328_GRF_MAC_CON1_RXDLY_EN | RK3328_GRF_MAC_CON1_TXDLY_EN; 137 1.3.2.3 pgoyette syscon_write_4(rk_sc->sc_syscon, RK3328_GRF_MAC_CON1, write_mask | write_val); 138 1.3.2.2 pgoyette #endif 139 1.3.2.3 pgoyette 140 1.3.2.3 pgoyette syscon_unlock(rk_sc->sc_syscon); 141 1.3.2.2 pgoyette } 142 1.3.2.2 pgoyette 143 1.3.2.2 pgoyette static void 144 1.3.2.2 pgoyette rk3328_gmac_set_speed_rgmii(struct dwc_gmac_softc *sc, int speed) 145 1.3.2.2 pgoyette { 146 1.3.2.2 pgoyette struct rk_gmac_softc * const rk_sc = (struct rk_gmac_softc *)sc; 147 1.3.2.3 pgoyette #if 0 148 1.3.2.2 pgoyette u_int clksel; 149 1.3.2.2 pgoyette 150 1.3.2.2 pgoyette switch (speed) { 151 1.3.2.2 pgoyette case IFM_10_T: 152 1.3.2.2 pgoyette clksel = RK3328_GRF_MAC_CON1_CLKSEL_2_5M; 153 1.3.2.2 pgoyette break; 154 1.3.2.2 pgoyette case IFM_100_TX: 155 1.3.2.2 pgoyette clksel = RK3328_GRF_MAC_CON1_CLKSEL_25M; 156 1.3.2.2 pgoyette break; 157 1.3.2.2 pgoyette default: 158 1.3.2.2 pgoyette clksel = RK3328_GRF_MAC_CON1_CLKSEL_125M; 159 1.3.2.2 pgoyette break; 160 1.3.2.2 pgoyette } 161 1.3.2.3 pgoyette #endif 162 1.3.2.2 pgoyette 163 1.3.2.3 pgoyette syscon_lock(rk_sc->sc_syscon); 164 1.3.2.3 pgoyette syscon_write_4(rk_sc->sc_syscon, RK3328_GRF_MAC_CON1, 165 1.3.2.2 pgoyette (RK3328_GRF_MAC_CON1_CLKSEL << 16) | 166 1.3.2.2 pgoyette __SHIFTIN(RK3328_GRF_MAC_CON1_CLKSEL_125M, RK3328_GRF_MAC_CON1_CLKSEL)); 167 1.3.2.3 pgoyette syscon_unlock(rk_sc->sc_syscon); 168 1.3.2.2 pgoyette } 169 1.3.2.2 pgoyette 170 1.3.2.2 pgoyette static int 171 1.3.2.2 pgoyette rk_gmac_setup_clocks(int phandle) 172 1.3.2.2 pgoyette { 173 1.3.2.2 pgoyette static const char * const clknames[] = { 174 1.3.2.2 pgoyette #if 0 175 1.3.2.2 pgoyette "stmmaceth", 176 1.3.2.2 pgoyette "mac_clk_rx", 177 1.3.2.2 pgoyette "mac_clk_tx", 178 1.3.2.2 pgoyette "clk_mac_ref", 179 1.3.2.2 pgoyette "clk_mac_refout", 180 1.3.2.2 pgoyette "aclk_mac", 181 1.3.2.2 pgoyette "pclk_mac" 182 1.3.2.2 pgoyette #else 183 1.3.2.2 pgoyette "stmmaceth", 184 1.3.2.2 pgoyette "aclk_mac", 185 1.3.2.2 pgoyette "pclk_mac", 186 1.3.2.2 pgoyette "mac_clk_tx", 187 1.3.2.2 pgoyette "mac_clk_rx" 188 1.3.2.2 pgoyette #endif 189 1.3.2.2 pgoyette }; 190 1.3.2.2 pgoyette static const char * const rstnames[] = { 191 1.3.2.2 pgoyette "stmmaceth" 192 1.3.2.2 pgoyette }; 193 1.3.2.2 pgoyette struct fdtbus_reset *rst; 194 1.3.2.2 pgoyette struct clk *clk; 195 1.3.2.2 pgoyette int error, n; 196 1.3.2.2 pgoyette 197 1.3.2.2 pgoyette fdtbus_clock_assign(phandle); 198 1.3.2.2 pgoyette 199 1.3.2.2 pgoyette for (n = 0; n < __arraycount(clknames); n++) { 200 1.3.2.2 pgoyette clk = fdtbus_clock_get(phandle, clknames[n]); 201 1.3.2.2 pgoyette if (clk == NULL) { 202 1.3.2.2 pgoyette aprint_error(": couldn't get %s clock\n", clknames[n]); 203 1.3.2.2 pgoyette return ENXIO; 204 1.3.2.2 pgoyette } 205 1.3.2.2 pgoyette error = clk_enable(clk); 206 1.3.2.2 pgoyette if (error != 0) { 207 1.3.2.2 pgoyette aprint_error(": couldn't enable %s clock: %d\n", 208 1.3.2.2 pgoyette clknames[n], error); 209 1.3.2.2 pgoyette return error; 210 1.3.2.2 pgoyette } 211 1.3.2.2 pgoyette } 212 1.3.2.2 pgoyette 213 1.3.2.2 pgoyette for (n = 0; n < __arraycount(rstnames); n++) { 214 1.3.2.2 pgoyette rst = fdtbus_reset_get(phandle, rstnames[n]); 215 1.3.2.2 pgoyette if (rst == NULL) { 216 1.3.2.2 pgoyette aprint_error(": couldn't get %s reset\n", rstnames[n]); 217 1.3.2.2 pgoyette return ENXIO; 218 1.3.2.2 pgoyette } 219 1.3.2.2 pgoyette error = fdtbus_reset_deassert(rst); 220 1.3.2.2 pgoyette if (error != 0) { 221 1.3.2.2 pgoyette aprint_error(": couldn't de-assert %s reset: %d\n", 222 1.3.2.2 pgoyette rstnames[n], error); 223 1.3.2.2 pgoyette return error; 224 1.3.2.2 pgoyette } 225 1.3.2.2 pgoyette } 226 1.3.2.2 pgoyette 227 1.3.2.2 pgoyette delay(5000); 228 1.3.2.2 pgoyette 229 1.3.2.2 pgoyette return 0; 230 1.3.2.2 pgoyette } 231 1.3.2.2 pgoyette 232 1.3.2.2 pgoyette static int 233 1.3.2.2 pgoyette rk_gmac_match(device_t parent, cfdata_t cf, void *aux) 234 1.3.2.2 pgoyette { 235 1.3.2.2 pgoyette struct fdt_attach_args * const faa = aux; 236 1.3.2.2 pgoyette 237 1.3.2.2 pgoyette return of_match_compatible(faa->faa_phandle, compatible); 238 1.3.2.2 pgoyette } 239 1.3.2.2 pgoyette 240 1.3.2.2 pgoyette static void 241 1.3.2.2 pgoyette rk_gmac_attach(device_t parent, device_t self, void *aux) 242 1.3.2.2 pgoyette { 243 1.3.2.2 pgoyette struct rk_gmac_softc * const rk_sc = device_private(self); 244 1.3.2.2 pgoyette struct dwc_gmac_softc * const sc = &rk_sc->sc_base; 245 1.3.2.2 pgoyette struct fdt_attach_args * const faa = aux; 246 1.3.2.2 pgoyette const int phandle = faa->faa_phandle; 247 1.3.2.2 pgoyette const char *phy_mode; 248 1.3.2.2 pgoyette char intrstr[128]; 249 1.3.2.3 pgoyette bus_addr_t addr; 250 1.3.2.3 pgoyette bus_size_t size; 251 1.3.2.2 pgoyette u_int tx_delay, rx_delay; 252 1.3.2.2 pgoyette 253 1.3.2.2 pgoyette if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 254 1.3.2.2 pgoyette aprint_error(": couldn't get registers\n"); 255 1.3.2.2 pgoyette return; 256 1.3.2.2 pgoyette } 257 1.3.2.2 pgoyette 258 1.3.2.3 pgoyette rk_sc->sc_syscon = fdtbus_syscon_acquire(phandle, "rockchip,grf"); 259 1.3.2.3 pgoyette if (rk_sc->sc_syscon == NULL) { 260 1.3.2.3 pgoyette aprint_error(": couldn't get grf syscon\n"); 261 1.3.2.2 pgoyette return; 262 1.3.2.2 pgoyette } 263 1.3.2.2 pgoyette 264 1.3.2.2 pgoyette if (of_getprop_uint32(phandle, "tx_delay", &tx_delay) != 0) 265 1.3.2.2 pgoyette tx_delay = RK_GMAC_TXDLY_DEFAULT; 266 1.3.2.2 pgoyette 267 1.3.2.2 pgoyette if (of_getprop_uint32(phandle, "rx_delay", &rx_delay) != 0) 268 1.3.2.2 pgoyette rx_delay = RK_GMAC_RXDLY_DEFAULT; 269 1.3.2.2 pgoyette 270 1.3.2.2 pgoyette sc->sc_dev = self; 271 1.3.2.2 pgoyette sc->sc_bst = faa->faa_bst; 272 1.3.2.2 pgoyette if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) { 273 1.3.2.2 pgoyette aprint_error(": couldn't map registers\n"); 274 1.3.2.2 pgoyette return; 275 1.3.2.2 pgoyette } 276 1.3.2.2 pgoyette sc->sc_dmat = faa->faa_dmat; 277 1.3.2.2 pgoyette 278 1.3.2.2 pgoyette if (!fdtbus_intr_str(phandle, 0, intrstr, sizeof(intrstr))) { 279 1.3.2.2 pgoyette aprint_error(": failed to decode interrupt\n"); 280 1.3.2.2 pgoyette return; 281 1.3.2.2 pgoyette } 282 1.3.2.2 pgoyette 283 1.3.2.2 pgoyette if (rk_gmac_setup_clocks(phandle) != 0) 284 1.3.2.2 pgoyette return; 285 1.3.2.2 pgoyette 286 1.3.2.2 pgoyette if (rk_gmac_reset(phandle) != 0) 287 1.3.2.2 pgoyette aprint_error_dev(self, "PHY reset failed\n"); 288 1.3.2.2 pgoyette 289 1.3.2.3 pgoyette /* Rock64 seems to need more time for the reset to complete */ 290 1.3.2.3 pgoyette delay(100000); 291 1.3.2.3 pgoyette 292 1.3.2.2 pgoyette #if notyet 293 1.3.2.2 pgoyette if (of_hasprop(phandle, "snps,force_thresh_dma_mode")) 294 1.3.2.2 pgoyette sc->sc_flags |= DWC_GMAC_FORCE_THRESH_DMA_MODE; 295 1.3.2.2 pgoyette #endif 296 1.3.2.2 pgoyette 297 1.3.2.2 pgoyette phy_mode = fdtbus_get_string(phandle, "phy-mode"); 298 1.3.2.2 pgoyette if (phy_mode == NULL) { 299 1.3.2.2 pgoyette aprint_error(": missing 'phy-mode' property\n"); 300 1.3.2.2 pgoyette return; 301 1.3.2.2 pgoyette } 302 1.3.2.2 pgoyette 303 1.3.2.2 pgoyette if (strcmp(phy_mode, "rgmii") == 0) { 304 1.3.2.2 pgoyette rk3328_gmac_set_mode_rgmii(sc, tx_delay, rx_delay); 305 1.3.2.2 pgoyette 306 1.3.2.2 pgoyette sc->sc_set_speed = rk3328_gmac_set_speed_rgmii; 307 1.3.2.2 pgoyette } else { 308 1.3.2.2 pgoyette aprint_error(": unsupported phy-mode '%s'\n", phy_mode); 309 1.3.2.2 pgoyette return; 310 1.3.2.2 pgoyette } 311 1.3.2.2 pgoyette 312 1.3.2.2 pgoyette aprint_naive("\n"); 313 1.3.2.2 pgoyette aprint_normal(": GMAC\n"); 314 1.3.2.2 pgoyette 315 1.3.2.3 pgoyette if (dwc_gmac_attach(sc, GMAC_MII_CLK_150_250M_DIV102) != 0) 316 1.3.2.3 pgoyette return; 317 1.3.2.3 pgoyette 318 1.3.2.2 pgoyette if (fdtbus_intr_establish(phandle, 0, IPL_NET, 0, rk_gmac_intr, sc) == NULL) { 319 1.3.2.2 pgoyette aprint_error_dev(self, "failed to establish interrupt on %s\n", intrstr); 320 1.3.2.2 pgoyette return; 321 1.3.2.2 pgoyette } 322 1.3.2.2 pgoyette aprint_normal_dev(self, "interrupting on %s\n", intrstr); 323 1.3.2.2 pgoyette } 324 1.3.2.2 pgoyette 325 1.3.2.2 pgoyette CFATTACH_DECL_NEW(rk_gmac, sizeof(struct rk_gmac_softc), 326 1.3.2.2 pgoyette rk_gmac_match, rk_gmac_attach, NULL, NULL); 327
Indexes created Tue Oct 21 16:10:11 GMT 2025