rk_gmac.c revision 1.1
1 /* $NetBSD: rk_gmac.c,v 1.1 2018/06/16 00:19:04 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2018 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 17 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 31 __KERNEL_RCSID(0, "$NetBSD: rk_gmac.c,v 1.1 2018/06/16 00:19:04 jmcneill Exp $"); 32 33 #include <sys/param.h> 34 #include <sys/bus.h> 35 #include <sys/device.h> 36 #include <sys/intr.h> 37 #include <sys/systm.h> 38 #include <sys/gpio.h> 39 40 #include <net/if.h> 41 #include <net/if_ether.h> 42 #include <net/if_media.h> 43 44 #include <dev/mii/miivar.h> 45 46 #include <dev/ic/dwc_gmac_var.h> 47 #include <dev/ic/dwc_gmac_reg.h> 48 49 #include <dev/fdt/fdtvar.h> 50 51 #define RK3328_GRF_MAC_CON0 0x0900 52 #define RK3328_GRF_MAC_CON0_RXDLY __BITS(13,7) 53 #define RK3328_GRF_MAC_CON0_TXDLY __BITS(6,0) 54 55 #define RK3328_GRF_MAC_CON1 0x0904 56 #define RK3328_GRF_MAC_CON1_CLKSEL __BITS(12,11) 57 #define RK3328_GRF_MAC_CON1_CLKSEL_125M 0 58 #define RK3328_GRF_MAC_CON1_CLKSEL_2_5M 2 59 #define RK3328_GRF_MAC_CON1_CLKSEL_25M 3 60 #define RK3328_GRF_MAC_CON1_MODE __BIT(9) 61 #define RK3328_GRF_MAC_CON1_SEL __BITS(6,4) 62 #define RK3328_GRF_MAC_CON1_SEL_RGMII 1 63 #define RK3328_GRF_MAC_CON1_RXDLY_EN __BIT(1) 64 #define RK3328_GRF_MAC_CON1_TXDLY_EN __BIT(0) 65 66 #define RK_GMAC_TXDLY_DEFAULT 0x30 67 #define RK_GMAC_RXDLY_DEFAULT 0x10 68 69 static const char * compatible[] = { 70 "rockchip,rk3328-gmac", 71 NULL 72 }; 73 74 struct rk_gmac_softc { 75 struct dwc_gmac_softc sc_base; 76 bus_space_handle_t sc_grf_bsh; 77 }; 78 79 static int 80 rk_gmac_reset(const int phandle) 81 { 82 #if notyet 83 struct fdtbus_gpio_pin *pin_reset; 84 const u_int *reset_delay_us; 85 bool reset_active_low; 86 int len, val; 87 88 if (!of_hasprop(phandle, "snps,reset-gpio")) 89 return 0; 90 91 pin_reset = fdtbus_gpio_acquire(phandle, "snps,reset-gpio", GPIO_PIN_OUTPUT); 92 if (pin_reset == NULL) 93 return ENOENT; 94 95 reset_delay_us = fdtbus_get_prop(phandle, "snps,reset-delays-us", &len); 96 if (reset_delay_us == NULL || len != 12) 97 return ENXIO; 98 99 reset_active_low = of_hasprop(phandle, "snps,reset-active-low"); 100 101 val = reset_active_low ? 1 : 0; 102 103 fdtbus_gpio_write(pin_reset, val); 104 if (be32toh(reset_delay_us[0]) > 0) 105 delay(be32toh(reset_delay_us[0])); 106 fdtbus_gpio_write(pin_reset, !val); 107 if (be32toh(reset_delay_us[1]) > 0) 108 delay(be32toh(reset_delay_us[1])); 109 fdtbus_gpio_write(pin_reset, val); 110 if (be32toh(reset_delay_us[2]) > 0) 111 delay(be32toh(reset_delay_us[2])); 112 #endif 113 114 return 0; 115 } 116 117 static int 118 rk_gmac_intr(void *arg) 119 { 120 return dwc_gmac_intr(arg); 121 } 122 123 static void 124 rk3328_gmac_set_mode_rgmii(struct dwc_gmac_softc *sc, u_int tx_delay, u_int rx_delay) 125 { 126 struct rk_gmac_softc * const rk_sc = (struct rk_gmac_softc *)sc; 127 128 const uint32_t write_mask = 129 (RK3328_GRF_MAC_CON1_MODE | RK3328_GRF_MAC_CON1_SEL | 130 RK3328_GRF_MAC_CON1_RXDLY_EN | RK3328_GRF_MAC_CON1_TXDLY_EN) << 16; 131 const uint32_t write_val = 132 __SHIFTIN(RK3328_GRF_MAC_CON1_SEL_RGMII, RK3328_GRF_MAC_CON1_SEL) | 133 RK3328_GRF_MAC_CON1_RXDLY_EN | RK3328_GRF_MAC_CON1_TXDLY_EN; 134 135 bus_space_write_4(sc->sc_bst, rk_sc->sc_grf_bsh, RK3328_GRF_MAC_CON1, write_mask | write_val); 136 bus_space_write_4(sc->sc_bst, rk_sc->sc_grf_bsh, RK3328_GRF_MAC_CON0, 137 (RK3328_GRF_MAC_CON0_TXDLY << 16) | 138 (RK3328_GRF_MAC_CON0_RXDLY << 16) | 139 __SHIFTIN(tx_delay, RK3328_GRF_MAC_CON0_TXDLY) | 140 __SHIFTIN(rx_delay, RK3328_GRF_MAC_CON0_RXDLY)); 141 } 142 143 static void 144 rk3328_gmac_set_speed_rgmii(struct dwc_gmac_softc *sc, int speed) 145 { 146 struct rk_gmac_softc * const rk_sc = (struct rk_gmac_softc *)sc; 147 u_int clksel; 148 149 switch (speed) { 150 case IFM_10_T: 151 clksel = RK3328_GRF_MAC_CON1_CLKSEL_2_5M; 152 break; 153 case IFM_100_TX: 154 clksel = RK3328_GRF_MAC_CON1_CLKSEL_25M; 155 break; 156 default: 157 clksel = RK3328_GRF_MAC_CON1_CLKSEL_125M; 158 break; 159 } 160 161 bus_space_write_4(sc->sc_bst, rk_sc->sc_grf_bsh, RK3328_GRF_MAC_CON1, 162 (RK3328_GRF_MAC_CON1_CLKSEL << 16) | 163 __SHIFTIN(RK3328_GRF_MAC_CON1_CLKSEL_125M, RK3328_GRF_MAC_CON1_CLKSEL)); 164 } 165 166 static int 167 rk_gmac_setup_clocks(int phandle) 168 { 169 static const char * const clknames[] = { 170 #if 0 171 "stmmaceth", 172 "mac_clk_rx", 173 "mac_clk_tx", 174 "clk_mac_ref", 175 "clk_mac_refout", 176 "aclk_mac", 177 "pclk_mac" 178 #else 179 "stmmaceth", 180 "aclk_mac", 181 "pclk_mac", 182 "mac_clk_tx", 183 #endif 184 }; 185 static const char * const rstnames[] = { 186 "stmmaceth" 187 }; 188 struct fdtbus_reset *rst; 189 struct clk *clk; 190 int error, n; 191 192 fdtbus_clock_assign(phandle); 193 194 for (n = 0; n < __arraycount(clknames); n++) { 195 clk = fdtbus_clock_get(phandle, clknames[n]); 196 if (clk == NULL) { 197 aprint_error(": couldn't get %s clock\n", clknames[n]); 198 return ENXIO; 199 } 200 error = clk_enable(clk); 201 if (error != 0) { 202 aprint_error(": couldn't enable %s clock: %d\n", 203 clknames[n], error); 204 return error; 205 } 206 } 207 208 for (n = 0; n < __arraycount(rstnames); n++) { 209 rst = fdtbus_reset_get(phandle, rstnames[n]); 210 if (rst == NULL) { 211 aprint_error(": couldn't get %s reset\n", rstnames[n]); 212 return ENXIO; 213 } 214 error = fdtbus_reset_deassert(rst); 215 if (error != 0) { 216 aprint_error(": couldn't de-assert %s reset: %d\n", 217 rstnames[n], error); 218 return error; 219 } 220 } 221 222 delay(5000); 223 224 return 0; 225 } 226 227 static int 228 rk_gmac_match(device_t parent, cfdata_t cf, void *aux) 229 { 230 struct fdt_attach_args * const faa = aux; 231 232 return of_match_compatible(faa->faa_phandle, compatible); 233 } 234 235 static void 236 rk_gmac_attach(device_t parent, device_t self, void *aux) 237 { 238 struct rk_gmac_softc * const rk_sc = device_private(self); 239 struct dwc_gmac_softc * const sc = &rk_sc->sc_base; 240 struct fdt_attach_args * const faa = aux; 241 const int phandle = faa->faa_phandle; 242 const char *phy_mode; 243 char intrstr[128]; 244 bus_addr_t addr, grf_addr; 245 bus_size_t size, grf_size; 246 u_int tx_delay, rx_delay; 247 248 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 249 aprint_error(": couldn't get registers\n"); 250 return; 251 } 252 253 const int grf_phandle = fdtbus_get_phandle(phandle, "rockchip,grf"); 254 if (grf_phandle == -1) { 255 aprint_error(": couldn't get grf phandle\n"); 256 return; 257 } 258 if (fdtbus_get_reg(grf_phandle, 0, &grf_addr, &grf_size) != 0) { 259 aprint_error(": couldn't get grf registers\n"); 260 return; 261 } 262 if (bus_space_map(faa->faa_bst, grf_addr, grf_size, 0, &rk_sc->sc_grf_bsh) != 0) { 263 aprint_error(": couldn't map grf registers\n"); 264 return; 265 } 266 267 if (of_getprop_uint32(phandle, "tx_delay", &tx_delay) != 0) 268 tx_delay = RK_GMAC_TXDLY_DEFAULT; 269 270 if (of_getprop_uint32(phandle, "rx_delay", &rx_delay) != 0) 271 rx_delay = RK_GMAC_RXDLY_DEFAULT; 272 273 sc->sc_dev = self; 274 sc->sc_bst = faa->faa_bst; 275 if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) { 276 aprint_error(": couldn't map registers\n"); 277 return; 278 } 279 sc->sc_dmat = faa->faa_dmat; 280 281 if (!fdtbus_intr_str(phandle, 0, intrstr, sizeof(intrstr))) { 282 aprint_error(": failed to decode interrupt\n"); 283 return; 284 } 285 286 if (rk_gmac_setup_clocks(phandle) != 0) 287 return; 288 289 if (rk_gmac_reset(phandle) != 0) 290 aprint_error_dev(self, "PHY reset failed\n"); 291 292 if (of_hasprop(phandle, "snps,force_thresh_dma_mode")) 293 sc->sc_flags |= DWC_GMAC_FORCE_THRESH_DMA_MODE; 294 295 phy_mode = fdtbus_get_string(phandle, "phy-mode"); 296 if (phy_mode == NULL) { 297 aprint_error(": missing 'phy-mode' property\n"); 298 return; 299 } 300 301 if (strcmp(phy_mode, "rgmii") == 0) { 302 rk3328_gmac_set_mode_rgmii(sc, tx_delay, rx_delay); 303 304 sc->sc_set_speed = rk3328_gmac_set_speed_rgmii; 305 } else { 306 aprint_error(": unsupported phy-mode '%s'\n", phy_mode); 307 return; 308 } 309 310 aprint_naive("\n"); 311 aprint_normal(": GMAC\n"); 312 313 if (fdtbus_intr_establish(phandle, 0, IPL_NET, 0, rk_gmac_intr, sc) == NULL) { 314 aprint_error_dev(self, "failed to establish interrupt on %s\n", intrstr); 315 return; 316 } 317 aprint_normal_dev(self, "interrupting on %s\n", intrstr); 318 319 dwc_gmac_attach(sc, GMAC_MII_CLK_150_250M_DIV102); 320 } 321 322 CFATTACH_DECL_NEW(rk_gmac, sizeof(struct rk_gmac_softc), 323 rk_gmac_match, rk_gmac_attach, NULL, NULL); 324
Indexes created Tue Sep 30 11:09:46 GMT 2025