rk_gmac.c revision 1.14
1 /* $NetBSD: rk_gmac.c,v 1.14 2019/07/21 08:24:32 mrg Exp $ */ 2 3 /*- 4 * Copyright (c) 2018 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 17 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 31 __KERNEL_RCSID(0, "$NetBSD: rk_gmac.c,v 1.14 2019/07/21 08:24:32 mrg Exp $"); 32 33 #include <sys/param.h> 34 #include <sys/bus.h> 35 #include <sys/device.h> 36 #include <sys/intr.h> 37 #include <sys/systm.h> 38 #include <sys/gpio.h> 39 #include <sys/rndsource.h> 40 41 #include <net/if.h> 42 #include <net/if_ether.h> 43 #include <net/if_media.h> 44 45 #include <dev/mii/miivar.h> 46 47 #include <dev/ic/dwc_gmac_var.h> 48 #include <dev/ic/dwc_gmac_reg.h> 49 50 #include <dev/fdt/fdtvar.h> 51 #include <dev/fdt/syscon.h> 52 53 #define RK_GMAC_TXDLY_DEFAULT 0x30 54 #define RK_GMAC_RXDLY_DEFAULT 0x10 55 56 enum rk_gmac_type { 57 GMAC_RK3328 = 1, 58 GMAC_RK3399 59 }; 60 61 static const struct of_compat_data compat_data[] = { 62 { "rockchip,rk3328-gmac", GMAC_RK3328 }, 63 { "rockchip,rk3399-gmac", GMAC_RK3399 }, 64 { NULL } 65 }; 66 67 struct rk_gmac_softc { 68 struct dwc_gmac_softc sc_base; 69 struct syscon *sc_syscon; 70 enum rk_gmac_type sc_type; 71 }; 72 73 /* 74 * RK3328 specific 75 */ 76 77 #define RK3328_GRF_MAC_CON0 0x0900 78 #define RK3328_GRF_MAC_CON0_RXDLY __BITS(13,7) 79 #define RK3328_GRF_MAC_CON0_TXDLY __BITS(6,0) 80 81 #define RK3328_GRF_MAC_CON1 0x0904 82 #define RK3328_GRF_MAC_CON1_CLKSEL __BITS(12,11) 83 #define RK3328_GRF_MAC_CON1_CLKSEL_125M 0 84 #define RK3328_GRF_MAC_CON1_CLKSEL_2_5M 2 85 #define RK3328_GRF_MAC_CON1_CLKSEL_25M 3 86 #define RK3328_GRF_MAC_CON1_MODE __BIT(9) 87 #define RK3328_GRF_MAC_CON1_SEL __BITS(6,4) 88 #define RK3328_GRF_MAC_CON1_SEL_RGMII 1 89 #define RK3328_GRF_MAC_CON1_RXDLY_EN __BIT(1) 90 #define RK3328_GRF_MAC_CON1_TXDLY_EN __BIT(0) 91 92 static void 93 rk3328_gmac_set_mode_rgmii(struct dwc_gmac_softc *sc, u_int tx_delay, u_int rx_delay) 94 { 95 struct rk_gmac_softc * const rk_sc = (struct rk_gmac_softc *)sc; 96 uint32_t write_mask, write_val; 97 98 syscon_lock(rk_sc->sc_syscon); 99 100 write_mask = (RK3328_GRF_MAC_CON1_MODE | RK3328_GRF_MAC_CON1_SEL) << 16; 101 write_val = __SHIFTIN(RK3328_GRF_MAC_CON1_SEL_RGMII, RK3328_GRF_MAC_CON1_SEL); 102 syscon_write_4(rk_sc->sc_syscon, RK3328_GRF_MAC_CON1, write_mask | write_val); 103 104 #if notyet 105 write_mask = (RK3328_GRF_MAC_CON0_TXDLY | RK3328_GRF_MAC_CON0_RXDLY) << 16; 106 write_val = __SHIFTIN(tx_delay, RK3328_GRF_MAC_CON0_TXDLY) | 107 __SHIFTIN(rx_delay, RK3328_GRF_MAC_CON0_RXDLY); 108 syscon_write_4(rk_sc->sc_syscon, RK3328_GRF_MAC_CON0, write_mask | write_val); 109 110 write_mask = (RK3328_GRF_MAC_CON1_RXDLY_EN | RK3328_GRF_MAC_CON1_TXDLY_EN) << 16; 111 write_val = RK3328_GRF_MAC_CON1_RXDLY_EN | RK3328_GRF_MAC_CON1_TXDLY_EN; 112 syscon_write_4(rk_sc->sc_syscon, RK3328_GRF_MAC_CON1, write_mask | write_val); 113 #endif 114 115 syscon_unlock(rk_sc->sc_syscon); 116 } 117 118 static void 119 rk3328_gmac_set_speed_rgmii(struct dwc_gmac_softc *sc, int speed) 120 { 121 struct rk_gmac_softc * const rk_sc = (struct rk_gmac_softc *)sc; 122 #if 0 123 u_int clksel; 124 125 switch (speed) { 126 case IFM_10_T: 127 clksel = RK3328_GRF_MAC_CON1_CLKSEL_2_5M; 128 break; 129 case IFM_100_TX: 130 clksel = RK3328_GRF_MAC_CON1_CLKSEL_25M; 131 break; 132 default: 133 clksel = RK3328_GRF_MAC_CON1_CLKSEL_125M; 134 break; 135 } 136 #endif 137 138 syscon_lock(rk_sc->sc_syscon); 139 syscon_write_4(rk_sc->sc_syscon, RK3328_GRF_MAC_CON1, 140 (RK3328_GRF_MAC_CON1_CLKSEL << 16) | 141 __SHIFTIN(RK3328_GRF_MAC_CON1_CLKSEL_125M, RK3328_GRF_MAC_CON1_CLKSEL)); 142 syscon_unlock(rk_sc->sc_syscon); 143 } 144 145 /* 146 * RK3399 specific 147 */ 148 149 #define RK3399_GRF_SOC_CON5 0x0c214 150 #define RK3399_GRF_SOC_CON5_GMAC_PHY_INTF_SEL __BITS(11,9) 151 #define RK3399_GRF_SOC_CON5_GMAC_FLOWCTRL __BIT(8) 152 #define RK3399_GRF_SOC_CON5_GMAC_SPEED __BIT(7) 153 #define RK3399_GRF_SOC_CON5_RMII_MODE __BIT(6) 154 #define RK3399_GRF_SOC_CON5_GMAC_CLK_SEL __BITS(5,4) 155 #define RK3399_GRF_SOC_CON5_GMAC_CLK_SEL_125M 0 156 #define RK3399_GRF_SOC_CON5_GMAC_CLK_SEL_25M 3 157 #define RK3399_GRF_SOC_CON5_GMAC_CLK_SEL_2_5M 2 158 #define RK3399_GRF_SOC_CON5_RMII_CLK_SEL __BIT(3) 159 #define RK3399_GRF_SOC_CON6 0x0c218 160 #define RK3399_GRF_SOC_CON6_GMAC_RXCLK_DLY_ENA __BIT(15) 161 #define RK3399_GRF_SOC_CON6_GMAC_CLK_RX_DL_CFG __BITS(14,8) 162 #define RK3399_GRF_SOC_CON6_GMAC_TXCLK_DLY_ENA __BIT(7) 163 #define RK3399_GRF_SOC_CON6_GMAC_CLK_TX_DL_CFG __BITS(6,0) 164 165 static void 166 rk3399_gmac_set_mode_rgmii(struct dwc_gmac_softc *sc, u_int tx_delay, u_int rx_delay) 167 { 168 struct rk_gmac_softc * const rk_sc = (struct rk_gmac_softc *)sc; 169 170 const uint32_t con5_mask = 171 (RK3399_GRF_SOC_CON5_RMII_MODE | RK3399_GRF_SOC_CON5_GMAC_PHY_INTF_SEL) << 16; 172 const uint32_t con5 = __SHIFTIN(1, RK3399_GRF_SOC_CON5_GMAC_PHY_INTF_SEL); 173 174 #if notyet 175 const uint32_t con6_mask = 176 (RK3399_GRF_SOC_CON6_GMAC_RXCLK_DLY_ENA | 177 RK3399_GRF_SOC_CON6_GMAC_TXCLK_DLY_ENA | 178 RK3399_GRF_SOC_CON6_GMAC_CLK_RX_DL_CFG | 179 RK3399_GRF_SOC_CON6_GMAC_CLK_TX_DL_CFG) << 16; 180 const uint32_t con6 = 181 (tx_delay ? RK3399_GRF_SOC_CON6_GMAC_TXCLK_DLY_ENA : 0) | 182 (rx_delay ? RK3399_GRF_SOC_CON6_GMAC_RXCLK_DLY_ENA : 0) | 183 __SHIFTIN(rx_delay, RK3399_GRF_SOC_CON6_GMAC_CLK_RX_DL_CFG) | 184 __SHIFTIN(tx_delay, RK3399_GRF_SOC_CON6_GMAC_CLK_TX_DL_CFG); 185 #endif 186 187 syscon_lock(rk_sc->sc_syscon); 188 syscon_write_4(rk_sc->sc_syscon, RK3399_GRF_SOC_CON5, con5 | con5_mask); 189 #if notyet 190 syscon_write_4(rk_sc->sc_syscon, RK3399_GRF_SOC_CON6, con6 | con6_mask); 191 #endif 192 syscon_unlock(rk_sc->sc_syscon); 193 } 194 195 static void 196 rk3399_gmac_set_speed_rgmii(struct dwc_gmac_softc *sc, int speed) 197 { 198 struct rk_gmac_softc * const rk_sc = (struct rk_gmac_softc *)sc; 199 u_int clksel; 200 201 switch (speed) { 202 case IFM_10_T: 203 clksel = RK3399_GRF_SOC_CON5_GMAC_CLK_SEL_2_5M; 204 break; 205 case IFM_100_TX: 206 clksel = RK3399_GRF_SOC_CON5_GMAC_CLK_SEL_25M; 207 break; 208 default: 209 clksel = RK3399_GRF_SOC_CON5_GMAC_CLK_SEL_125M; 210 break; 211 } 212 213 const uint32_t con5_mask = 214 RK3399_GRF_SOC_CON5_GMAC_CLK_SEL << 16; 215 const uint32_t con5 = 216 __SHIFTIN(clksel, RK3399_GRF_SOC_CON5_GMAC_CLK_SEL); 217 218 syscon_lock(rk_sc->sc_syscon); 219 syscon_write_4(rk_sc->sc_syscon, RK3399_GRF_SOC_CON5, con5 | con5_mask); 220 syscon_unlock(rk_sc->sc_syscon); 221 } 222 223 static int 224 rk_gmac_reset(const int phandle) 225 { 226 struct fdtbus_gpio_pin *pin_reset; 227 const u_int *reset_delay_us; 228 bool reset_active_low; 229 int len; 230 231 if (!of_hasprop(phandle, "snps,reset-gpio")) 232 return 0; 233 234 pin_reset = fdtbus_gpio_acquire(phandle, "snps,reset-gpio", GPIO_PIN_OUTPUT); 235 if (pin_reset == NULL) 236 return ENOENT; 237 238 reset_delay_us = fdtbus_get_prop(phandle, "snps,reset-delays-us", &len); 239 if (reset_delay_us == NULL || len != 12) 240 return ENXIO; 241 242 reset_active_low = of_hasprop(phandle, "snps,reset-active-low"); 243 244 fdtbus_gpio_write_raw(pin_reset, reset_active_low ? 1 : 0); 245 delay(be32toh(reset_delay_us[0])); 246 fdtbus_gpio_write_raw(pin_reset, reset_active_low ? 0 : 1); 247 delay(be32toh(reset_delay_us[1])); 248 fdtbus_gpio_write_raw(pin_reset, reset_active_low ? 1 : 0); 249 delay(be32toh(reset_delay_us[2])); 250 251 return 0; 252 } 253 254 static int 255 rk_gmac_intr(void *arg) 256 { 257 return dwc_gmac_intr(arg); 258 } 259 260 static int 261 rk_gmac_setup_clocks(int phandle) 262 { 263 static const char * const clknames[] = { 264 #if 0 265 "stmmaceth", 266 "mac_clk_rx", 267 "mac_clk_tx", 268 "clk_mac_ref", 269 "clk_mac_refout", 270 "aclk_mac", 271 "pclk_mac" 272 #else 273 "stmmaceth", 274 "aclk_mac", 275 "pclk_mac", 276 "mac_clk_tx", 277 "mac_clk_rx" 278 #endif 279 }; 280 static const char * const rstnames[] = { 281 "stmmaceth" 282 }; 283 struct fdtbus_reset *rst; 284 struct clk *clk; 285 int error, n; 286 287 fdtbus_clock_assign(phandle); 288 289 for (n = 0; n < __arraycount(clknames); n++) { 290 clk = fdtbus_clock_get(phandle, clknames[n]); 291 if (clk == NULL) { 292 aprint_error(": couldn't get %s clock\n", clknames[n]); 293 return ENXIO; 294 } 295 error = clk_enable(clk); 296 if (error != 0) { 297 aprint_error(": couldn't enable %s clock: %d\n", 298 clknames[n], error); 299 return error; 300 } 301 } 302 303 for (n = 0; n < __arraycount(rstnames); n++) { 304 rst = fdtbus_reset_get(phandle, rstnames[n]); 305 if (rst == NULL) { 306 aprint_error(": couldn't get %s reset\n", rstnames[n]); 307 return ENXIO; 308 } 309 error = fdtbus_reset_deassert(rst); 310 if (error != 0) { 311 aprint_error(": couldn't de-assert %s reset: %d\n", 312 rstnames[n], error); 313 return error; 314 } 315 } 316 317 delay(5000); 318 319 return 0; 320 } 321 322 static int 323 rk_gmac_match(device_t parent, cfdata_t cf, void *aux) 324 { 325 struct fdt_attach_args * const faa = aux; 326 327 return of_match_compat_data(faa->faa_phandle, compat_data); 328 } 329 330 static void 331 rk_gmac_attach(device_t parent, device_t self, void *aux) 332 { 333 struct rk_gmac_softc * const rk_sc = device_private(self); 334 struct dwc_gmac_softc * const sc = &rk_sc->sc_base; 335 struct fdt_attach_args * const faa = aux; 336 const int phandle = faa->faa_phandle; 337 const char *phy_mode; 338 char intrstr[128]; 339 bus_addr_t addr; 340 bus_size_t size; 341 u_int tx_delay, rx_delay; 342 343 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 344 aprint_error(": couldn't get registers\n"); 345 return; 346 } 347 348 rk_sc->sc_type = of_search_compatible(phandle, compat_data)->data; 349 350 rk_sc->sc_syscon = fdtbus_syscon_acquire(phandle, "rockchip,grf"); 351 if (rk_sc->sc_syscon == NULL) { 352 aprint_error(": couldn't get grf syscon\n"); 353 return; 354 } 355 356 if (of_getprop_uint32(phandle, "tx_delay", &tx_delay) != 0) 357 tx_delay = RK_GMAC_TXDLY_DEFAULT; 358 359 if (of_getprop_uint32(phandle, "rx_delay", &rx_delay) != 0) 360 rx_delay = RK_GMAC_RXDLY_DEFAULT; 361 362 sc->sc_dev = self; 363 sc->sc_bst = faa->faa_bst; 364 if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) { 365 aprint_error(": couldn't map registers\n"); 366 return; 367 } 368 sc->sc_dmat = faa->faa_dmat; 369 370 if (!fdtbus_intr_str(phandle, 0, intrstr, sizeof(intrstr))) { 371 aprint_error(": failed to decode interrupt\n"); 372 return; 373 } 374 375 if (rk_gmac_setup_clocks(phandle) != 0) 376 return; 377 378 if (rk_gmac_reset(phandle) != 0) 379 aprint_error_dev(self, "PHY reset failed\n"); 380 381 /* Rock64 seems to need more time for the reset to complete */ 382 delay(100000); 383 384 #if notyet 385 if (of_hasprop(phandle, "snps,force_thresh_dma_mode")) 386 sc->sc_flags |= DWC_GMAC_FORCE_THRESH_DMA_MODE; 387 #endif 388 389 phy_mode = fdtbus_get_string(phandle, "phy-mode"); 390 if (phy_mode == NULL) { 391 aprint_error(": missing 'phy-mode' property\n"); 392 return; 393 } 394 395 switch (rk_sc->sc_type) { 396 case GMAC_RK3328: 397 if (strcmp(phy_mode, "rgmii") == 0) { 398 rk3328_gmac_set_mode_rgmii(sc, tx_delay, rx_delay); 399 400 sc->sc_set_speed = rk3328_gmac_set_speed_rgmii; 401 } else { 402 aprint_error(": unsupported phy-mode '%s'\n", phy_mode); 403 return; 404 } 405 break; 406 case GMAC_RK3399: 407 if (strcmp(phy_mode, "rgmii") == 0) { 408 rk3399_gmac_set_mode_rgmii(sc, tx_delay, rx_delay); 409 410 sc->sc_set_speed = rk3399_gmac_set_speed_rgmii; 411 } else { 412 aprint_error(": unsupported phy-mode '%s'\n", phy_mode); 413 return; 414 } 415 break; 416 } 417 418 aprint_naive("\n"); 419 aprint_normal(": GMAC\n"); 420 421 if (dwc_gmac_attach(sc, MII_PHY_ANY, GMAC_MII_CLK_150_250M_DIV102) != 0) 422 return; 423 424 if (fdtbus_intr_establish(phandle, 0, IPL_NET, DWCGMAC_FDT_INTR_MPSAFE, 425 rk_gmac_intr, sc) == NULL) { 426 aprint_error_dev(self, "failed to establish interrupt on %s\n", intrstr); 427 return; 428 } 429 aprint_normal_dev(self, "interrupting on %s\n", intrstr); 430 } 431 432 CFATTACH_DECL_NEW(rk_gmac, sizeof(struct rk_gmac_softc), 433 rk_gmac_match, rk_gmac_attach, NULL, NULL); 434
Indexes created Tue Sep 30 17:09:57 GMT 2025