rk_gmac.c revision 1.15
1 /* $NetBSD: rk_gmac.c,v 1.15 2019/11/09 17:21:48 tnn Exp $ */ 2 3 /*- 4 * Copyright (c) 2018 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 17 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 31 __KERNEL_RCSID(0, "$NetBSD: rk_gmac.c,v 1.15 2019/11/09 17:21:48 tnn Exp $"); 32 33 #include <sys/param.h> 34 #include <sys/bus.h> 35 #include <sys/device.h> 36 #include <sys/intr.h> 37 #include <sys/systm.h> 38 #include <sys/gpio.h> 39 #include <sys/rndsource.h> 40 41 #include <net/if.h> 42 #include <net/if_ether.h> 43 #include <net/if_media.h> 44 45 #include <dev/mii/miivar.h> 46 47 #include <dev/ic/dwc_gmac_var.h> 48 #include <dev/ic/dwc_gmac_reg.h> 49 50 #include <dev/fdt/fdtvar.h> 51 #include <dev/fdt/syscon.h> 52 53 #define RK_GMAC_TXDLY_DEFAULT 0x30 54 #define RK_GMAC_RXDLY_DEFAULT 0x10 55 56 enum rk_gmac_type { 57 GMAC_RK3328 = 1, 58 GMAC_RK3399 59 }; 60 61 static const struct of_compat_data compat_data[] = { 62 { "rockchip,rk3328-gmac", GMAC_RK3328 }, 63 { "rockchip,rk3399-gmac", GMAC_RK3399 }, 64 { NULL } 65 }; 66 67 struct rk_gmac_softc { 68 struct dwc_gmac_softc sc_base; 69 struct syscon *sc_syscon; 70 enum rk_gmac_type sc_type; 71 }; 72 73 /* 74 * RK3328 specific 75 */ 76 77 #define RK3328_GRF_MAC_CON0 0x0900 78 #define RK3328_GRF_MAC_CON0_RXDLY __BITS(13,7) 79 #define RK3328_GRF_MAC_CON0_TXDLY __BITS(6,0) 80 81 #define RK3328_GRF_MAC_CON1 0x0904 82 #define RK3328_GRF_MAC_CON1_CLKSEL __BITS(12,11) 83 #define RK3328_GRF_MAC_CON1_CLKSEL_125M 0 84 #define RK3328_GRF_MAC_CON1_CLKSEL_2_5M 2 85 #define RK3328_GRF_MAC_CON1_CLKSEL_25M 3 86 #define RK3328_GRF_MAC_CON1_MODE __BIT(9) 87 #define RK3328_GRF_MAC_CON1_SEL __BITS(6,4) 88 #define RK3328_GRF_MAC_CON1_SEL_RGMII 1 89 #define RK3328_GRF_MAC_CON1_RXDLY_EN __BIT(1) 90 #define RK3328_GRF_MAC_CON1_TXDLY_EN __BIT(0) 91 92 static void 93 rk3328_gmac_set_mode_rgmii(struct dwc_gmac_softc *sc, u_int tx_delay, u_int rx_delay, bool set_delay) 94 { 95 struct rk_gmac_softc * const rk_sc = (struct rk_gmac_softc *)sc; 96 uint32_t write_mask, write_val; 97 98 syscon_lock(rk_sc->sc_syscon); 99 100 write_mask = (RK3328_GRF_MAC_CON1_MODE | RK3328_GRF_MAC_CON1_SEL) << 16; 101 write_val = __SHIFTIN(RK3328_GRF_MAC_CON1_SEL_RGMII, 102 RK3328_GRF_MAC_CON1_SEL); 103 syscon_write_4(rk_sc->sc_syscon, RK3328_GRF_MAC_CON1, 104 write_mask | write_val); 105 106 if (set_delay) { 107 write_mask = ( 108 RK3328_GRF_MAC_CON0_TXDLY | 109 RK3328_GRF_MAC_CON0_RXDLY) << 16; 110 write_val = 111 __SHIFTIN(tx_delay, RK3328_GRF_MAC_CON0_TXDLY) | 112 __SHIFTIN(rx_delay, RK3328_GRF_MAC_CON0_RXDLY); 113 syscon_write_4(rk_sc->sc_syscon, RK3328_GRF_MAC_CON0, 114 write_mask | write_val); 115 116 write_mask = ( 117 RK3328_GRF_MAC_CON1_RXDLY_EN | 118 RK3328_GRF_MAC_CON1_TXDLY_EN) << 16; 119 write_val = 120 RK3328_GRF_MAC_CON1_RXDLY_EN | 121 RK3328_GRF_MAC_CON1_TXDLY_EN; 122 syscon_write_4(rk_sc->sc_syscon, RK3328_GRF_MAC_CON1, 123 write_mask | write_val); 124 } 125 126 syscon_unlock(rk_sc->sc_syscon); 127 } 128 129 static void 130 rk3328_gmac_set_speed_rgmii(struct dwc_gmac_softc *sc, int speed) 131 { 132 struct rk_gmac_softc * const rk_sc = (struct rk_gmac_softc *)sc; 133 #if 0 134 u_int clksel; 135 136 switch (speed) { 137 case IFM_10_T: 138 clksel = RK3328_GRF_MAC_CON1_CLKSEL_2_5M; 139 break; 140 case IFM_100_TX: 141 clksel = RK3328_GRF_MAC_CON1_CLKSEL_25M; 142 break; 143 default: 144 clksel = RK3328_GRF_MAC_CON1_CLKSEL_125M; 145 break; 146 } 147 #endif 148 149 syscon_lock(rk_sc->sc_syscon); 150 syscon_write_4(rk_sc->sc_syscon, RK3328_GRF_MAC_CON1, 151 (RK3328_GRF_MAC_CON1_CLKSEL << 16) | 152 __SHIFTIN(RK3328_GRF_MAC_CON1_CLKSEL_125M, RK3328_GRF_MAC_CON1_CLKSEL)); 153 syscon_unlock(rk_sc->sc_syscon); 154 } 155 156 /* 157 * RK3399 specific 158 */ 159 160 #define RK3399_GRF_SOC_CON5 0x0c214 161 #define RK3399_GRF_SOC_CON5_GMAC_PHY_INTF_SEL __BITS(11,9) 162 #define RK3399_GRF_SOC_CON5_GMAC_FLOWCTRL __BIT(8) 163 #define RK3399_GRF_SOC_CON5_GMAC_SPEED __BIT(7) 164 #define RK3399_GRF_SOC_CON5_RMII_MODE __BIT(6) 165 #define RK3399_GRF_SOC_CON5_GMAC_CLK_SEL __BITS(5,4) 166 #define RK3399_GRF_SOC_CON5_GMAC_CLK_SEL_125M 0 167 #define RK3399_GRF_SOC_CON5_GMAC_CLK_SEL_25M 3 168 #define RK3399_GRF_SOC_CON5_GMAC_CLK_SEL_2_5M 2 169 #define RK3399_GRF_SOC_CON5_RMII_CLK_SEL __BIT(3) 170 #define RK3399_GRF_SOC_CON6 0x0c218 171 #define RK3399_GRF_SOC_CON6_GMAC_RXCLK_DLY_ENA __BIT(15) 172 #define RK3399_GRF_SOC_CON6_GMAC_CLK_RX_DL_CFG __BITS(14,8) 173 #define RK3399_GRF_SOC_CON6_GMAC_TXCLK_DLY_ENA __BIT(7) 174 #define RK3399_GRF_SOC_CON6_GMAC_CLK_TX_DL_CFG __BITS(6,0) 175 176 static void 177 rk3399_gmac_set_mode_rgmii(struct dwc_gmac_softc *sc, u_int tx_delay, 178 u_int rx_delay, bool set_delay) 179 { 180 struct rk_gmac_softc * const rk_sc = (struct rk_gmac_softc *)sc; 181 uint32_t write_mask, write_val; 182 183 syscon_lock(rk_sc->sc_syscon); 184 185 write_mask = ( 186 RK3399_GRF_SOC_CON5_RMII_MODE | 187 RK3399_GRF_SOC_CON5_GMAC_PHY_INTF_SEL) << 16; 188 write_val = __SHIFTIN(1, RK3399_GRF_SOC_CON5_GMAC_PHY_INTF_SEL); 189 syscon_write_4(rk_sc->sc_syscon, RK3399_GRF_SOC_CON5, 190 write_mask | write_val); 191 if (set_delay) { 192 write_mask = ( 193 RK3399_GRF_SOC_CON6_GMAC_TXCLK_DLY_ENA | 194 RK3399_GRF_SOC_CON6_GMAC_RXCLK_DLY_ENA | 195 RK3399_GRF_SOC_CON6_GMAC_CLK_RX_DL_CFG | 196 RK3399_GRF_SOC_CON6_GMAC_CLK_TX_DL_CFG) << 16; 197 write_val = 198 (tx_delay ? RK3399_GRF_SOC_CON6_GMAC_TXCLK_DLY_ENA : 0) | 199 (rx_delay ? RK3399_GRF_SOC_CON6_GMAC_RXCLK_DLY_ENA : 0) | 200 __SHIFTIN(rx_delay, RK3399_GRF_SOC_CON6_GMAC_CLK_RX_DL_CFG) | 201 __SHIFTIN(tx_delay, RK3399_GRF_SOC_CON6_GMAC_CLK_TX_DL_CFG); 202 syscon_write_4(rk_sc->sc_syscon, RK3399_GRF_SOC_CON6, 203 write_mask | write_val); 204 } 205 syscon_unlock(rk_sc->sc_syscon); 206 } 207 208 static void 209 rk3399_gmac_set_speed_rgmii(struct dwc_gmac_softc *sc, int speed) 210 { 211 struct rk_gmac_softc * const rk_sc = (struct rk_gmac_softc *)sc; 212 u_int clksel; 213 214 switch (speed) { 215 case IFM_10_T: 216 clksel = RK3399_GRF_SOC_CON5_GMAC_CLK_SEL_2_5M; 217 break; 218 case IFM_100_TX: 219 clksel = RK3399_GRF_SOC_CON5_GMAC_CLK_SEL_25M; 220 break; 221 default: 222 clksel = RK3399_GRF_SOC_CON5_GMAC_CLK_SEL_125M; 223 break; 224 } 225 226 const uint32_t con5_mask = 227 RK3399_GRF_SOC_CON5_GMAC_CLK_SEL << 16; 228 const uint32_t con5 = 229 __SHIFTIN(clksel, RK3399_GRF_SOC_CON5_GMAC_CLK_SEL); 230 231 syscon_lock(rk_sc->sc_syscon); 232 syscon_write_4(rk_sc->sc_syscon, RK3399_GRF_SOC_CON5, con5 | con5_mask); 233 syscon_unlock(rk_sc->sc_syscon); 234 } 235 236 static int 237 rk_gmac_reset(const int phandle) 238 { 239 struct fdtbus_gpio_pin *pin_reset; 240 const u_int *reset_delay_us; 241 bool reset_active_low; 242 int len; 243 244 if (!of_hasprop(phandle, "snps,reset-gpio")) 245 return 0; 246 247 pin_reset = fdtbus_gpio_acquire(phandle, "snps,reset-gpio", GPIO_PIN_OUTPUT); 248 if (pin_reset == NULL) 249 return ENOENT; 250 251 reset_delay_us = fdtbus_get_prop(phandle, "snps,reset-delays-us", &len); 252 if (reset_delay_us == NULL || len != 12) 253 return ENXIO; 254 255 reset_active_low = of_hasprop(phandle, "snps,reset-active-low"); 256 257 fdtbus_gpio_write_raw(pin_reset, reset_active_low ? 1 : 0); 258 delay(be32toh(reset_delay_us[0])); 259 fdtbus_gpio_write_raw(pin_reset, reset_active_low ? 0 : 1); 260 delay(be32toh(reset_delay_us[1])); 261 fdtbus_gpio_write_raw(pin_reset, reset_active_low ? 1 : 0); 262 delay(be32toh(reset_delay_us[2])); 263 264 return 0; 265 } 266 267 static int 268 rk_gmac_intr(void *arg) 269 { 270 return dwc_gmac_intr(arg); 271 } 272 273 static int 274 rk_gmac_setup_clocks(int phandle) 275 { 276 static const char * const clknames[] = { 277 #if 0 278 "stmmaceth", 279 "mac_clk_rx", 280 "mac_clk_tx", 281 "clk_mac_ref", 282 "clk_mac_refout", 283 "aclk_mac", 284 "pclk_mac" 285 #else 286 "stmmaceth", 287 "aclk_mac", 288 "pclk_mac", 289 "mac_clk_tx", 290 "mac_clk_rx" 291 #endif 292 }; 293 static const char * const rstnames[] = { 294 "stmmaceth" 295 }; 296 struct fdtbus_reset *rst; 297 struct clk *clk; 298 int error, n; 299 300 fdtbus_clock_assign(phandle); 301 302 for (n = 0; n < __arraycount(clknames); n++) { 303 clk = fdtbus_clock_get(phandle, clknames[n]); 304 if (clk == NULL) { 305 aprint_error(": couldn't get %s clock\n", clknames[n]); 306 return ENXIO; 307 } 308 error = clk_enable(clk); 309 if (error != 0) { 310 aprint_error(": couldn't enable %s clock: %d\n", 311 clknames[n], error); 312 return error; 313 } 314 } 315 316 for (n = 0; n < __arraycount(rstnames); n++) { 317 rst = fdtbus_reset_get(phandle, rstnames[n]); 318 if (rst == NULL) { 319 aprint_error(": couldn't get %s reset\n", rstnames[n]); 320 return ENXIO; 321 } 322 error = fdtbus_reset_deassert(rst); 323 if (error != 0) { 324 aprint_error(": couldn't de-assert %s reset: %d\n", 325 rstnames[n], error); 326 return error; 327 } 328 } 329 330 delay(5000); 331 332 return 0; 333 } 334 335 static int 336 rk_gmac_match(device_t parent, cfdata_t cf, void *aux) 337 { 338 struct fdt_attach_args * const faa = aux; 339 340 return of_match_compat_data(faa->faa_phandle, compat_data); 341 } 342 343 static void 344 rk_gmac_attach(device_t parent, device_t self, void *aux) 345 { 346 struct rk_gmac_softc * const rk_sc = device_private(self); 347 struct dwc_gmac_softc * const sc = &rk_sc->sc_base; 348 struct fdt_attach_args * const faa = aux; 349 const int phandle = faa->faa_phandle; 350 const char *phy_mode; 351 char intrstr[128]; 352 bus_addr_t addr; 353 bus_size_t size; 354 u_int tx_delay, rx_delay; 355 #ifdef notyet 356 bool set_delay = true; 357 #else 358 bool set_delay = false; 359 #endif 360 361 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 362 aprint_error(": couldn't get registers\n"); 363 return; 364 } 365 366 rk_sc->sc_type = of_search_compatible(phandle, compat_data)->data; 367 368 rk_sc->sc_syscon = fdtbus_syscon_acquire(phandle, "rockchip,grf"); 369 if (rk_sc->sc_syscon == NULL) { 370 aprint_error(": couldn't get grf syscon\n"); 371 return; 372 } 373 374 if (of_getprop_uint32(phandle, "tx_delay", &tx_delay) != 0) { 375 tx_delay = RK_GMAC_TXDLY_DEFAULT; 376 set_delay = false; 377 } 378 379 if (of_getprop_uint32(phandle, "rx_delay", &rx_delay) != 0) { 380 rx_delay = RK_GMAC_RXDLY_DEFAULT; 381 set_delay = false; 382 } 383 384 sc->sc_dev = self; 385 sc->sc_bst = faa->faa_bst; 386 if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) { 387 aprint_error(": couldn't map registers\n"); 388 return; 389 } 390 sc->sc_dmat = faa->faa_dmat; 391 392 if (!fdtbus_intr_str(phandle, 0, intrstr, sizeof(intrstr))) { 393 aprint_error(": failed to decode interrupt\n"); 394 return; 395 } 396 397 if (rk_gmac_setup_clocks(phandle) != 0) 398 return; 399 400 if (rk_gmac_reset(phandle) != 0) 401 aprint_error_dev(self, "PHY reset failed\n"); 402 403 /* Rock64 seems to need more time for the reset to complete */ 404 delay(100000); 405 406 #if notyet 407 if (of_hasprop(phandle, "snps,force_thresh_dma_mode")) 408 sc->sc_flags |= DWC_GMAC_FORCE_THRESH_DMA_MODE; 409 #endif 410 411 phy_mode = fdtbus_get_string(phandle, "phy-mode"); 412 if (phy_mode == NULL) { 413 aprint_error(": missing 'phy-mode' property\n"); 414 return; 415 } 416 417 switch (rk_sc->sc_type) { 418 case GMAC_RK3328: 419 if (strcmp(phy_mode, "rgmii") == 0) { 420 rk3328_gmac_set_mode_rgmii(sc, tx_delay, rx_delay, 421 set_delay); 422 423 sc->sc_set_speed = rk3328_gmac_set_speed_rgmii; 424 } else { 425 aprint_error(": unsupported phy-mode '%s'\n", phy_mode); 426 return; 427 } 428 break; 429 case GMAC_RK3399: 430 if (strcmp(phy_mode, "rgmii") == 0) { 431 rk3399_gmac_set_mode_rgmii(sc, tx_delay, rx_delay, 432 set_delay); 433 434 sc->sc_set_speed = rk3399_gmac_set_speed_rgmii; 435 } else { 436 aprint_error(": unsupported phy-mode '%s'\n", phy_mode); 437 return; 438 } 439 break; 440 } 441 442 aprint_naive("\n"); 443 aprint_normal(": GMAC\n"); 444 445 if (dwc_gmac_attach(sc, MII_PHY_ANY, GMAC_MII_CLK_150_250M_DIV102) != 0) 446 return; 447 448 if (fdtbus_intr_establish(phandle, 0, IPL_NET, DWCGMAC_FDT_INTR_MPSAFE, 449 rk_gmac_intr, sc) == NULL) { 450 aprint_error_dev(self, "failed to establish interrupt on %s\n", intrstr); 451 return; 452 } 453 aprint_normal_dev(self, "interrupting on %s\n", intrstr); 454 } 455 456 CFATTACH_DECL_NEW(rk_gmac, sizeof(struct rk_gmac_softc), 457 rk_gmac_match, rk_gmac_attach, NULL, NULL); 458
Indexes created Tue Sep 30 11:09:46 GMT 2025