rk_gmac.c revision 1.17
1 /* $NetBSD: rk_gmac.c,v 1.17 2021/01/18 02:35:49 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2018 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 17 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 31 __KERNEL_RCSID(0, "$NetBSD: rk_gmac.c,v 1.17 2021/01/18 02:35:49 thorpej Exp $"); 32 33 #include <sys/param.h> 34 #include <sys/bus.h> 35 #include <sys/device.h> 36 #include <sys/intr.h> 37 #include <sys/systm.h> 38 #include <sys/gpio.h> 39 #include <sys/rndsource.h> 40 41 #include <net/if.h> 42 #include <net/if_ether.h> 43 #include <net/if_media.h> 44 45 #include <dev/mii/miivar.h> 46 47 #include <dev/ic/dwc_gmac_var.h> 48 #include <dev/ic/dwc_gmac_reg.h> 49 50 #include <dev/fdt/fdtvar.h> 51 #include <dev/fdt/syscon.h> 52 53 #define RK_GMAC_TXDLY_DEFAULT 0x30 54 #define RK_GMAC_RXDLY_DEFAULT 0x10 55 56 enum rk_gmac_type { 57 GMAC_RK3328 = 1, 58 GMAC_RK3399 59 }; 60 61 static const struct device_compatible_entry compat_data[] = { 62 { .compat = "rockchip,rk3328-gmac", .value = GMAC_RK3328 }, 63 { .compat = "rockchip,rk3399-gmac", .value = GMAC_RK3399 }, 64 65 { 0 } 66 }; 67 68 struct rk_gmac_softc { 69 struct dwc_gmac_softc sc_base; 70 struct syscon *sc_syscon; 71 enum rk_gmac_type sc_type; 72 }; 73 74 /* 75 * RK3328 specific 76 */ 77 78 #define RK3328_GRF_MAC_CON0 0x0900 79 #define RK3328_GRF_MAC_CON0_RXDLY __BITS(13,7) 80 #define RK3328_GRF_MAC_CON0_TXDLY __BITS(6,0) 81 82 #define RK3328_GRF_MAC_CON1 0x0904 83 #define RK3328_GRF_MAC_CON1_CLKSEL __BITS(12,11) 84 #define RK3328_GRF_MAC_CON1_CLKSEL_125M 0 85 #define RK3328_GRF_MAC_CON1_CLKSEL_2_5M 2 86 #define RK3328_GRF_MAC_CON1_CLKSEL_25M 3 87 #define RK3328_GRF_MAC_CON1_MODE __BIT(9) 88 #define RK3328_GRF_MAC_CON1_SEL __BITS(6,4) 89 #define RK3328_GRF_MAC_CON1_SEL_RGMII 1 90 #define RK3328_GRF_MAC_CON1_RXDLY_EN __BIT(1) 91 #define RK3328_GRF_MAC_CON1_TXDLY_EN __BIT(0) 92 93 static void 94 rk3328_gmac_set_mode_rgmii(struct dwc_gmac_softc *sc, u_int tx_delay, u_int rx_delay, bool set_delay) 95 { 96 struct rk_gmac_softc * const rk_sc = (struct rk_gmac_softc *)sc; 97 uint32_t write_mask, write_val; 98 99 syscon_lock(rk_sc->sc_syscon); 100 101 write_mask = (RK3328_GRF_MAC_CON1_MODE | RK3328_GRF_MAC_CON1_SEL) << 16; 102 write_val = __SHIFTIN(RK3328_GRF_MAC_CON1_SEL_RGMII, 103 RK3328_GRF_MAC_CON1_SEL); 104 syscon_write_4(rk_sc->sc_syscon, RK3328_GRF_MAC_CON1, 105 write_mask | write_val); 106 107 if (set_delay) { 108 write_mask = ( 109 RK3328_GRF_MAC_CON0_TXDLY | 110 RK3328_GRF_MAC_CON0_RXDLY) << 16; 111 write_val = 112 __SHIFTIN(tx_delay, RK3328_GRF_MAC_CON0_TXDLY) | 113 __SHIFTIN(rx_delay, RK3328_GRF_MAC_CON0_RXDLY); 114 syscon_write_4(rk_sc->sc_syscon, RK3328_GRF_MAC_CON0, 115 write_mask | write_val); 116 117 write_mask = ( 118 RK3328_GRF_MAC_CON1_RXDLY_EN | 119 RK3328_GRF_MAC_CON1_TXDLY_EN) << 16; 120 write_val = 121 RK3328_GRF_MAC_CON1_RXDLY_EN | 122 RK3328_GRF_MAC_CON1_TXDLY_EN; 123 syscon_write_4(rk_sc->sc_syscon, RK3328_GRF_MAC_CON1, 124 write_mask | write_val); 125 } 126 127 syscon_unlock(rk_sc->sc_syscon); 128 } 129 130 static void 131 rk3328_gmac_set_speed_rgmii(struct dwc_gmac_softc *sc, int speed) 132 { 133 struct rk_gmac_softc * const rk_sc = (struct rk_gmac_softc *)sc; 134 #if 0 135 u_int clksel; 136 137 switch (speed) { 138 case IFM_10_T: 139 clksel = RK3328_GRF_MAC_CON1_CLKSEL_2_5M; 140 break; 141 case IFM_100_TX: 142 clksel = RK3328_GRF_MAC_CON1_CLKSEL_25M; 143 break; 144 default: 145 clksel = RK3328_GRF_MAC_CON1_CLKSEL_125M; 146 break; 147 } 148 #endif 149 150 syscon_lock(rk_sc->sc_syscon); 151 syscon_write_4(rk_sc->sc_syscon, RK3328_GRF_MAC_CON1, 152 (RK3328_GRF_MAC_CON1_CLKSEL << 16) | 153 __SHIFTIN(RK3328_GRF_MAC_CON1_CLKSEL_125M, RK3328_GRF_MAC_CON1_CLKSEL)); 154 syscon_unlock(rk_sc->sc_syscon); 155 } 156 157 /* 158 * RK3399 specific 159 */ 160 161 #define RK3399_GRF_SOC_CON5 0x0c214 162 #define RK3399_GRF_SOC_CON5_GMAC_PHY_INTF_SEL __BITS(11,9) 163 #define RK3399_GRF_SOC_CON5_GMAC_FLOWCTRL __BIT(8) 164 #define RK3399_GRF_SOC_CON5_GMAC_SPEED __BIT(7) 165 #define RK3399_GRF_SOC_CON5_RMII_MODE __BIT(6) 166 #define RK3399_GRF_SOC_CON5_GMAC_CLK_SEL __BITS(5,4) 167 #define RK3399_GRF_SOC_CON5_GMAC_CLK_SEL_125M 0 168 #define RK3399_GRF_SOC_CON5_GMAC_CLK_SEL_25M 3 169 #define RK3399_GRF_SOC_CON5_GMAC_CLK_SEL_2_5M 2 170 #define RK3399_GRF_SOC_CON5_RMII_CLK_SEL __BIT(3) 171 #define RK3399_GRF_SOC_CON6 0x0c218 172 #define RK3399_GRF_SOC_CON6_GMAC_RXCLK_DLY_ENA __BIT(15) 173 #define RK3399_GRF_SOC_CON6_GMAC_CLK_RX_DL_CFG __BITS(14,8) 174 #define RK3399_GRF_SOC_CON6_GMAC_TXCLK_DLY_ENA __BIT(7) 175 #define RK3399_GRF_SOC_CON6_GMAC_CLK_TX_DL_CFG __BITS(6,0) 176 177 static void 178 rk3399_gmac_set_mode_rgmii(struct dwc_gmac_softc *sc, u_int tx_delay, 179 u_int rx_delay, bool set_delay) 180 { 181 struct rk_gmac_softc * const rk_sc = (struct rk_gmac_softc *)sc; 182 uint32_t write_mask, write_val; 183 184 syscon_lock(rk_sc->sc_syscon); 185 186 write_mask = ( 187 RK3399_GRF_SOC_CON5_RMII_MODE | 188 RK3399_GRF_SOC_CON5_GMAC_PHY_INTF_SEL) << 16; 189 write_val = __SHIFTIN(1, RK3399_GRF_SOC_CON5_GMAC_PHY_INTF_SEL); 190 syscon_write_4(rk_sc->sc_syscon, RK3399_GRF_SOC_CON5, 191 write_mask | write_val); 192 if (set_delay) { 193 write_mask = ( 194 RK3399_GRF_SOC_CON6_GMAC_TXCLK_DLY_ENA | 195 RK3399_GRF_SOC_CON6_GMAC_RXCLK_DLY_ENA | 196 RK3399_GRF_SOC_CON6_GMAC_CLK_RX_DL_CFG | 197 RK3399_GRF_SOC_CON6_GMAC_CLK_TX_DL_CFG) << 16; 198 write_val = 199 (tx_delay ? RK3399_GRF_SOC_CON6_GMAC_TXCLK_DLY_ENA : 0) | 200 (rx_delay ? RK3399_GRF_SOC_CON6_GMAC_RXCLK_DLY_ENA : 0) | 201 __SHIFTIN(rx_delay, RK3399_GRF_SOC_CON6_GMAC_CLK_RX_DL_CFG) | 202 __SHIFTIN(tx_delay, RK3399_GRF_SOC_CON6_GMAC_CLK_TX_DL_CFG); 203 syscon_write_4(rk_sc->sc_syscon, RK3399_GRF_SOC_CON6, 204 write_mask | write_val); 205 } 206 syscon_unlock(rk_sc->sc_syscon); 207 } 208 209 static void 210 rk3399_gmac_set_speed_rgmii(struct dwc_gmac_softc *sc, int speed) 211 { 212 struct rk_gmac_softc * const rk_sc = (struct rk_gmac_softc *)sc; 213 u_int clksel; 214 215 switch (speed) { 216 case IFM_10_T: 217 clksel = RK3399_GRF_SOC_CON5_GMAC_CLK_SEL_2_5M; 218 break; 219 case IFM_100_TX: 220 clksel = RK3399_GRF_SOC_CON5_GMAC_CLK_SEL_25M; 221 break; 222 default: 223 clksel = RK3399_GRF_SOC_CON5_GMAC_CLK_SEL_125M; 224 break; 225 } 226 227 const uint32_t con5_mask = 228 RK3399_GRF_SOC_CON5_GMAC_CLK_SEL << 16; 229 const uint32_t con5 = 230 __SHIFTIN(clksel, RK3399_GRF_SOC_CON5_GMAC_CLK_SEL); 231 232 syscon_lock(rk_sc->sc_syscon); 233 syscon_write_4(rk_sc->sc_syscon, RK3399_GRF_SOC_CON5, con5 | con5_mask); 234 syscon_unlock(rk_sc->sc_syscon); 235 } 236 237 static int 238 rk_gmac_reset(const int phandle) 239 { 240 struct fdtbus_gpio_pin *pin_reset; 241 const u_int *reset_delay_us; 242 bool reset_active_low; 243 int len; 244 245 if (!of_hasprop(phandle, "snps,reset-gpio")) 246 return 0; 247 248 pin_reset = fdtbus_gpio_acquire(phandle, "snps,reset-gpio", GPIO_PIN_OUTPUT); 249 if (pin_reset == NULL) 250 return ENOENT; 251 252 reset_delay_us = fdtbus_get_prop(phandle, "snps,reset-delays-us", &len); 253 if (reset_delay_us == NULL || len != 12) 254 return ENXIO; 255 256 reset_active_low = of_hasprop(phandle, "snps,reset-active-low"); 257 258 fdtbus_gpio_write_raw(pin_reset, reset_active_low ? 1 : 0); 259 delay(be32toh(reset_delay_us[0])); 260 fdtbus_gpio_write_raw(pin_reset, reset_active_low ? 0 : 1); 261 delay(be32toh(reset_delay_us[1])); 262 fdtbus_gpio_write_raw(pin_reset, reset_active_low ? 1 : 0); 263 delay(be32toh(reset_delay_us[2])); 264 265 return 0; 266 } 267 268 static int 269 rk_gmac_intr(void *arg) 270 { 271 return dwc_gmac_intr(arg); 272 } 273 274 static int 275 rk_gmac_setup_clocks(int phandle) 276 { 277 static const char * const clknames[] = { 278 #if 0 279 "stmmaceth", 280 "mac_clk_rx", 281 "mac_clk_tx", 282 "clk_mac_ref", 283 "clk_mac_refout", 284 "aclk_mac", 285 "pclk_mac" 286 #else 287 "stmmaceth", 288 "aclk_mac", 289 "pclk_mac", 290 "mac_clk_tx", 291 "mac_clk_rx" 292 #endif 293 }; 294 static const char * const rstnames[] = { 295 "stmmaceth" 296 }; 297 struct fdtbus_reset *rst; 298 struct clk *clk; 299 int error, n; 300 301 fdtbus_clock_assign(phandle); 302 303 for (n = 0; n < __arraycount(clknames); n++) { 304 clk = fdtbus_clock_get(phandle, clknames[n]); 305 if (clk == NULL) { 306 aprint_error(": couldn't get %s clock\n", clknames[n]); 307 return ENXIO; 308 } 309 error = clk_enable(clk); 310 if (error != 0) { 311 aprint_error(": couldn't enable %s clock: %d\n", 312 clknames[n], error); 313 return error; 314 } 315 } 316 317 for (n = 0; n < __arraycount(rstnames); n++) { 318 rst = fdtbus_reset_get(phandle, rstnames[n]); 319 if (rst == NULL) { 320 aprint_error(": couldn't get %s reset\n", rstnames[n]); 321 return ENXIO; 322 } 323 error = fdtbus_reset_deassert(rst); 324 if (error != 0) { 325 aprint_error(": couldn't de-assert %s reset: %d\n", 326 rstnames[n], error); 327 return error; 328 } 329 } 330 331 delay(5000); 332 333 return 0; 334 } 335 336 static int 337 rk_gmac_match(device_t parent, cfdata_t cf, void *aux) 338 { 339 struct fdt_attach_args * const faa = aux; 340 341 return of_match_compat_data(faa->faa_phandle, compat_data); 342 } 343 344 static void 345 rk_gmac_attach(device_t parent, device_t self, void *aux) 346 { 347 struct rk_gmac_softc * const rk_sc = device_private(self); 348 struct dwc_gmac_softc * const sc = &rk_sc->sc_base; 349 struct fdt_attach_args * const faa = aux; 350 const int phandle = faa->faa_phandle; 351 const char *phy_mode; 352 char intrstr[128]; 353 bus_addr_t addr; 354 bus_size_t size; 355 u_int tx_delay, rx_delay; 356 #ifdef notyet 357 bool set_delay = true; 358 #else 359 bool set_delay = false; 360 #endif 361 362 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 363 aprint_error(": couldn't get registers\n"); 364 return; 365 } 366 367 rk_sc->sc_type = of_search_compatible(phandle, compat_data)->value; 368 369 rk_sc->sc_syscon = fdtbus_syscon_acquire(phandle, "rockchip,grf"); 370 if (rk_sc->sc_syscon == NULL) { 371 aprint_error(": couldn't get grf syscon\n"); 372 return; 373 } 374 375 if (of_getprop_uint32(phandle, "tx_delay", &tx_delay) != 0) { 376 tx_delay = RK_GMAC_TXDLY_DEFAULT; 377 set_delay = false; 378 } 379 380 if (of_getprop_uint32(phandle, "rx_delay", &rx_delay) != 0) { 381 rx_delay = RK_GMAC_RXDLY_DEFAULT; 382 set_delay = false; 383 } 384 385 sc->sc_dev = self; 386 sc->sc_bst = faa->faa_bst; 387 if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) { 388 aprint_error(": couldn't map registers\n"); 389 return; 390 } 391 sc->sc_dmat = faa->faa_dmat; 392 393 if (!fdtbus_intr_str(phandle, 0, intrstr, sizeof(intrstr))) { 394 aprint_error(": failed to decode interrupt\n"); 395 return; 396 } 397 398 if (rk_gmac_setup_clocks(phandle) != 0) 399 return; 400 401 if (rk_gmac_reset(phandle) != 0) 402 aprint_error_dev(self, "PHY reset failed\n"); 403 404 /* Rock64 seems to need more time for the reset to complete */ 405 delay(100000); 406 407 #if notyet 408 if (of_hasprop(phandle, "snps,force_thresh_dma_mode")) 409 sc->sc_flags |= DWC_GMAC_FORCE_THRESH_DMA_MODE; 410 #endif 411 412 phy_mode = fdtbus_get_string(phandle, "phy-mode"); 413 if (phy_mode == NULL) { 414 aprint_error(": missing 'phy-mode' property\n"); 415 return; 416 } 417 418 switch (rk_sc->sc_type) { 419 case GMAC_RK3328: 420 if (strcmp(phy_mode, "rgmii") == 0) { 421 rk3328_gmac_set_mode_rgmii(sc, tx_delay, rx_delay, 422 set_delay); 423 424 sc->sc_set_speed = rk3328_gmac_set_speed_rgmii; 425 } else { 426 aprint_error(": unsupported phy-mode '%s'\n", phy_mode); 427 return; 428 } 429 break; 430 case GMAC_RK3399: 431 if (strcmp(phy_mode, "rgmii") == 0) { 432 rk3399_gmac_set_mode_rgmii(sc, tx_delay, rx_delay, 433 set_delay); 434 435 sc->sc_set_speed = rk3399_gmac_set_speed_rgmii; 436 } else { 437 aprint_error(": unsupported phy-mode '%s'\n", phy_mode); 438 return; 439 } 440 break; 441 } 442 443 aprint_naive("\n"); 444 aprint_normal(": GMAC\n"); 445 446 if (dwc_gmac_attach(sc, MII_PHY_ANY, GMAC_MII_CLK_150_250M_DIV102) != 0) 447 return; 448 449 if (fdtbus_intr_establish_xname(phandle, 0, IPL_NET, 450 DWCGMAC_FDT_INTR_MPSAFE, rk_gmac_intr, sc, 451 device_xname(self)) == NULL) { 452 aprint_error_dev(self, "failed to establish interrupt on %s\n", intrstr); 453 return; 454 } 455 aprint_normal_dev(self, "interrupting on %s\n", intrstr); 456 } 457 458 CFATTACH_DECL_NEW(rk_gmac, sizeof(struct rk_gmac_softc), 459 rk_gmac_match, rk_gmac_attach, NULL, NULL); 460
Indexes created Tue Sep 30 17:09:57 GMT 2025