rk_gmac.c revision 1.4
1 /* $NetBSD: rk_gmac.c,v 1.4 2018/06/30 16:28:14 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2018 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 17 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 31 __KERNEL_RCSID(0, "$NetBSD: rk_gmac.c,v 1.4 2018/06/30 16:28:14 jmcneill Exp $"); 32 33 #include <sys/param.h> 34 #include <sys/bus.h> 35 #include <sys/device.h> 36 #include <sys/intr.h> 37 #include <sys/systm.h> 38 #include <sys/gpio.h> 39 40 #include <net/if.h> 41 #include <net/if_ether.h> 42 #include <net/if_media.h> 43 44 #include <dev/mii/miivar.h> 45 46 #include <dev/ic/dwc_gmac_var.h> 47 #include <dev/ic/dwc_gmac_reg.h> 48 49 #include <dev/fdt/fdtvar.h> 50 51 #define RK3328_GRF_MAC_CON0 0x0900 52 #define RK3328_GRF_MAC_CON0_RXDLY __BITS(13,7) 53 #define RK3328_GRF_MAC_CON0_TXDLY __BITS(6,0) 54 55 #define RK3328_GRF_MAC_CON1 0x0904 56 #define RK3328_GRF_MAC_CON1_CLKSEL __BITS(12,11) 57 #define RK3328_GRF_MAC_CON1_CLKSEL_125M 0 58 #define RK3328_GRF_MAC_CON1_CLKSEL_2_5M 2 59 #define RK3328_GRF_MAC_CON1_CLKSEL_25M 3 60 #define RK3328_GRF_MAC_CON1_MODE __BIT(9) 61 #define RK3328_GRF_MAC_CON1_SEL __BITS(6,4) 62 #define RK3328_GRF_MAC_CON1_SEL_RGMII 1 63 #define RK3328_GRF_MAC_CON1_RXDLY_EN __BIT(1) 64 #define RK3328_GRF_MAC_CON1_TXDLY_EN __BIT(0) 65 66 #define RK_GMAC_TXDLY_DEFAULT 0x30 67 #define RK_GMAC_RXDLY_DEFAULT 0x10 68 69 static const char * compatible[] = { 70 "rockchip,rk3328-gmac", 71 NULL 72 }; 73 74 struct rk_gmac_softc { 75 struct dwc_gmac_softc sc_base; 76 bus_space_handle_t sc_grf_bsh; 77 }; 78 79 static int 80 rk_gmac_reset(const int phandle) 81 { 82 struct fdtbus_gpio_pin *pin_reset; 83 const u_int *reset_delay_us; 84 bool reset_active_low; 85 int len; 86 87 if (!of_hasprop(phandle, "snps,reset-gpio")) 88 return 0; 89 90 pin_reset = fdtbus_gpio_acquire(phandle, "snps,reset-gpio", GPIO_PIN_OUTPUT); 91 if (pin_reset == NULL) 92 return ENOENT; 93 94 reset_delay_us = fdtbus_get_prop(phandle, "snps,reset-delays-us", &len); 95 if (reset_delay_us == NULL || len != 12) 96 return ENXIO; 97 98 reset_active_low = of_hasprop(phandle, "snps,reset-active-low"); 99 100 fdtbus_gpio_write_raw(pin_reset, reset_active_low ? 1 : 0); 101 delay(be32toh(reset_delay_us[0])); 102 fdtbus_gpio_write_raw(pin_reset, reset_active_low ? 0 : 1); 103 delay(be32toh(reset_delay_us[1])); 104 fdtbus_gpio_write_raw(pin_reset, reset_active_low ? 1 : 0); 105 delay(be32toh(reset_delay_us[2])); 106 107 return 0; 108 } 109 110 static int 111 rk_gmac_intr(void *arg) 112 { 113 return dwc_gmac_intr(arg); 114 } 115 116 static void 117 rk3328_gmac_set_mode_rgmii(struct dwc_gmac_softc *sc, u_int tx_delay, u_int rx_delay) 118 { 119 struct rk_gmac_softc * const rk_sc = (struct rk_gmac_softc *)sc; 120 uint32_t write_mask, write_val; 121 122 write_mask = (RK3328_GRF_MAC_CON1_MODE | RK3328_GRF_MAC_CON1_SEL) << 16; 123 write_val = __SHIFTIN(RK3328_GRF_MAC_CON1_SEL_RGMII, RK3328_GRF_MAC_CON1_SEL); 124 bus_space_write_4(sc->sc_bst, rk_sc->sc_grf_bsh, RK3328_GRF_MAC_CON1, 125 write_mask | write_val); 126 127 #if notyet 128 write_mask = (RK3328_GRF_MAC_CON0_TXDLY | RK3328_GRF_MAC_CON0_RXDLY) << 16; 129 write_val = __SHIFTIN(tx_delay, RK3328_GRF_MAC_CON0_TXDLY) | 130 __SHIFTIN(rx_delay, RK3328_GRF_MAC_CON0_RXDLY); 131 bus_space_write_4(sc->sc_bst, rk_sc->sc_grf_bsh, RK3328_GRF_MAC_CON0, 132 write_mask | write_val); 133 134 write_mask = (RK3328_GRF_MAC_CON1_RXDLY_EN | RK3328_GRF_MAC_CON1_TXDLY_EN) << 16; 135 write_val = RK3328_GRF_MAC_CON1_RXDLY_EN | RK3328_GRF_MAC_CON1_TXDLY_EN; 136 bus_space_write_4(sc->sc_bst, rk_sc->sc_grf_bsh, RK3328_GRF_MAC_CON1, 137 write_mask | write_val); 138 #endif 139 } 140 141 static void 142 rk3328_gmac_set_speed_rgmii(struct dwc_gmac_softc *sc, int speed) 143 { 144 struct rk_gmac_softc * const rk_sc = (struct rk_gmac_softc *)sc; 145 u_int clksel; 146 147 switch (speed) { 148 case IFM_10_T: 149 clksel = RK3328_GRF_MAC_CON1_CLKSEL_2_5M; 150 break; 151 case IFM_100_TX: 152 clksel = RK3328_GRF_MAC_CON1_CLKSEL_25M; 153 break; 154 default: 155 clksel = RK3328_GRF_MAC_CON1_CLKSEL_125M; 156 break; 157 } 158 159 bus_space_write_4(sc->sc_bst, rk_sc->sc_grf_bsh, RK3328_GRF_MAC_CON1, 160 (RK3328_GRF_MAC_CON1_CLKSEL << 16) | 161 __SHIFTIN(RK3328_GRF_MAC_CON1_CLKSEL_125M, RK3328_GRF_MAC_CON1_CLKSEL)); 162 } 163 164 static int 165 rk_gmac_setup_clocks(int phandle) 166 { 167 static const char * const clknames[] = { 168 #if 0 169 "stmmaceth", 170 "mac_clk_rx", 171 "mac_clk_tx", 172 "clk_mac_ref", 173 "clk_mac_refout", 174 "aclk_mac", 175 "pclk_mac" 176 #else 177 "stmmaceth", 178 "aclk_mac", 179 "pclk_mac", 180 "mac_clk_tx", 181 "mac_clk_rx" 182 #endif 183 }; 184 static const char * const rstnames[] = { 185 "stmmaceth" 186 }; 187 struct fdtbus_reset *rst; 188 struct clk *clk; 189 int error, n; 190 191 fdtbus_clock_assign(phandle); 192 193 for (n = 0; n < __arraycount(clknames); n++) { 194 clk = fdtbus_clock_get(phandle, clknames[n]); 195 if (clk == NULL) { 196 aprint_error(": couldn't get %s clock\n", clknames[n]); 197 return ENXIO; 198 } 199 error = clk_enable(clk); 200 if (error != 0) { 201 aprint_error(": couldn't enable %s clock: %d\n", 202 clknames[n], error); 203 return error; 204 } 205 } 206 207 for (n = 0; n < __arraycount(rstnames); n++) { 208 rst = fdtbus_reset_get(phandle, rstnames[n]); 209 if (rst == NULL) { 210 aprint_error(": couldn't get %s reset\n", rstnames[n]); 211 return ENXIO; 212 } 213 error = fdtbus_reset_deassert(rst); 214 if (error != 0) { 215 aprint_error(": couldn't de-assert %s reset: %d\n", 216 rstnames[n], error); 217 return error; 218 } 219 } 220 221 delay(5000); 222 223 return 0; 224 } 225 226 static int 227 rk_gmac_match(device_t parent, cfdata_t cf, void *aux) 228 { 229 struct fdt_attach_args * const faa = aux; 230 231 return of_match_compatible(faa->faa_phandle, compatible); 232 } 233 234 static void 235 rk_gmac_attach(device_t parent, device_t self, void *aux) 236 { 237 struct rk_gmac_softc * const rk_sc = device_private(self); 238 struct dwc_gmac_softc * const sc = &rk_sc->sc_base; 239 struct fdt_attach_args * const faa = aux; 240 const int phandle = faa->faa_phandle; 241 const char *phy_mode; 242 char intrstr[128]; 243 bus_addr_t addr, grf_addr; 244 bus_size_t size, grf_size; 245 u_int tx_delay, rx_delay; 246 247 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 248 aprint_error(": couldn't get registers\n"); 249 return; 250 } 251 252 const int grf_phandle = fdtbus_get_phandle(phandle, "rockchip,grf"); 253 if (grf_phandle == -1) { 254 aprint_error(": couldn't get grf phandle\n"); 255 return; 256 } 257 if (fdtbus_get_reg(grf_phandle, 0, &grf_addr, &grf_size) != 0) { 258 aprint_error(": couldn't get grf registers\n"); 259 return; 260 } 261 if (bus_space_map(faa->faa_bst, grf_addr, grf_size, 0, &rk_sc->sc_grf_bsh) != 0) { 262 aprint_error(": couldn't map grf registers\n"); 263 return; 264 } 265 266 if (of_getprop_uint32(phandle, "tx_delay", &tx_delay) != 0) 267 tx_delay = RK_GMAC_TXDLY_DEFAULT; 268 269 if (of_getprop_uint32(phandle, "rx_delay", &rx_delay) != 0) 270 rx_delay = RK_GMAC_RXDLY_DEFAULT; 271 272 sc->sc_dev = self; 273 sc->sc_bst = faa->faa_bst; 274 if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) { 275 aprint_error(": couldn't map registers\n"); 276 return; 277 } 278 sc->sc_dmat = faa->faa_dmat; 279 280 if (!fdtbus_intr_str(phandle, 0, intrstr, sizeof(intrstr))) { 281 aprint_error(": failed to decode interrupt\n"); 282 return; 283 } 284 285 if (rk_gmac_setup_clocks(phandle) != 0) 286 return; 287 288 if (rk_gmac_reset(phandle) != 0) 289 aprint_error_dev(self, "PHY reset failed\n"); 290 291 #if notyet 292 if (of_hasprop(phandle, "snps,force_thresh_dma_mode")) 293 sc->sc_flags |= DWC_GMAC_FORCE_THRESH_DMA_MODE; 294 #endif 295 296 phy_mode = fdtbus_get_string(phandle, "phy-mode"); 297 if (phy_mode == NULL) { 298 aprint_error(": missing 'phy-mode' property\n"); 299 return; 300 } 301 302 if (strcmp(phy_mode, "rgmii") == 0) { 303 rk3328_gmac_set_mode_rgmii(sc, tx_delay, rx_delay); 304 305 sc->sc_set_speed = rk3328_gmac_set_speed_rgmii; 306 } else { 307 aprint_error(": unsupported phy-mode '%s'\n", phy_mode); 308 return; 309 } 310 311 aprint_naive("\n"); 312 aprint_normal(": GMAC\n"); 313 314 if (dwc_gmac_attach(sc, GMAC_MII_CLK_150_250M_DIV102) != 0) 315 return; 316 317 if (fdtbus_intr_establish(phandle, 0, IPL_NET, 0, rk_gmac_intr, sc) == NULL) { 318 aprint_error_dev(self, "failed to establish interrupt on %s\n", intrstr); 319 return; 320 } 321 aprint_normal_dev(self, "interrupting on %s\n", intrstr); 322 } 323 324 CFATTACH_DECL_NEW(rk_gmac, sizeof(struct rk_gmac_softc), 325 rk_gmac_match, rk_gmac_attach, NULL, NULL); 326
Indexes created Tue Sep 30 11:09:46 GMT 2025