rk_gmac.c revision 1.7
1 /* $NetBSD: rk_gmac.c,v 1.7 2018/07/16 23:11:47 christos Exp $ */ 2 3 /*- 4 * Copyright (c) 2018 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 17 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 31 __KERNEL_RCSID(0, "$NetBSD: rk_gmac.c,v 1.7 2018/07/16 23:11:47 christos Exp $"); 32 33 #include <sys/param.h> 34 #include <sys/bus.h> 35 #include <sys/device.h> 36 #include <sys/intr.h> 37 #include <sys/systm.h> 38 #include <sys/gpio.h> 39 40 #include <net/if.h> 41 #include <net/if_ether.h> 42 #include <net/if_media.h> 43 44 #include <dev/mii/miivar.h> 45 46 #include <dev/ic/dwc_gmac_var.h> 47 #include <dev/ic/dwc_gmac_reg.h> 48 49 #include <dev/fdt/fdtvar.h> 50 #include <dev/fdt/syscon.h> 51 52 #define RK3328_GRF_MAC_CON0 0x0900 53 #define RK3328_GRF_MAC_CON0_RXDLY __BITS(13,7) 54 #define RK3328_GRF_MAC_CON0_TXDLY __BITS(6,0) 55 56 #define RK3328_GRF_MAC_CON1 0x0904 57 #define RK3328_GRF_MAC_CON1_CLKSEL __BITS(12,11) 58 #define RK3328_GRF_MAC_CON1_CLKSEL_125M 0 59 #define RK3328_GRF_MAC_CON1_CLKSEL_2_5M 2 60 #define RK3328_GRF_MAC_CON1_CLKSEL_25M 3 61 #define RK3328_GRF_MAC_CON1_MODE __BIT(9) 62 #define RK3328_GRF_MAC_CON1_SEL __BITS(6,4) 63 #define RK3328_GRF_MAC_CON1_SEL_RGMII 1 64 #define RK3328_GRF_MAC_CON1_RXDLY_EN __BIT(1) 65 #define RK3328_GRF_MAC_CON1_TXDLY_EN __BIT(0) 66 67 #define RK_GMAC_TXDLY_DEFAULT 0x30 68 #define RK_GMAC_RXDLY_DEFAULT 0x10 69 70 static const char * compatible[] = { 71 "rockchip,rk3328-gmac", 72 NULL 73 }; 74 75 struct rk_gmac_softc { 76 struct dwc_gmac_softc sc_base; 77 struct syscon *sc_syscon; 78 }; 79 80 static int 81 rk_gmac_reset(const int phandle) 82 { 83 struct fdtbus_gpio_pin *pin_reset; 84 const u_int *reset_delay_us; 85 bool reset_active_low; 86 int len; 87 88 if (!of_hasprop(phandle, "snps,reset-gpio")) 89 return 0; 90 91 pin_reset = fdtbus_gpio_acquire(phandle, "snps,reset-gpio", GPIO_PIN_OUTPUT); 92 if (pin_reset == NULL) 93 return ENOENT; 94 95 reset_delay_us = fdtbus_get_prop(phandle, "snps,reset-delays-us", &len); 96 if (reset_delay_us == NULL || len != 12) 97 return ENXIO; 98 99 reset_active_low = of_hasprop(phandle, "snps,reset-active-low"); 100 101 fdtbus_gpio_write_raw(pin_reset, reset_active_low ? 1 : 0); 102 delay(be32toh(reset_delay_us[0])); 103 fdtbus_gpio_write_raw(pin_reset, reset_active_low ? 0 : 1); 104 delay(be32toh(reset_delay_us[1])); 105 fdtbus_gpio_write_raw(pin_reset, reset_active_low ? 1 : 0); 106 delay(be32toh(reset_delay_us[2])); 107 108 return 0; 109 } 110 111 static int 112 rk_gmac_intr(void *arg) 113 { 114 return dwc_gmac_intr(arg); 115 } 116 117 static void 118 rk3328_gmac_set_mode_rgmii(struct dwc_gmac_softc *sc, u_int tx_delay, u_int rx_delay) 119 { 120 struct rk_gmac_softc * const rk_sc = (struct rk_gmac_softc *)sc; 121 uint32_t write_mask, write_val; 122 123 syscon_lock(rk_sc->sc_syscon); 124 125 write_mask = (RK3328_GRF_MAC_CON1_MODE | RK3328_GRF_MAC_CON1_SEL) << 16; 126 write_val = __SHIFTIN(RK3328_GRF_MAC_CON1_SEL_RGMII, RK3328_GRF_MAC_CON1_SEL); 127 syscon_write_4(rk_sc->sc_syscon, RK3328_GRF_MAC_CON1, write_mask | write_val); 128 129 #if notyet 130 write_mask = (RK3328_GRF_MAC_CON0_TXDLY | RK3328_GRF_MAC_CON0_RXDLY) << 16; 131 write_val = __SHIFTIN(tx_delay, RK3328_GRF_MAC_CON0_TXDLY) | 132 __SHIFTIN(rx_delay, RK3328_GRF_MAC_CON0_RXDLY); 133 syscon_write_4(rk_sc->sc_syscon, RK3328_GRF_MAC_CON0, write_mask | write_val); 134 135 write_mask = (RK3328_GRF_MAC_CON1_RXDLY_EN | RK3328_GRF_MAC_CON1_TXDLY_EN) << 16; 136 write_val = RK3328_GRF_MAC_CON1_RXDLY_EN | RK3328_GRF_MAC_CON1_TXDLY_EN; 137 syscon_write_4(rk_sc->sc_syscon, RK3328_GRF_MAC_CON1, write_mask | write_val); 138 #endif 139 140 syscon_unlock(rk_sc->sc_syscon); 141 } 142 143 static void 144 rk3328_gmac_set_speed_rgmii(struct dwc_gmac_softc *sc, int speed) 145 { 146 struct rk_gmac_softc * const rk_sc = (struct rk_gmac_softc *)sc; 147 #if 0 148 u_int clksel; 149 150 switch (speed) { 151 case IFM_10_T: 152 clksel = RK3328_GRF_MAC_CON1_CLKSEL_2_5M; 153 break; 154 case IFM_100_TX: 155 clksel = RK3328_GRF_MAC_CON1_CLKSEL_25M; 156 break; 157 default: 158 clksel = RK3328_GRF_MAC_CON1_CLKSEL_125M; 159 break; 160 } 161 #endif 162 163 syscon_lock(rk_sc->sc_syscon); 164 syscon_write_4(rk_sc->sc_syscon, RK3328_GRF_MAC_CON1, 165 (RK3328_GRF_MAC_CON1_CLKSEL << 16) | 166 __SHIFTIN(RK3328_GRF_MAC_CON1_CLKSEL_125M, RK3328_GRF_MAC_CON1_CLKSEL)); 167 syscon_unlock(rk_sc->sc_syscon); 168 } 169 170 static int 171 rk_gmac_setup_clocks(int phandle) 172 { 173 static const char * const clknames[] = { 174 #if 0 175 "stmmaceth", 176 "mac_clk_rx", 177 "mac_clk_tx", 178 "clk_mac_ref", 179 "clk_mac_refout", 180 "aclk_mac", 181 "pclk_mac" 182 #else 183 "stmmaceth", 184 "aclk_mac", 185 "pclk_mac", 186 "mac_clk_tx", 187 "mac_clk_rx" 188 #endif 189 }; 190 static const char * const rstnames[] = { 191 "stmmaceth" 192 }; 193 struct fdtbus_reset *rst; 194 struct clk *clk; 195 int error, n; 196 197 fdtbus_clock_assign(phandle); 198 199 for (n = 0; n < __arraycount(clknames); n++) { 200 clk = fdtbus_clock_get(phandle, clknames[n]); 201 if (clk == NULL) { 202 aprint_error(": couldn't get %s clock\n", clknames[n]); 203 return ENXIO; 204 } 205 error = clk_enable(clk); 206 if (error != 0) { 207 aprint_error(": couldn't enable %s clock: %d\n", 208 clknames[n], error); 209 return error; 210 } 211 } 212 213 for (n = 0; n < __arraycount(rstnames); n++) { 214 rst = fdtbus_reset_get(phandle, rstnames[n]); 215 if (rst == NULL) { 216 aprint_error(": couldn't get %s reset\n", rstnames[n]); 217 return ENXIO; 218 } 219 error = fdtbus_reset_deassert(rst); 220 if (error != 0) { 221 aprint_error(": couldn't de-assert %s reset: %d\n", 222 rstnames[n], error); 223 return error; 224 } 225 } 226 227 delay(5000); 228 229 return 0; 230 } 231 232 static int 233 rk_gmac_match(device_t parent, cfdata_t cf, void *aux) 234 { 235 struct fdt_attach_args * const faa = aux; 236 237 return of_match_compatible(faa->faa_phandle, compatible); 238 } 239 240 static void 241 rk_gmac_attach(device_t parent, device_t self, void *aux) 242 { 243 struct rk_gmac_softc * const rk_sc = device_private(self); 244 struct dwc_gmac_softc * const sc = &rk_sc->sc_base; 245 struct fdt_attach_args * const faa = aux; 246 const int phandle = faa->faa_phandle; 247 const char *phy_mode; 248 char intrstr[128]; 249 bus_addr_t addr; 250 bus_size_t size; 251 u_int tx_delay, rx_delay; 252 253 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 254 aprint_error(": couldn't get registers\n"); 255 return; 256 } 257 258 rk_sc->sc_syscon = fdtbus_syscon_acquire(phandle, "rockchip,grf"); 259 if (rk_sc->sc_syscon == NULL) { 260 aprint_error(": couldn't get grf syscon\n"); 261 return; 262 } 263 264 if (of_getprop_uint32(phandle, "tx_delay", &tx_delay) != 0) 265 tx_delay = RK_GMAC_TXDLY_DEFAULT; 266 267 if (of_getprop_uint32(phandle, "rx_delay", &rx_delay) != 0) 268 rx_delay = RK_GMAC_RXDLY_DEFAULT; 269 270 sc->sc_dev = self; 271 sc->sc_bst = faa->faa_bst; 272 if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) { 273 aprint_error(": couldn't map registers\n"); 274 return; 275 } 276 sc->sc_dmat = faa->faa_dmat; 277 278 if (!fdtbus_intr_str(phandle, 0, intrstr, sizeof(intrstr))) { 279 aprint_error(": failed to decode interrupt\n"); 280 return; 281 } 282 283 if (rk_gmac_setup_clocks(phandle) != 0) 284 return; 285 286 if (rk_gmac_reset(phandle) != 0) 287 aprint_error_dev(self, "PHY reset failed\n"); 288 289 /* Rock64 seems to need more time for the reset to complete */ 290 delay(100000); 291 292 #if notyet 293 if (of_hasprop(phandle, "snps,force_thresh_dma_mode")) 294 sc->sc_flags |= DWC_GMAC_FORCE_THRESH_DMA_MODE; 295 #endif 296 297 phy_mode = fdtbus_get_string(phandle, "phy-mode"); 298 if (phy_mode == NULL) { 299 aprint_error(": missing 'phy-mode' property\n"); 300 return; 301 } 302 303 if (strcmp(phy_mode, "rgmii") == 0) { 304 rk3328_gmac_set_mode_rgmii(sc, tx_delay, rx_delay); 305 306 sc->sc_set_speed = rk3328_gmac_set_speed_rgmii; 307 } else { 308 aprint_error(": unsupported phy-mode '%s'\n", phy_mode); 309 return; 310 } 311 312 aprint_naive("\n"); 313 aprint_normal(": GMAC\n"); 314 315 if (dwc_gmac_attach(sc, GMAC_MII_CLK_150_250M_DIV102) != 0) 316 return; 317 318 if (fdtbus_intr_establish(phandle, 0, IPL_NET, 0, rk_gmac_intr, sc) == NULL) { 319 aprint_error_dev(self, "failed to establish interrupt on %s\n", intrstr); 320 return; 321 } 322 aprint_normal_dev(self, "interrupting on %s\n", intrstr); 323 } 324 325 CFATTACH_DECL_NEW(rk_gmac, sizeof(struct rk_gmac_softc), 326 rk_gmac_match, rk_gmac_attach, NULL, NULL); 327
Indexes created Tue Sep 30 11:09:46 GMT 2025