rk_gpio.c revision 1.4.8.1
1 /* $NetBSD: rk_gpio.c,v 1.4.8.1 2021/08/04 16:51:28 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2018 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: rk_gpio.c,v 1.4.8.1 2021/08/04 16:51:28 thorpej Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/bus.h> 34 #include <sys/device.h> 35 #include <sys/intr.h> 36 #include <sys/systm.h> 37 #include <sys/mutex.h> 38 #include <sys/kmem.h> 39 #include <sys/gpio.h> 40 #include <sys/bitops.h> 41 #include <sys/lwp.h> 42 43 #include <dev/fdt/fdtvar.h> 44 #include <dev/gpio/gpiovar.h> 45 46 #define GPIO_SWPORTA_DR_REG 0x0000 47 #define GPIO_SWPORTA_DDR_REG 0x0004 48 #define GPIO_INTEN_REG 0x0030 49 #define GPIO_INTMASK_REG 0x0034 50 #define GPIO_INTTYPE_LEVEL_REG 0x0038 51 #define GPIO_INT_POLARITY_REG 0x003c 52 #define GPIO_INT_STATUS_REG 0x0040 53 #define GPIO_INT_RAWSTATUS_REG 0x0044 54 #define GPIO_DEBOUNCE_REG 0x0048 55 #define GPIO_PORTA_EOI_REG 0x004c 56 #define GPIO_EXT_PORTA_REG 0x0050 57 #define GPIO_LS_SYNC_REG 0x0060 58 59 static const struct device_compatible_entry compat_data[] = { 60 { .compat = "rockchip,gpio-bank" }, 61 DEVICE_COMPAT_EOL 62 }; 63 64 struct rk_gpio_softc { 65 device_t sc_dev; 66 bus_space_tag_t sc_bst; 67 bus_space_handle_t sc_bsh; 68 kmutex_t sc_lock; 69 70 struct gpio_chipset_tag sc_gp; 71 gpio_pin_t sc_pins[32]; 72 device_t sc_gpiodev; 73 }; 74 75 struct rk_gpio_pin { 76 struct rk_gpio_softc *pin_sc; 77 u_int pin_nr; 78 int pin_flags; 79 bool pin_actlo; 80 }; 81 82 #define RD4(sc, reg) \ 83 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg)) 84 #define WR4(sc, reg, val) \ 85 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)) 86 87 static int rk_gpio_match(device_t, cfdata_t, void *); 88 static void rk_gpio_attach(device_t, device_t, void *); 89 90 CFATTACH_DECL_NEW(rk_gpio, sizeof(struct rk_gpio_softc), 91 rk_gpio_match, rk_gpio_attach, NULL, NULL); 92 93 static int 94 rk_gpio_ctl(struct rk_gpio_softc *sc, u_int pin, int flags) 95 { 96 uint32_t ddr; 97 98 KASSERT(mutex_owned(&sc->sc_lock)); 99 100 ddr = RD4(sc, GPIO_SWPORTA_DDR_REG); 101 if (flags & GPIO_PIN_INPUT) 102 ddr &= ~__BIT(pin); 103 else if (flags & GPIO_PIN_OUTPUT) 104 ddr |= __BIT(pin); 105 WR4(sc, GPIO_SWPORTA_DDR_REG, ddr); 106 107 return 0; 108 } 109 110 static void * 111 rk_gpio_acquire(device_t dev, const void *data, size_t len, int flags) 112 { 113 struct rk_gpio_softc * const sc = device_private(dev); 114 struct rk_gpio_pin *gpin; 115 const u_int *gpio = data; 116 int error; 117 118 if (len != 12) 119 return NULL; 120 121 const uint8_t pin = be32toh(gpio[1]) & 0xff; 122 const bool actlo = be32toh(gpio[2]) & 1; 123 124 if (pin >= __arraycount(sc->sc_pins)) 125 return NULL; 126 127 mutex_enter(&sc->sc_lock); 128 error = rk_gpio_ctl(sc, pin, flags); 129 mutex_exit(&sc->sc_lock); 130 131 if (error != 0) 132 return NULL; 133 134 gpin = kmem_zalloc(sizeof(*gpin), KM_SLEEP); 135 gpin->pin_sc = sc; 136 gpin->pin_nr = pin; 137 gpin->pin_flags = flags; 138 gpin->pin_actlo = actlo; 139 140 return gpin; 141 } 142 143 static void 144 rk_gpio_release(device_t dev, void *priv) 145 { 146 struct rk_gpio_softc * const sc = device_private(dev); 147 struct rk_gpio_pin *pin = priv; 148 149 mutex_enter(&sc->sc_lock); 150 rk_gpio_ctl(pin->pin_sc, pin->pin_nr, GPIO_PIN_INPUT); 151 mutex_exit(&sc->sc_lock); 152 153 kmem_free(pin, sizeof(*pin)); 154 } 155 156 static int 157 rk_gpio_read(device_t dev, void *priv, bool raw) 158 { 159 struct rk_gpio_softc * const sc = device_private(dev); 160 struct rk_gpio_pin *pin = priv; 161 uint32_t data; 162 int val; 163 164 KASSERT(sc == pin->pin_sc); 165 166 const uint32_t data_mask = __BIT(pin->pin_nr); 167 168 /* No lock required for reads */ 169 data = RD4(sc, GPIO_EXT_PORTA_REG); 170 val = __SHIFTOUT(data, data_mask); 171 if (!raw && pin->pin_actlo) 172 val = !val; 173 174 return val; 175 } 176 177 static void 178 rk_gpio_write(device_t dev, void *priv, int val, bool raw) 179 { 180 struct rk_gpio_softc * const sc = device_private(dev); 181 struct rk_gpio_pin *pin = priv; 182 uint32_t data; 183 184 KASSERT(sc == pin->pin_sc); 185 186 const uint32_t data_mask = __BIT(pin->pin_nr); 187 188 if (!raw && pin->pin_actlo) 189 val = !val; 190 191 mutex_enter(&sc->sc_lock); 192 data = RD4(sc, GPIO_SWPORTA_DR_REG); 193 if (val) 194 data |= data_mask; 195 else 196 data &= ~data_mask; 197 WR4(sc, GPIO_SWPORTA_DR_REG, data); 198 mutex_exit(&sc->sc_lock); 199 } 200 201 static struct fdtbus_gpio_controller_func rk_gpio_funcs = { 202 .acquire = rk_gpio_acquire, 203 .release = rk_gpio_release, 204 .read = rk_gpio_read, 205 .write = rk_gpio_write, 206 }; 207 208 static int 209 rk_gpio_pin_read(void *priv, int pin) 210 { 211 struct rk_gpio_softc * const sc = priv; 212 uint32_t data; 213 int val; 214 215 KASSERT(pin < __arraycount(sc->sc_pins)); 216 217 const uint32_t data_mask = __BIT(pin); 218 219 /* No lock required for reads */ 220 data = RD4(sc, GPIO_EXT_PORTA_REG); 221 val = __SHIFTOUT(data, data_mask); 222 223 return val; 224 } 225 226 static void 227 rk_gpio_pin_write(void *priv, int pin, int val) 228 { 229 struct rk_gpio_softc * const sc = priv; 230 uint32_t data; 231 232 KASSERT(pin < __arraycount(sc->sc_pins)); 233 234 const uint32_t data_mask = __BIT(pin); 235 236 mutex_enter(&sc->sc_lock); 237 data = RD4(sc, GPIO_SWPORTA_DR_REG); 238 if (val) 239 data |= data_mask; 240 else 241 data &= ~data_mask; 242 WR4(sc, GPIO_SWPORTA_DR_REG, data); 243 mutex_exit(&sc->sc_lock); 244 } 245 246 static void 247 rk_gpio_pin_ctl(void *priv, int pin, int flags) 248 { 249 struct rk_gpio_softc * const sc = priv; 250 251 KASSERT(pin < __arraycount(sc->sc_pins)); 252 253 mutex_enter(&sc->sc_lock); 254 rk_gpio_ctl(sc, pin, flags); 255 mutex_exit(&sc->sc_lock); 256 } 257 258 static void 259 rk_gpio_attach_ports(struct rk_gpio_softc *sc) 260 { 261 struct gpio_chipset_tag *gp = &sc->sc_gp; 262 struct gpiobus_attach_args gba; 263 u_int pin; 264 265 gp->gp_cookie = sc; 266 gp->gp_pin_read = rk_gpio_pin_read; 267 gp->gp_pin_write = rk_gpio_pin_write; 268 gp->gp_pin_ctl = rk_gpio_pin_ctl; 269 270 for (pin = 0; pin < __arraycount(sc->sc_pins); pin++) { 271 sc->sc_pins[pin].pin_num = pin; 272 sc->sc_pins[pin].pin_caps = GPIO_PIN_INPUT | GPIO_PIN_OUTPUT; 273 sc->sc_pins[pin].pin_state = rk_gpio_pin_read(sc, pin); 274 } 275 276 memset(&gba, 0, sizeof(gba)); 277 gba.gba_gc = gp; 278 gba.gba_pins = sc->sc_pins; 279 gba.gba_npins = __arraycount(sc->sc_pins); 280 sc->sc_gpiodev = config_found(sc->sc_dev, &gba, NULL, CFARGS_NONE); 281 } 282 283 static int 284 rk_gpio_match(device_t parent, cfdata_t cf, void *aux) 285 { 286 struct fdt_attach_args * const faa = aux; 287 288 return of_compatible_match(faa->faa_phandle, compat_data); 289 } 290 291 static void 292 rk_gpio_attach(device_t parent, device_t self, void *aux) 293 { 294 struct rk_gpio_softc * const sc = device_private(self); 295 struct fdt_attach_args * const faa = aux; 296 const int phandle = faa->faa_phandle; 297 struct clk *clk; 298 bus_addr_t addr; 299 bus_size_t size; 300 301 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 302 aprint_error(": couldn't get registers\n"); 303 return; 304 } 305 306 if ((clk = fdtbus_clock_get_index(phandle, 0)) == NULL || clk_enable(clk) != 0) { 307 aprint_error(": couldn't enable clock\n"); 308 return; 309 } 310 311 sc->sc_dev = self; 312 sc->sc_bst = faa->faa_bst; 313 if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) { 314 aprint_error(": couldn't map registers\n"); 315 return; 316 } 317 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_VM); 318 319 aprint_naive("\n"); 320 aprint_normal(": GPIO (%s)\n", fdtbus_get_string(phandle, "name")); 321 322 fdtbus_register_gpio_controller(self, phandle, &rk_gpio_funcs); 323 324 rk_gpio_attach_ports(sc); 325 } 326
Indexes created Thu Oct 02 14:10:14 GMT 2025