rk_i2c.c revision 1.10
1 /* $NetBSD: rk_i2c.c,v 1.10 2021/01/27 03:10:19 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2018 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 17 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 31 __KERNEL_RCSID(0, "$NetBSD: rk_i2c.c,v 1.10 2021/01/27 03:10:19 thorpej Exp $"); 32 33 #include <sys/param.h> 34 #include <sys/bus.h> 35 #include <sys/device.h> 36 #include <sys/intr.h> 37 #include <sys/systm.h> 38 #include <sys/time.h> 39 #include <sys/kmem.h> 40 41 #include <dev/i2c/i2cvar.h> 42 43 #include <dev/fdt/fdtvar.h> 44 45 #define RKI2C_CON 0x000 46 #define RKI2C_CON_ACT2NAK __BIT(6) 47 #define RKI2C_CON_ACK __BIT(5) 48 #define RKI2C_CON_STOP __BIT(4) 49 #define RKI2C_CON_START __BIT(3) 50 #define RKI2C_CON_I2C_MODE __BITS(2,1) 51 #define RKI2C_CON_I2C_MODE_TX 0 52 #define RKI2C_CON_I2C_MODE_RTX 1 53 #define RKI2C_CON_I2C_MODE_RX 2 54 #define RKI2C_CON_I2C_MODE_RRX 3 55 #define RKI2C_CON_I2C_EN __BIT(0) 56 57 #define RKI2C_CLKDIV 0x004 58 #define RKI2C_CLKDIV_CLKDIVH __BITS(31,16) 59 #define RKI2C_CLKDIV_CLKDIVL __BITS(15,0) 60 61 #define RKI2C_MRXADDR 0x008 62 #define RKI2C_MRXADDR_ADDHVLD __BIT(26) 63 #define RKI2C_MRXADDR_ADDMVLD __BIT(25) 64 #define RKI2C_MRXADDR_ADDLVLD __BIT(24) 65 #define RKI2C_MRXADDR_SADDR __BITS(23,0) 66 67 #define RKI2C_MRXRADDR 0x00c 68 #define RKI2C_MRXRADDR_ADDHVLD __BIT(26) 69 #define RKI2C_MRXRADDR_ADDMVLD __BIT(25) 70 #define RKI2C_MRXRADDR_ADDLVLD __BIT(24) 71 #define RKI2C_MRXRADDR_SADDR __BITS(23,0) 72 73 #define RKI2C_MTXCNT 0x010 74 #define RKI2C_MTXCNT_MTXCNT __BITS(5,0) 75 76 #define RKI2C_MRXCNT 0x014 77 #define RKI2C_MRXCNT_MRXCNT __BITS(5,0) 78 79 #define RKI2C_IEN 0x018 80 #define RKI2C_IEN_NAKRCVIEN __BIT(6) 81 #define RKI2C_IEN_STOPIEN __BIT(5) 82 #define RKI2C_IEN_STARTIEN __BIT(4) 83 #define RKI2C_IEN_MBRFIEN __BIT(3) 84 #define RKI2C_IEN_MBTFIEN __BIT(2) 85 #define RKI2C_IEN_BRFIEN __BIT(1) 86 #define RKI2C_IEN_BTFIEN __BIT(0) 87 88 #define RKI2C_IPD 0x01c 89 #define RKI2C_IPD_NAKRCVIPD __BIT(6) 90 #define RKI2C_IPD_STOPIPD __BIT(5) 91 #define RKI2C_IPD_STARTIPD __BIT(4) 92 #define RKI2C_IPD_MBRFIPD __BIT(3) 93 #define RKI2C_IPD_MBTFIPD __BIT(2) 94 #define RKI2C_IPD_BRFIPD __BIT(1) 95 #define RKI2C_IPD_BTFIPD __BIT(0) 96 97 #define RKI2C_FCNT 0x020 98 #define RKI2C_FCNT_FCNT __BITS(5,0) 99 100 #define RKI2C_TXDATA(n) (0x100 + (n) * 4) 101 #define RKI2C_RXDATA(n) (0x200 + (n) * 4) 102 103 static const struct device_compatible_entry compat_data[] = { 104 { .compat = "rockchip,rk3399-i2c" }, 105 DEVICE_COMPAT_EOL 106 }; 107 108 struct rk_i2c_softc { 109 device_t sc_dev; 110 bus_space_tag_t sc_bst; 111 bus_space_handle_t sc_bsh; 112 struct clk *sc_sclk; 113 struct clk *sc_pclk; 114 115 u_int sc_clkfreq; 116 117 struct i2c_controller sc_ic; 118 }; 119 120 #define RD4(sc, reg) \ 121 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg)) 122 #define WR4(sc, reg, val) \ 123 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)) 124 125 static void 126 rk_i2c_init(struct rk_i2c_softc *sc) 127 { 128 int div, divl, divh; 129 u_int rate; 130 131 /* 132 * SCL frequency is calculated by the following formula: 133 * 134 * SCL Divisor = 8 * (CLKDIVL + 1 + CLKDIVH + 1) 135 * SCL = PCLK / SCLK Divisor 136 */ 137 138 rate = clk_get_rate(sc->sc_sclk); 139 div = howmany(rate, sc->sc_clkfreq * 8) - 2; 140 if (div >= 0) { 141 divl = div / 2; 142 if (div % 2 == 0) 143 divh = divl; 144 else 145 divh = howmany(div, 2); 146 } else { 147 divl = divh = 0; 148 } 149 150 WR4(sc, RKI2C_CLKDIV, 151 __SHIFTIN(divh, RKI2C_CLKDIV_CLKDIVH) | 152 __SHIFTIN(divl, RKI2C_CLKDIV_CLKDIVL)); 153 154 /* 155 * Disable the module until we are ready to use it. 156 */ 157 WR4(sc, RKI2C_CON, 0); 158 WR4(sc, RKI2C_IEN, 0); 159 WR4(sc, RKI2C_IPD, RD4(sc, RKI2C_IPD)); 160 } 161 162 static int 163 rk_i2c_wait(struct rk_i2c_softc *sc, uint32_t mask) 164 { 165 u_int timeo = 100000; 166 uint32_t val; 167 168 const uint32_t ipdmask = mask | RKI2C_IPD_NAKRCVIPD; 169 do { 170 val = RD4(sc, RKI2C_IPD); 171 if (val & ipdmask) 172 break; 173 delay(1); 174 } while (--timeo > 0); 175 176 WR4(sc, RKI2C_IPD, val & ipdmask); 177 178 if ((val & RKI2C_IPD_NAKRCVIPD) != 0) 179 return EIO; 180 if ((val & mask) != 0) 181 return 0; 182 183 return ETIMEDOUT; 184 } 185 186 static int 187 rk_i2c_start(struct rk_i2c_softc *sc) 188 { 189 uint32_t con; 190 int error; 191 192 /* Send start */ 193 con = RD4(sc, RKI2C_CON); 194 con |= RKI2C_CON_START; 195 WR4(sc, RKI2C_CON, con); 196 197 if ((error = rk_i2c_wait(sc, RKI2C_IPD_STARTIPD)) != 0) 198 return error; 199 200 con &= ~RKI2C_CON_START; 201 WR4(sc, RKI2C_CON, con); 202 203 return 0; 204 } 205 206 static int 207 rk_i2c_stop(struct rk_i2c_softc *sc) 208 { 209 uint32_t con; 210 int error; 211 212 /* Send start */ 213 con = RD4(sc, RKI2C_CON); 214 con |= RKI2C_CON_STOP; 215 WR4(sc, RKI2C_CON, con); 216 217 if ((error = rk_i2c_wait(sc, RKI2C_IPD_STOPIPD)) != 0) 218 return error; 219 220 con &= ~RKI2C_CON_STOP; 221 WR4(sc, RKI2C_CON, con); 222 223 return 0; 224 } 225 226 static int 227 rk_i2c_write(struct rk_i2c_softc *sc, i2c_addr_t addr, const uint8_t *cmd, 228 size_t cmdlen, const uint8_t *buf, size_t buflen, int flags, bool send_start) 229 { 230 union { 231 uint8_t data8[32]; 232 uint32_t data32[8]; 233 } txdata; 234 uint32_t con; 235 u_int mode; 236 int error; 237 size_t len; 238 239 len = cmdlen + buflen; 240 if (len > 31) 241 return EINVAL; 242 243 mode = RKI2C_CON_I2C_MODE_TX; 244 con = RKI2C_CON_I2C_EN | __SHIFTIN(mode, RKI2C_CON_I2C_MODE); 245 WR4(sc, RKI2C_CON, con); 246 247 if (send_start && (error = rk_i2c_start(sc)) != 0) 248 return error; 249 250 /* Transmit data. Slave address goes in the lower 8 bits of TXDATA0 */ 251 txdata.data8[0] = addr << 1; 252 memcpy(&txdata.data8[1], cmd, cmdlen); 253 memcpy(&txdata.data8[1 + cmdlen], buf, buflen); 254 #if _BYTE_ORDER == _BIG_ENDIAN 255 for (int i = 0; i < howmany(len + 1, 4); i++) 256 LE32TOH(txdata.data32[i]); 257 #endif 258 bus_space_write_region_4(sc->sc_bst, sc->sc_bsh, RKI2C_TXDATA(0), 259 txdata.data32, howmany(len + 1, 4)); 260 WR4(sc, RKI2C_MTXCNT, __SHIFTIN(len + 1, RKI2C_MTXCNT_MTXCNT)); 261 262 if ((error = rk_i2c_wait(sc, RKI2C_IPD_MBTFIPD)) != 0) 263 return error; 264 265 return 0; 266 } 267 268 static int 269 rk_i2c_read(struct rk_i2c_softc *sc, i2c_addr_t addr, 270 const uint8_t *cmd, size_t cmdlen, uint8_t *buf, 271 size_t buflen, int flags, bool send_start, bool last_ack) 272 { 273 uint32_t rxdata[8]; 274 uint32_t con, mrxaddr, mrxraddr; 275 u_int mode; 276 int error, n; 277 278 if (buflen > 32) 279 return EINVAL; 280 if (cmdlen > 3) 281 return EINVAL; 282 283 mode = send_start ? RKI2C_CON_I2C_MODE_RTX : RKI2C_CON_I2C_MODE_RX; 284 con = RKI2C_CON_I2C_EN | __SHIFTIN(mode, RKI2C_CON_I2C_MODE); 285 WR4(sc, RKI2C_CON, con); 286 287 if (send_start && (error = rk_i2c_start(sc)) != 0) 288 return error; 289 290 if (send_start) { 291 mrxaddr = __SHIFTIN((addr << 1) | 1, RKI2C_MRXADDR_SADDR) | 292 RKI2C_MRXADDR_ADDLVLD; 293 WR4(sc, RKI2C_MRXADDR, mrxaddr); 294 for (n = 0, mrxraddr = 0; n < cmdlen; n++) { 295 mrxraddr |= cmd[n] << (n * 8); 296 mrxraddr |= (RKI2C_MRXRADDR_ADDLVLD << n); 297 } 298 WR4(sc, RKI2C_MRXRADDR, mrxraddr); 299 } 300 301 if (last_ack) { 302 con |= RKI2C_CON_ACK; 303 } 304 WR4(sc, RKI2C_CON, con); 305 306 /* Receive data. Slave address goes in the lower 8 bits of MRXADDR */ 307 WR4(sc, RKI2C_MRXCNT, __SHIFTIN(buflen, RKI2C_MRXCNT_MRXCNT)); 308 if ((error = rk_i2c_wait(sc, RKI2C_IPD_MBRFIPD)) != 0) 309 return error; 310 311 #if 0 312 bus_space_read_region_4(sc->sc_bst, sc->sc_bsh, RKI2C_RXDATA(0), 313 rxdata, howmany(buflen, 4)); 314 #else 315 for (n = 0; n < roundup(buflen, 4); n += 4) 316 rxdata[n/4] = RD4(sc, RKI2C_RXDATA(n/4)); 317 #endif 318 319 #if _BYTE_ORDER == _BIG_ENDIAN 320 for (int i = 0; i < howmany(buflen, 4); i++) 321 HTOLE32(rxdata[i]); 322 #endif 323 324 memcpy(buf, rxdata, buflen); 325 326 return 0; 327 } 328 329 static int 330 rk_i2c_exec(void *priv, i2c_op_t op, i2c_addr_t addr, 331 const void *cmdbuf, size_t cmdlen, void *buf, size_t buflen, int flags) 332 { 333 struct rk_i2c_softc * const sc = priv; 334 bool send_start = true; 335 int error; 336 337 if (I2C_OP_READ_P(op)) { 338 uint8_t *databuf = buf; 339 while (buflen > 0) { 340 const size_t datalen = uimin(buflen, 32); 341 const bool last_ack = datalen == buflen; 342 error = rk_i2c_read(sc, addr, cmdbuf, cmdlen, databuf, datalen, flags, send_start, last_ack); 343 if (error != 0) 344 break; 345 databuf += datalen; 346 buflen -= datalen; 347 send_start = false; 348 cmdbuf = NULL; 349 cmdlen = 0; 350 } 351 } else { 352 error = rk_i2c_write(sc, addr, cmdbuf, cmdlen, buf, buflen, flags, send_start); 353 } 354 355 if (error != 0 || I2C_OP_STOP_P(op)) 356 rk_i2c_stop(sc); 357 358 WR4(sc, RKI2C_CON, 0); 359 WR4(sc, RKI2C_IPD, RD4(sc, RKI2C_IPD)); 360 361 return error; 362 } 363 364 static int 365 rk_i2c_match(device_t parent, cfdata_t cf, void *aux) 366 { 367 struct fdt_attach_args * const faa = aux; 368 369 return of_compatible_match(faa->faa_phandle, compat_data); 370 } 371 372 static void 373 rk_i2c_attach(device_t parent, device_t self, void *aux) 374 { 375 struct rk_i2c_softc * const sc = device_private(self); 376 struct fdt_attach_args * const faa = aux; 377 const int phandle = faa->faa_phandle; 378 bus_addr_t addr; 379 bus_size_t size; 380 381 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 382 aprint_error(": couldn't get registers\n"); 383 return; 384 } 385 386 sc->sc_sclk = fdtbus_clock_get(phandle, "i2c"); 387 if (sc->sc_sclk == NULL || clk_enable(sc->sc_sclk) != 0) { 388 aprint_error(": couldn't enable sclk\n"); 389 return; 390 } 391 392 sc->sc_pclk = fdtbus_clock_get(phandle, "pclk"); 393 if (sc->sc_pclk == NULL || clk_enable(sc->sc_pclk) != 0) { 394 aprint_error(": couldn't enable pclk\n"); 395 return; 396 } 397 398 if (of_getprop_uint32(phandle, "clock-frequency", &sc->sc_clkfreq)) 399 sc->sc_clkfreq = 100000; 400 401 sc->sc_dev = self; 402 sc->sc_bst = faa->faa_bst; 403 if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) { 404 aprint_error(": couldn't map registers\n"); 405 return; 406 } 407 408 aprint_naive("\n"); 409 aprint_normal(": Rockchip I2C (%u Hz)\n", sc->sc_clkfreq); 410 411 fdtbus_clock_assign(phandle); 412 413 rk_i2c_init(sc); 414 415 iic_tag_init(&sc->sc_ic); 416 sc->sc_ic.ic_cookie = sc; 417 sc->sc_ic.ic_exec = rk_i2c_exec; 418 419 fdtbus_register_i2c_controller(&sc->sc_ic, phandle); 420 421 fdtbus_attach_i2cbus(self, phandle, &sc->sc_ic, iicbus_print); 422 } 423 424 CFATTACH_DECL_NEW(rk_i2c, sizeof(struct rk_i2c_softc), 425 rk_i2c_match, rk_i2c_attach, NULL, NULL); 426
Indexes created Tue Sep 30 20:09:53 GMT 2025