rk_i2c.c revision 1.11
1 /* $NetBSD: rk_i2c.c,v 1.11 2021/11/12 22:02:08 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2018 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 17 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 31 __KERNEL_RCSID(0, "$NetBSD: rk_i2c.c,v 1.11 2021/11/12 22:02:08 jmcneill Exp $"); 32 33 #include <sys/param.h> 34 #include <sys/bus.h> 35 #include <sys/device.h> 36 #include <sys/intr.h> 37 #include <sys/systm.h> 38 #include <sys/time.h> 39 #include <sys/kmem.h> 40 41 #include <dev/i2c/i2cvar.h> 42 43 #include <dev/fdt/fdtvar.h> 44 45 #define RKI2C_CON 0x000 46 #define RKI2C_CON_ACT2NAK __BIT(6) 47 #define RKI2C_CON_ACK __BIT(5) 48 #define RKI2C_CON_STOP __BIT(4) 49 #define RKI2C_CON_START __BIT(3) 50 #define RKI2C_CON_I2C_MODE __BITS(2,1) 51 #define RKI2C_CON_I2C_MODE_TX 0 52 #define RKI2C_CON_I2C_MODE_RTX 1 53 #define RKI2C_CON_I2C_MODE_RX 2 54 #define RKI2C_CON_I2C_MODE_RRX 3 55 #define RKI2C_CON_I2C_EN __BIT(0) 56 57 #define RKI2C_CLKDIV 0x004 58 #define RKI2C_CLKDIV_CLKDIVH __BITS(31,16) 59 #define RKI2C_CLKDIV_CLKDIVL __BITS(15,0) 60 61 #define RKI2C_MRXADDR 0x008 62 #define RKI2C_MRXADDR_ADDHVLD __BIT(26) 63 #define RKI2C_MRXADDR_ADDMVLD __BIT(25) 64 #define RKI2C_MRXADDR_ADDLVLD __BIT(24) 65 #define RKI2C_MRXADDR_SADDR __BITS(23,0) 66 67 #define RKI2C_MRXRADDR 0x00c 68 #define RKI2C_MRXRADDR_ADDHVLD __BIT(26) 69 #define RKI2C_MRXRADDR_ADDMVLD __BIT(25) 70 #define RKI2C_MRXRADDR_ADDLVLD __BIT(24) 71 #define RKI2C_MRXRADDR_SADDR __BITS(23,0) 72 73 #define RKI2C_MTXCNT 0x010 74 #define RKI2C_MTXCNT_MTXCNT __BITS(5,0) 75 76 #define RKI2C_MRXCNT 0x014 77 #define RKI2C_MRXCNT_MRXCNT __BITS(5,0) 78 79 #define RKI2C_IEN 0x018 80 #define RKI2C_IEN_NAKRCVIEN __BIT(6) 81 #define RKI2C_IEN_STOPIEN __BIT(5) 82 #define RKI2C_IEN_STARTIEN __BIT(4) 83 #define RKI2C_IEN_MBRFIEN __BIT(3) 84 #define RKI2C_IEN_MBTFIEN __BIT(2) 85 #define RKI2C_IEN_BRFIEN __BIT(1) 86 #define RKI2C_IEN_BTFIEN __BIT(0) 87 88 #define RKI2C_IPD 0x01c 89 #define RKI2C_IPD_NAKRCVIPD __BIT(6) 90 #define RKI2C_IPD_STOPIPD __BIT(5) 91 #define RKI2C_IPD_STARTIPD __BIT(4) 92 #define RKI2C_IPD_MBRFIPD __BIT(3) 93 #define RKI2C_IPD_MBTFIPD __BIT(2) 94 #define RKI2C_IPD_BRFIPD __BIT(1) 95 #define RKI2C_IPD_BTFIPD __BIT(0) 96 97 #define RKI2C_FCNT 0x020 98 #define RKI2C_FCNT_FCNT __BITS(5,0) 99 100 #define RKI2C_TXDATA(n) (0x100 + (n) * 4) 101 #define RKI2C_RXDATA(n) (0x200 + (n) * 4) 102 103 /* Compat data flags */ 104 #define RKI2C_HAS_PCLK __BIT(0) 105 106 static const struct device_compatible_entry compat_data[] = { 107 #if notyet 108 { .compat = "rockchip,rk3288-i2c", .value = 0 }, 109 #endif 110 { .compat = "rockchip,rk3399-i2c", .value = RKI2C_HAS_PCLK }, 111 DEVICE_COMPAT_EOL 112 }; 113 114 struct rk_i2c_softc { 115 device_t sc_dev; 116 bus_space_tag_t sc_bst; 117 bus_space_handle_t sc_bsh; 118 struct clk *sc_sclk; 119 struct clk *sc_pclk; 120 121 u_int sc_clkfreq; 122 123 struct i2c_controller sc_ic; 124 }; 125 126 #define RD4(sc, reg) \ 127 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg)) 128 #define WR4(sc, reg, val) \ 129 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)) 130 131 static void 132 rk_i2c_init(struct rk_i2c_softc *sc) 133 { 134 int div, divl, divh; 135 u_int rate; 136 137 /* 138 * SCL frequency is calculated by the following formula: 139 * 140 * SCL Divisor = 8 * (CLKDIVL + 1 + CLKDIVH + 1) 141 * SCL = PCLK / SCLK Divisor 142 */ 143 144 rate = clk_get_rate(sc->sc_sclk); 145 div = howmany(rate, sc->sc_clkfreq * 8) - 2; 146 if (div >= 0) { 147 divl = div / 2; 148 if (div % 2 == 0) 149 divh = divl; 150 else 151 divh = howmany(div, 2); 152 } else { 153 divl = divh = 0; 154 } 155 156 WR4(sc, RKI2C_CLKDIV, 157 __SHIFTIN(divh, RKI2C_CLKDIV_CLKDIVH) | 158 __SHIFTIN(divl, RKI2C_CLKDIV_CLKDIVL)); 159 160 /* 161 * Disable the module until we are ready to use it. 162 */ 163 WR4(sc, RKI2C_CON, 0); 164 WR4(sc, RKI2C_IEN, 0); 165 WR4(sc, RKI2C_IPD, RD4(sc, RKI2C_IPD)); 166 } 167 168 static int 169 rk_i2c_wait(struct rk_i2c_softc *sc, uint32_t mask) 170 { 171 u_int timeo = 100000; 172 uint32_t val; 173 174 const uint32_t ipdmask = mask | RKI2C_IPD_NAKRCVIPD; 175 do { 176 val = RD4(sc, RKI2C_IPD); 177 if (val & ipdmask) 178 break; 179 delay(1); 180 } while (--timeo > 0); 181 182 WR4(sc, RKI2C_IPD, val & ipdmask); 183 184 if ((val & RKI2C_IPD_NAKRCVIPD) != 0) 185 return EIO; 186 if ((val & mask) != 0) 187 return 0; 188 189 return ETIMEDOUT; 190 } 191 192 static int 193 rk_i2c_start(struct rk_i2c_softc *sc) 194 { 195 uint32_t con; 196 int error; 197 198 /* Send start */ 199 con = RD4(sc, RKI2C_CON); 200 con |= RKI2C_CON_START; 201 WR4(sc, RKI2C_CON, con); 202 203 if ((error = rk_i2c_wait(sc, RKI2C_IPD_STARTIPD)) != 0) 204 return error; 205 206 con &= ~RKI2C_CON_START; 207 WR4(sc, RKI2C_CON, con); 208 209 return 0; 210 } 211 212 static int 213 rk_i2c_stop(struct rk_i2c_softc *sc) 214 { 215 uint32_t con; 216 int error; 217 218 /* Send start */ 219 con = RD4(sc, RKI2C_CON); 220 con |= RKI2C_CON_STOP; 221 WR4(sc, RKI2C_CON, con); 222 223 if ((error = rk_i2c_wait(sc, RKI2C_IPD_STOPIPD)) != 0) 224 return error; 225 226 con &= ~RKI2C_CON_STOP; 227 WR4(sc, RKI2C_CON, con); 228 229 return 0; 230 } 231 232 static int 233 rk_i2c_write(struct rk_i2c_softc *sc, i2c_addr_t addr, const uint8_t *cmd, 234 size_t cmdlen, const uint8_t *buf, size_t buflen, int flags, bool send_start) 235 { 236 union { 237 uint8_t data8[32]; 238 uint32_t data32[8]; 239 } txdata; 240 uint32_t con; 241 u_int mode; 242 int error; 243 size_t len; 244 245 len = cmdlen + buflen; 246 if (len > 31) 247 return EINVAL; 248 249 mode = RKI2C_CON_I2C_MODE_TX; 250 con = RKI2C_CON_I2C_EN | __SHIFTIN(mode, RKI2C_CON_I2C_MODE); 251 WR4(sc, RKI2C_CON, con); 252 253 if (send_start && (error = rk_i2c_start(sc)) != 0) 254 return error; 255 256 /* Transmit data. Slave address goes in the lower 8 bits of TXDATA0 */ 257 txdata.data8[0] = addr << 1; 258 memcpy(&txdata.data8[1], cmd, cmdlen); 259 memcpy(&txdata.data8[1 + cmdlen], buf, buflen); 260 #if _BYTE_ORDER == _BIG_ENDIAN 261 for (int i = 0; i < howmany(len + 1, 4); i++) 262 LE32TOH(txdata.data32[i]); 263 #endif 264 bus_space_write_region_4(sc->sc_bst, sc->sc_bsh, RKI2C_TXDATA(0), 265 txdata.data32, howmany(len + 1, 4)); 266 WR4(sc, RKI2C_MTXCNT, __SHIFTIN(len + 1, RKI2C_MTXCNT_MTXCNT)); 267 268 if ((error = rk_i2c_wait(sc, RKI2C_IPD_MBTFIPD)) != 0) 269 return error; 270 271 return 0; 272 } 273 274 static int 275 rk_i2c_read(struct rk_i2c_softc *sc, i2c_addr_t addr, 276 const uint8_t *cmd, size_t cmdlen, uint8_t *buf, 277 size_t buflen, int flags, bool send_start, bool last_ack) 278 { 279 uint32_t rxdata[8]; 280 uint32_t con, mrxaddr, mrxraddr; 281 u_int mode; 282 int error, n; 283 284 if (buflen > 32) 285 return EINVAL; 286 if (cmdlen > 3) 287 return EINVAL; 288 289 mode = send_start ? RKI2C_CON_I2C_MODE_RTX : RKI2C_CON_I2C_MODE_RX; 290 con = RKI2C_CON_I2C_EN | __SHIFTIN(mode, RKI2C_CON_I2C_MODE); 291 WR4(sc, RKI2C_CON, con); 292 293 if (send_start && (error = rk_i2c_start(sc)) != 0) 294 return error; 295 296 if (send_start) { 297 mrxaddr = __SHIFTIN((addr << 1) | 1, RKI2C_MRXADDR_SADDR) | 298 RKI2C_MRXADDR_ADDLVLD; 299 WR4(sc, RKI2C_MRXADDR, mrxaddr); 300 for (n = 0, mrxraddr = 0; n < cmdlen; n++) { 301 mrxraddr |= cmd[n] << (n * 8); 302 mrxraddr |= (RKI2C_MRXRADDR_ADDLVLD << n); 303 } 304 WR4(sc, RKI2C_MRXRADDR, mrxraddr); 305 } 306 307 if (last_ack) { 308 con |= RKI2C_CON_ACK; 309 } 310 WR4(sc, RKI2C_CON, con); 311 312 /* Receive data. Slave address goes in the lower 8 bits of MRXADDR */ 313 WR4(sc, RKI2C_MRXCNT, __SHIFTIN(buflen, RKI2C_MRXCNT_MRXCNT)); 314 if ((error = rk_i2c_wait(sc, RKI2C_IPD_MBRFIPD)) != 0) 315 return error; 316 317 #if 0 318 bus_space_read_region_4(sc->sc_bst, sc->sc_bsh, RKI2C_RXDATA(0), 319 rxdata, howmany(buflen, 4)); 320 #else 321 for (n = 0; n < roundup(buflen, 4); n += 4) 322 rxdata[n/4] = RD4(sc, RKI2C_RXDATA(n/4)); 323 #endif 324 325 #if _BYTE_ORDER == _BIG_ENDIAN 326 for (int i = 0; i < howmany(buflen, 4); i++) 327 HTOLE32(rxdata[i]); 328 #endif 329 330 memcpy(buf, rxdata, buflen); 331 332 return 0; 333 } 334 335 static int 336 rk_i2c_exec(void *priv, i2c_op_t op, i2c_addr_t addr, 337 const void *cmdbuf, size_t cmdlen, void *buf, size_t buflen, int flags) 338 { 339 struct rk_i2c_softc * const sc = priv; 340 bool send_start = true; 341 int error; 342 343 if (I2C_OP_READ_P(op)) { 344 uint8_t *databuf = buf; 345 while (buflen > 0) { 346 const size_t datalen = uimin(buflen, 32); 347 const bool last_ack = datalen == buflen; 348 error = rk_i2c_read(sc, addr, cmdbuf, cmdlen, databuf, datalen, flags, send_start, last_ack); 349 if (error != 0) 350 break; 351 databuf += datalen; 352 buflen -= datalen; 353 send_start = false; 354 cmdbuf = NULL; 355 cmdlen = 0; 356 } 357 } else { 358 error = rk_i2c_write(sc, addr, cmdbuf, cmdlen, buf, buflen, flags, send_start); 359 } 360 361 if (error != 0 || I2C_OP_STOP_P(op)) 362 rk_i2c_stop(sc); 363 364 WR4(sc, RKI2C_CON, 0); 365 WR4(sc, RKI2C_IPD, RD4(sc, RKI2C_IPD)); 366 367 return error; 368 } 369 370 static int 371 rk_i2c_match(device_t parent, cfdata_t cf, void *aux) 372 { 373 struct fdt_attach_args * const faa = aux; 374 375 return of_compatible_match(faa->faa_phandle, compat_data); 376 } 377 378 static void 379 rk_i2c_attach(device_t parent, device_t self, void *aux) 380 { 381 struct rk_i2c_softc * const sc = device_private(self); 382 struct fdt_attach_args * const faa = aux; 383 const int phandle = faa->faa_phandle; 384 bus_addr_t addr; 385 bus_size_t size; 386 u_int flags; 387 388 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 389 aprint_error(": couldn't get registers\n"); 390 return; 391 } 392 393 flags = of_compatible_lookup(phandle, compat_data)->value; 394 395 sc->sc_sclk = fdtbus_clock_get(phandle, "i2c"); 396 if (sc->sc_sclk == NULL || clk_enable(sc->sc_sclk) != 0) { 397 aprint_error(": couldn't enable sclk\n"); 398 return; 399 } 400 401 if (ISSET(flags, RKI2C_HAS_PCLK)) { 402 sc->sc_pclk = fdtbus_clock_get(phandle, "pclk"); 403 if (sc->sc_pclk == NULL || clk_enable(sc->sc_pclk) != 0) { 404 aprint_error(": couldn't enable pclk\n"); 405 return; 406 } 407 } 408 409 if (of_getprop_uint32(phandle, "clock-frequency", &sc->sc_clkfreq)) 410 sc->sc_clkfreq = 100000; 411 412 sc->sc_dev = self; 413 sc->sc_bst = faa->faa_bst; 414 if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) { 415 aprint_error(": couldn't map registers\n"); 416 return; 417 } 418 419 aprint_naive("\n"); 420 aprint_normal(": Rockchip I2C (%u Hz)\n", sc->sc_clkfreq); 421 422 fdtbus_clock_assign(phandle); 423 424 rk_i2c_init(sc); 425 426 iic_tag_init(&sc->sc_ic); 427 sc->sc_ic.ic_cookie = sc; 428 sc->sc_ic.ic_exec = rk_i2c_exec; 429 430 fdtbus_register_i2c_controller(&sc->sc_ic, phandle); 431 432 fdtbus_attach_i2cbus(self, phandle, &sc->sc_ic, iicbus_print); 433 } 434 435 CFATTACH_DECL_NEW(rk_i2c, sizeof(struct rk_i2c_softc), 436 rk_i2c_match, rk_i2c_attach, NULL, NULL); 437
Indexes created Tue Sep 30 20:09:53 GMT 2025