rk_i2c.c revision 1.5
1 /* $NetBSD: rk_i2c.c,v 1.5 2019/09/18 12:49:34 tnn Exp $ */ 2 3 /*- 4 * Copyright (c) 2018 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 17 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 31 __KERNEL_RCSID(0, "$NetBSD: rk_i2c.c,v 1.5 2019/09/18 12:49:34 tnn Exp $"); 32 33 #include <sys/param.h> 34 #include <sys/bus.h> 35 #include <sys/device.h> 36 #include <sys/intr.h> 37 #include <sys/systm.h> 38 #include <sys/time.h> 39 #include <sys/kmem.h> 40 41 #include <dev/i2c/i2cvar.h> 42 43 #include <dev/fdt/fdtvar.h> 44 45 #define RKI2C_CON 0x000 46 #define RKI2C_CON_ACT2NAK __BIT(6) 47 #define RKI2C_CON_ACK __BIT(5) 48 #define RKI2C_CON_STOP __BIT(4) 49 #define RKI2C_CON_START __BIT(3) 50 #define RKI2C_CON_I2C_MODE __BITS(2,1) 51 #define RKI2C_CON_I2C_MODE_TX 0 52 #define RKI2C_CON_I2C_MODE_RTX 1 53 #define RKI2C_CON_I2C_MODE_RX 2 54 #define RKI2C_CON_I2C_MODE_RRX 3 55 #define RKI2C_CON_I2C_EN __BIT(0) 56 57 #define RKI2C_CLKDIV 0x004 58 #define RKI2C_CLKDIV_CLKDIVH __BITS(31,16) 59 #define RKI2C_CLKDIV_CLKDIVL __BITS(15,0) 60 61 #define RKI2C_MRXADDR 0x008 62 #define RKI2C_MRXADDR_ADDHVLD __BIT(26) 63 #define RKI2C_MRXADDR_ADDMVLD __BIT(25) 64 #define RKI2C_MRXADDR_ADDLVLD __BIT(24) 65 #define RKI2C_MRXADDR_SADDR __BITS(23,0) 66 67 #define RKI2C_MRXRADDR 0x00c 68 #define RKI2C_MRXRADDR_ADDHVLD __BIT(26) 69 #define RKI2C_MRXRADDR_ADDMVLD __BIT(25) 70 #define RKI2C_MRXRADDR_ADDLVLD __BIT(24) 71 #define RKI2C_MRXRADDR_SADDR __BITS(23,0) 72 73 #define RKI2C_MTXCNT 0x010 74 #define RKI2C_MTXCNT_MTXCNT __BITS(5,0) 75 76 #define RKI2C_MRXCNT 0x014 77 #define RKI2C_MRXCNT_MRXCNT __BITS(5,0) 78 79 #define RKI2C_IEN 0x018 80 #define RKI2C_IEN_NAKRCVIEN __BIT(6) 81 #define RKI2C_IEN_STOPIEN __BIT(5) 82 #define RKI2C_IEN_STARTIEN __BIT(4) 83 #define RKI2C_IEN_MBRFIEN __BIT(3) 84 #define RKI2C_IEN_MBTFIEN __BIT(2) 85 #define RKI2C_IEN_BRFIEN __BIT(1) 86 #define RKI2C_IEN_BTFIEN __BIT(0) 87 88 #define RKI2C_IPD 0x01c 89 #define RKI2C_IPD_NAKRCVIPD __BIT(6) 90 #define RKI2C_IPD_STOPIPD __BIT(5) 91 #define RKI2C_IPD_STARTIPD __BIT(4) 92 #define RKI2C_IPD_MBRFIPD __BIT(3) 93 #define RKI2C_IPD_MBTFIPD __BIT(2) 94 #define RKI2C_IPD_BRFIPD __BIT(1) 95 #define RKI2C_IPD_BTFIPD __BIT(0) 96 97 #define RKI2C_FCNT 0x020 98 #define RKI2C_FCNT_FCNT __BITS(5,0) 99 100 #define RKI2C_TXDATA(n) (0x100 + (n) * 4) 101 #define RKI2C_RXDATA(n) (0x200 + (n) * 4) 102 103 static const char * const compatible[] = { 104 "rockchip,rk3399-i2c", 105 NULL 106 }; 107 108 struct rk_i2c_softc { 109 device_t sc_dev; 110 bus_space_tag_t sc_bst; 111 bus_space_handle_t sc_bsh; 112 struct clk *sc_sclk; 113 struct clk *sc_pclk; 114 115 u_int sc_clkfreq; 116 117 struct i2c_controller sc_ic; 118 kmutex_t sc_lock; 119 kcondvar_t sc_cv; 120 }; 121 122 #define RD4(sc, reg) \ 123 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg)) 124 #define WR4(sc, reg, val) \ 125 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)) 126 127 static void 128 rk_i2c_init(struct rk_i2c_softc *sc) 129 { 130 int div, divl, divh; 131 u_int rate; 132 133 /* 134 * SCL frequency is calculated by the following formula: 135 * 136 * SCL Divisor = 8 * (CLKDIVL + 1 + CLKDIVH + 1) 137 * SCL = PCLK / SCLK Divisor 138 */ 139 140 rate = clk_get_rate(sc->sc_sclk); 141 div = howmany(rate, sc->sc_clkfreq * 8) - 2; 142 if (div >= 0) { 143 divl = div / 2; 144 if (div % 2 == 0) 145 divh = divl; 146 else 147 divh = howmany(div, 2); 148 } else { 149 divl = divh = 0; 150 } 151 152 WR4(sc, RKI2C_CLKDIV, 153 __SHIFTIN(divh, RKI2C_CLKDIV_CLKDIVH) | 154 __SHIFTIN(divl, RKI2C_CLKDIV_CLKDIVL)); 155 156 /* 157 * Disable the module until we are ready to use it. 158 */ 159 WR4(sc, RKI2C_CON, 0); 160 WR4(sc, RKI2C_IEN, 0); 161 WR4(sc, RKI2C_IPD, RD4(sc, RKI2C_IPD)); 162 } 163 164 static int 165 rk_i2c_acquire_bus(void *priv, int flags) 166 { 167 struct rk_i2c_softc * const sc = priv; 168 169 mutex_enter(&sc->sc_lock); 170 171 return 0; 172 } 173 174 static void 175 rk_i2c_release_bus(void *priv, int flags) 176 { 177 struct rk_i2c_softc * const sc = priv; 178 179 mutex_exit(&sc->sc_lock); 180 } 181 182 static int 183 rk_i2c_wait(struct rk_i2c_softc *sc, uint32_t mask) 184 { 185 u_int timeo = 100000; 186 uint32_t val; 187 188 const uint32_t ipdmask = mask | RKI2C_IPD_NAKRCVIPD; 189 do { 190 val = RD4(sc, RKI2C_IPD); 191 if (val & ipdmask) 192 break; 193 delay(1); 194 } while (--timeo > 0); 195 196 WR4(sc, RKI2C_IPD, val & ipdmask); 197 198 if ((val & RKI2C_IPD_NAKRCVIPD) != 0) 199 return EIO; 200 if ((val & mask) != 0) 201 return 0; 202 203 return ETIMEDOUT; 204 } 205 206 static int 207 rk_i2c_start(struct rk_i2c_softc *sc) 208 { 209 uint32_t con; 210 int error; 211 212 /* Send start */ 213 con = RD4(sc, RKI2C_CON); 214 con |= RKI2C_CON_START; 215 WR4(sc, RKI2C_CON, con); 216 217 if ((error = rk_i2c_wait(sc, RKI2C_IPD_STARTIPD)) != 0) 218 return error; 219 220 con &= ~RKI2C_CON_START; 221 WR4(sc, RKI2C_CON, con); 222 223 return 0; 224 } 225 226 static int 227 rk_i2c_stop(struct rk_i2c_softc *sc) 228 { 229 uint32_t con; 230 int error; 231 232 /* Send start */ 233 con = RD4(sc, RKI2C_CON); 234 con |= RKI2C_CON_STOP; 235 WR4(sc, RKI2C_CON, con); 236 237 if ((error = rk_i2c_wait(sc, RKI2C_IPD_STOPIPD)) != 0) 238 return error; 239 240 con &= ~RKI2C_CON_STOP; 241 WR4(sc, RKI2C_CON, con); 242 243 return 0; 244 } 245 246 static int 247 rk_i2c_write(struct rk_i2c_softc *sc, i2c_addr_t addr, const uint8_t *cmd, 248 size_t cmdlen, const uint8_t *buf, size_t buflen, int flags, bool send_start) 249 { 250 union { 251 uint8_t data8[32]; 252 uint32_t data32[8]; 253 } txdata; 254 uint32_t con; 255 u_int mode; 256 int error; 257 size_t len; 258 259 len = cmdlen + buflen; 260 if (len > 31) 261 return EINVAL; 262 263 mode = RKI2C_CON_I2C_MODE_TX; 264 con = RKI2C_CON_I2C_EN | __SHIFTIN(mode, RKI2C_CON_I2C_MODE); 265 WR4(sc, RKI2C_CON, con); 266 267 if (send_start && (error = rk_i2c_start(sc)) != 0) 268 return error; 269 270 /* Transmit data. Slave address goes in the lower 8 bits of TXDATA0 */ 271 txdata.data8[0] = addr << 1; 272 memcpy(&txdata.data8[1], cmd, cmdlen); 273 memcpy(&txdata.data8[1 + cmdlen], buf, buflen); 274 bus_space_write_region_4(sc->sc_bst, sc->sc_bsh, RKI2C_TXDATA(0), 275 txdata.data32, howmany(len + 1, 4)); 276 WR4(sc, RKI2C_MTXCNT, __SHIFTIN(len + 1, RKI2C_MTXCNT_MTXCNT)); 277 278 if ((error = rk_i2c_wait(sc, RKI2C_IPD_MBTFIPD)) != 0) 279 return error; 280 281 return 0; 282 } 283 284 static int 285 rk_i2c_read(struct rk_i2c_softc *sc, i2c_addr_t addr, 286 const uint8_t *cmd, size_t cmdlen, uint8_t *buf, 287 size_t buflen, int flags, bool send_start) 288 { 289 uint32_t rxdata[8]; 290 uint32_t con, mrxaddr, mrxraddr; 291 u_int mode; 292 int error, n; 293 294 if (buflen > 32) 295 return EINVAL; 296 if (cmdlen > 3) 297 return EINVAL; 298 299 mode = RKI2C_CON_I2C_MODE_RTX; 300 con = RKI2C_CON_I2C_EN | RKI2C_CON_ACK | __SHIFTIN(mode, RKI2C_CON_I2C_MODE); 301 WR4(sc, RKI2C_CON, con); 302 303 if (send_start && (error = rk_i2c_start(sc)) != 0) 304 return error; 305 306 mrxaddr = __SHIFTIN((addr << 1) | 1, RKI2C_MRXADDR_SADDR) | 307 RKI2C_MRXADDR_ADDLVLD; 308 WR4(sc, RKI2C_MRXADDR, mrxaddr); 309 for (n = 0, mrxraddr = 0; n < cmdlen; n++) { 310 mrxraddr |= cmd[n] << (n * 8); 311 mrxraddr |= (RKI2C_MRXRADDR_ADDLVLD << n); 312 } 313 WR4(sc, RKI2C_MRXRADDR, mrxraddr); 314 315 /* Acknowledge last byte read */ 316 con |= RKI2C_CON_ACK; 317 WR4(sc, RKI2C_CON, con); 318 319 /* Receive data. Slave address goes in the lower 8 bits of MRXADDR */ 320 WR4(sc, RKI2C_MRXCNT, __SHIFTIN(buflen, RKI2C_MRXCNT_MRXCNT)); 321 if ((error = rk_i2c_wait(sc, RKI2C_IPD_MBRFIPD)) != 0) 322 return error; 323 324 bus_space_read_region_4(sc->sc_bst, sc->sc_bsh, RKI2C_RXDATA(0), 325 rxdata, howmany(buflen, 4)); 326 memcpy(buf, rxdata, buflen); 327 328 return 0; 329 } 330 331 static int 332 rk_i2c_exec(void *priv, i2c_op_t op, i2c_addr_t addr, 333 const void *cmdbuf, size_t cmdlen, void *buf, size_t buflen, int flags) 334 { 335 struct rk_i2c_softc * const sc = priv; 336 bool send_start = true; 337 int error; 338 339 KASSERT(mutex_owned(&sc->sc_lock)); 340 341 if (I2C_OP_READ_P(op)) { 342 error = rk_i2c_read(sc, addr, cmdbuf, cmdlen, buf, buflen, flags, send_start); 343 } else { 344 error = rk_i2c_write(sc, addr, cmdbuf, cmdlen, buf, buflen, flags, send_start); 345 } 346 347 if (error != 0 || I2C_OP_STOP_P(op)) 348 rk_i2c_stop(sc); 349 350 WR4(sc, RKI2C_CON, 0); 351 WR4(sc, RKI2C_IPD, RD4(sc, RKI2C_IPD)); 352 353 return error; 354 } 355 356 static i2c_tag_t 357 rk_i2c_get_tag(device_t dev) 358 { 359 struct rk_i2c_softc * const sc = device_private(dev); 360 361 return &sc->sc_ic; 362 } 363 364 static const struct fdtbus_i2c_controller_func rk_i2c_funcs = { 365 .get_tag = rk_i2c_get_tag, 366 }; 367 368 static int 369 rk_i2c_match(device_t parent, cfdata_t cf, void *aux) 370 { 371 struct fdt_attach_args * const faa = aux; 372 373 return of_match_compatible(faa->faa_phandle, compatible); 374 } 375 376 static void 377 rk_i2c_attach(device_t parent, device_t self, void *aux) 378 { 379 struct rk_i2c_softc * const sc = device_private(self); 380 struct fdt_attach_args * const faa = aux; 381 const int phandle = faa->faa_phandle; 382 bus_addr_t addr; 383 bus_size_t size; 384 385 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 386 aprint_error(": couldn't get registers\n"); 387 return; 388 } 389 390 sc->sc_sclk = fdtbus_clock_get(phandle, "i2c"); 391 if (sc->sc_sclk == NULL || clk_enable(sc->sc_sclk) != 0) { 392 aprint_error(": couldn't enable sclk\n"); 393 return; 394 } 395 396 sc->sc_pclk = fdtbus_clock_get(phandle, "pclk"); 397 if (sc->sc_pclk == NULL || clk_enable(sc->sc_pclk) != 0) { 398 aprint_error(": couldn't enable pclk\n"); 399 return; 400 } 401 402 if (of_getprop_uint32(phandle, "clock-frequency", &sc->sc_clkfreq)) 403 sc->sc_clkfreq = 100000; 404 405 sc->sc_dev = self; 406 sc->sc_bst = faa->faa_bst; 407 if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) { 408 aprint_error(": couldn't map registers\n"); 409 return; 410 } 411 412 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SCHED); 413 cv_init(&sc->sc_cv, "rkiic"); 414 415 aprint_naive("\n"); 416 aprint_normal(": Rockchip I2C (%u Hz)\n", sc->sc_clkfreq); 417 418 fdtbus_clock_assign(phandle); 419 420 rk_i2c_init(sc); 421 422 sc->sc_ic.ic_cookie = sc; 423 sc->sc_ic.ic_acquire_bus = rk_i2c_acquire_bus; 424 sc->sc_ic.ic_release_bus = rk_i2c_release_bus; 425 sc->sc_ic.ic_exec = rk_i2c_exec; 426 427 fdtbus_register_i2c_controller(self, phandle, &rk_i2c_funcs); 428 429 fdtbus_attach_i2cbus(self, phandle, &sc->sc_ic, iicbus_print); 430 } 431 432 CFATTACH_DECL_NEW(rk_i2c, sizeof(struct rk_i2c_softc), 433 rk_i2c_match, rk_i2c_attach, NULL, NULL); 434
Indexes created Tue Sep 30 20:09:53 GMT 2025