rk_i2c.c revision 1.7
1 /* $NetBSD: rk_i2c.c,v 1.7 2019/12/22 23:23:29 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2018 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 17 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 31 __KERNEL_RCSID(0, "$NetBSD: rk_i2c.c,v 1.7 2019/12/22 23:23:29 thorpej Exp $"); 32 33 #include <sys/param.h> 34 #include <sys/bus.h> 35 #include <sys/device.h> 36 #include <sys/intr.h> 37 #include <sys/systm.h> 38 #include <sys/time.h> 39 #include <sys/kmem.h> 40 41 #include <dev/i2c/i2cvar.h> 42 43 #include <dev/fdt/fdtvar.h> 44 45 #define RKI2C_CON 0x000 46 #define RKI2C_CON_ACT2NAK __BIT(6) 47 #define RKI2C_CON_ACK __BIT(5) 48 #define RKI2C_CON_STOP __BIT(4) 49 #define RKI2C_CON_START __BIT(3) 50 #define RKI2C_CON_I2C_MODE __BITS(2,1) 51 #define RKI2C_CON_I2C_MODE_TX 0 52 #define RKI2C_CON_I2C_MODE_RTX 1 53 #define RKI2C_CON_I2C_MODE_RX 2 54 #define RKI2C_CON_I2C_MODE_RRX 3 55 #define RKI2C_CON_I2C_EN __BIT(0) 56 57 #define RKI2C_CLKDIV 0x004 58 #define RKI2C_CLKDIV_CLKDIVH __BITS(31,16) 59 #define RKI2C_CLKDIV_CLKDIVL __BITS(15,0) 60 61 #define RKI2C_MRXADDR 0x008 62 #define RKI2C_MRXADDR_ADDHVLD __BIT(26) 63 #define RKI2C_MRXADDR_ADDMVLD __BIT(25) 64 #define RKI2C_MRXADDR_ADDLVLD __BIT(24) 65 #define RKI2C_MRXADDR_SADDR __BITS(23,0) 66 67 #define RKI2C_MRXRADDR 0x00c 68 #define RKI2C_MRXRADDR_ADDHVLD __BIT(26) 69 #define RKI2C_MRXRADDR_ADDMVLD __BIT(25) 70 #define RKI2C_MRXRADDR_ADDLVLD __BIT(24) 71 #define RKI2C_MRXRADDR_SADDR __BITS(23,0) 72 73 #define RKI2C_MTXCNT 0x010 74 #define RKI2C_MTXCNT_MTXCNT __BITS(5,0) 75 76 #define RKI2C_MRXCNT 0x014 77 #define RKI2C_MRXCNT_MRXCNT __BITS(5,0) 78 79 #define RKI2C_IEN 0x018 80 #define RKI2C_IEN_NAKRCVIEN __BIT(6) 81 #define RKI2C_IEN_STOPIEN __BIT(5) 82 #define RKI2C_IEN_STARTIEN __BIT(4) 83 #define RKI2C_IEN_MBRFIEN __BIT(3) 84 #define RKI2C_IEN_MBTFIEN __BIT(2) 85 #define RKI2C_IEN_BRFIEN __BIT(1) 86 #define RKI2C_IEN_BTFIEN __BIT(0) 87 88 #define RKI2C_IPD 0x01c 89 #define RKI2C_IPD_NAKRCVIPD __BIT(6) 90 #define RKI2C_IPD_STOPIPD __BIT(5) 91 #define RKI2C_IPD_STARTIPD __BIT(4) 92 #define RKI2C_IPD_MBRFIPD __BIT(3) 93 #define RKI2C_IPD_MBTFIPD __BIT(2) 94 #define RKI2C_IPD_BRFIPD __BIT(1) 95 #define RKI2C_IPD_BTFIPD __BIT(0) 96 97 #define RKI2C_FCNT 0x020 98 #define RKI2C_FCNT_FCNT __BITS(5,0) 99 100 #define RKI2C_TXDATA(n) (0x100 + (n) * 4) 101 #define RKI2C_RXDATA(n) (0x200 + (n) * 4) 102 103 static const char * const compatible[] = { 104 "rockchip,rk3399-i2c", 105 NULL 106 }; 107 108 struct rk_i2c_softc { 109 device_t sc_dev; 110 bus_space_tag_t sc_bst; 111 bus_space_handle_t sc_bsh; 112 struct clk *sc_sclk; 113 struct clk *sc_pclk; 114 115 u_int sc_clkfreq; 116 117 struct i2c_controller sc_ic; 118 }; 119 120 #define RD4(sc, reg) \ 121 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg)) 122 #define WR4(sc, reg, val) \ 123 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)) 124 125 static void 126 rk_i2c_init(struct rk_i2c_softc *sc) 127 { 128 int div, divl, divh; 129 u_int rate; 130 131 /* 132 * SCL frequency is calculated by the following formula: 133 * 134 * SCL Divisor = 8 * (CLKDIVL + 1 + CLKDIVH + 1) 135 * SCL = PCLK / SCLK Divisor 136 */ 137 138 rate = clk_get_rate(sc->sc_sclk); 139 div = howmany(rate, sc->sc_clkfreq * 8) - 2; 140 if (div >= 0) { 141 divl = div / 2; 142 if (div % 2 == 0) 143 divh = divl; 144 else 145 divh = howmany(div, 2); 146 } else { 147 divl = divh = 0; 148 } 149 150 WR4(sc, RKI2C_CLKDIV, 151 __SHIFTIN(divh, RKI2C_CLKDIV_CLKDIVH) | 152 __SHIFTIN(divl, RKI2C_CLKDIV_CLKDIVL)); 153 154 /* 155 * Disable the module until we are ready to use it. 156 */ 157 WR4(sc, RKI2C_CON, 0); 158 WR4(sc, RKI2C_IEN, 0); 159 WR4(sc, RKI2C_IPD, RD4(sc, RKI2C_IPD)); 160 } 161 162 static int 163 rk_i2c_wait(struct rk_i2c_softc *sc, uint32_t mask) 164 { 165 u_int timeo = 100000; 166 uint32_t val; 167 168 const uint32_t ipdmask = mask | RKI2C_IPD_NAKRCVIPD; 169 do { 170 val = RD4(sc, RKI2C_IPD); 171 if (val & ipdmask) 172 break; 173 delay(1); 174 } while (--timeo > 0); 175 176 WR4(sc, RKI2C_IPD, val & ipdmask); 177 178 if ((val & RKI2C_IPD_NAKRCVIPD) != 0) 179 return EIO; 180 if ((val & mask) != 0) 181 return 0; 182 183 return ETIMEDOUT; 184 } 185 186 static int 187 rk_i2c_start(struct rk_i2c_softc *sc) 188 { 189 uint32_t con; 190 int error; 191 192 /* Send start */ 193 con = RD4(sc, RKI2C_CON); 194 con |= RKI2C_CON_START; 195 WR4(sc, RKI2C_CON, con); 196 197 if ((error = rk_i2c_wait(sc, RKI2C_IPD_STARTIPD)) != 0) 198 return error; 199 200 con &= ~RKI2C_CON_START; 201 WR4(sc, RKI2C_CON, con); 202 203 return 0; 204 } 205 206 static int 207 rk_i2c_stop(struct rk_i2c_softc *sc) 208 { 209 uint32_t con; 210 int error; 211 212 /* Send start */ 213 con = RD4(sc, RKI2C_CON); 214 con |= RKI2C_CON_STOP; 215 WR4(sc, RKI2C_CON, con); 216 217 if ((error = rk_i2c_wait(sc, RKI2C_IPD_STOPIPD)) != 0) 218 return error; 219 220 con &= ~RKI2C_CON_STOP; 221 WR4(sc, RKI2C_CON, con); 222 223 return 0; 224 } 225 226 static int 227 rk_i2c_write(struct rk_i2c_softc *sc, i2c_addr_t addr, const uint8_t *cmd, 228 size_t cmdlen, const uint8_t *buf, size_t buflen, int flags, bool send_start) 229 { 230 union { 231 uint8_t data8[32]; 232 uint32_t data32[8]; 233 } txdata; 234 uint32_t con; 235 u_int mode; 236 int error; 237 size_t len; 238 239 len = cmdlen + buflen; 240 if (len > 31) 241 return EINVAL; 242 243 mode = RKI2C_CON_I2C_MODE_TX; 244 con = RKI2C_CON_I2C_EN | __SHIFTIN(mode, RKI2C_CON_I2C_MODE); 245 WR4(sc, RKI2C_CON, con); 246 247 if (send_start && (error = rk_i2c_start(sc)) != 0) 248 return error; 249 250 /* Transmit data. Slave address goes in the lower 8 bits of TXDATA0 */ 251 txdata.data8[0] = addr << 1; 252 memcpy(&txdata.data8[1], cmd, cmdlen); 253 memcpy(&txdata.data8[1 + cmdlen], buf, buflen); 254 bus_space_write_region_4(sc->sc_bst, sc->sc_bsh, RKI2C_TXDATA(0), 255 txdata.data32, howmany(len + 1, 4)); 256 WR4(sc, RKI2C_MTXCNT, __SHIFTIN(len + 1, RKI2C_MTXCNT_MTXCNT)); 257 258 if ((error = rk_i2c_wait(sc, RKI2C_IPD_MBTFIPD)) != 0) 259 return error; 260 261 return 0; 262 } 263 264 static int 265 rk_i2c_read(struct rk_i2c_softc *sc, i2c_addr_t addr, 266 const uint8_t *cmd, size_t cmdlen, uint8_t *buf, 267 size_t buflen, int flags, bool send_start, bool last_ack) 268 { 269 uint32_t rxdata[8]; 270 uint32_t con, mrxaddr, mrxraddr; 271 u_int mode; 272 int error, n; 273 274 if (buflen > 32) 275 return EINVAL; 276 if (cmdlen > 3) 277 return EINVAL; 278 279 mode = send_start ? RKI2C_CON_I2C_MODE_RTX : RKI2C_CON_I2C_MODE_RX; 280 con = RKI2C_CON_I2C_EN | __SHIFTIN(mode, RKI2C_CON_I2C_MODE); 281 WR4(sc, RKI2C_CON, con); 282 283 if (send_start && (error = rk_i2c_start(sc)) != 0) 284 return error; 285 286 if (send_start) { 287 mrxaddr = __SHIFTIN((addr << 1) | 1, RKI2C_MRXADDR_SADDR) | 288 RKI2C_MRXADDR_ADDLVLD; 289 WR4(sc, RKI2C_MRXADDR, mrxaddr); 290 for (n = 0, mrxraddr = 0; n < cmdlen; n++) { 291 mrxraddr |= cmd[n] << (n * 8); 292 mrxraddr |= (RKI2C_MRXRADDR_ADDLVLD << n); 293 } 294 WR4(sc, RKI2C_MRXRADDR, mrxraddr); 295 } 296 297 if (last_ack) { 298 con |= RKI2C_CON_ACK; 299 } 300 WR4(sc, RKI2C_CON, con); 301 302 /* Receive data. Slave address goes in the lower 8 bits of MRXADDR */ 303 WR4(sc, RKI2C_MRXCNT, __SHIFTIN(buflen, RKI2C_MRXCNT_MRXCNT)); 304 if ((error = rk_i2c_wait(sc, RKI2C_IPD_MBRFIPD)) != 0) 305 return error; 306 307 #if 0 308 bus_space_read_region_4(sc->sc_bst, sc->sc_bsh, RKI2C_RXDATA(0), 309 rxdata, howmany(buflen, 4)); 310 #else 311 for (n = 0; n < roundup(buflen, 4); n += 4) 312 rxdata[n/4] = RD4(sc, RKI2C_RXDATA(n/4)); 313 #endif 314 315 memcpy(buf, rxdata, buflen); 316 317 return 0; 318 } 319 320 static int 321 rk_i2c_exec(void *priv, i2c_op_t op, i2c_addr_t addr, 322 const void *cmdbuf, size_t cmdlen, void *buf, size_t buflen, int flags) 323 { 324 struct rk_i2c_softc * const sc = priv; 325 bool send_start = true; 326 int error; 327 328 if (I2C_OP_READ_P(op)) { 329 uint8_t *databuf = buf; 330 while (buflen > 0) { 331 const size_t datalen = uimin(buflen, 32); 332 const bool last_ack = datalen == buflen; 333 error = rk_i2c_read(sc, addr, cmdbuf, cmdlen, databuf, datalen, flags, send_start, last_ack); 334 if (error != 0) 335 break; 336 databuf += datalen; 337 buflen -= datalen; 338 send_start = false; 339 cmdbuf = NULL; 340 cmdlen = 0; 341 } 342 } else { 343 error = rk_i2c_write(sc, addr, cmdbuf, cmdlen, buf, buflen, flags, send_start); 344 } 345 346 if (error != 0 || I2C_OP_STOP_P(op)) 347 rk_i2c_stop(sc); 348 349 WR4(sc, RKI2C_CON, 0); 350 WR4(sc, RKI2C_IPD, RD4(sc, RKI2C_IPD)); 351 352 return error; 353 } 354 355 static i2c_tag_t 356 rk_i2c_get_tag(device_t dev) 357 { 358 struct rk_i2c_softc * const sc = device_private(dev); 359 360 return &sc->sc_ic; 361 } 362 363 static const struct fdtbus_i2c_controller_func rk_i2c_funcs = { 364 .get_tag = rk_i2c_get_tag, 365 }; 366 367 static int 368 rk_i2c_match(device_t parent, cfdata_t cf, void *aux) 369 { 370 struct fdt_attach_args * const faa = aux; 371 372 return of_match_compatible(faa->faa_phandle, compatible); 373 } 374 375 static void 376 rk_i2c_attach(device_t parent, device_t self, void *aux) 377 { 378 struct rk_i2c_softc * const sc = device_private(self); 379 struct fdt_attach_args * const faa = aux; 380 const int phandle = faa->faa_phandle; 381 bus_addr_t addr; 382 bus_size_t size; 383 384 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 385 aprint_error(": couldn't get registers\n"); 386 return; 387 } 388 389 sc->sc_sclk = fdtbus_clock_get(phandle, "i2c"); 390 if (sc->sc_sclk == NULL || clk_enable(sc->sc_sclk) != 0) { 391 aprint_error(": couldn't enable sclk\n"); 392 return; 393 } 394 395 sc->sc_pclk = fdtbus_clock_get(phandle, "pclk"); 396 if (sc->sc_pclk == NULL || clk_enable(sc->sc_pclk) != 0) { 397 aprint_error(": couldn't enable pclk\n"); 398 return; 399 } 400 401 if (of_getprop_uint32(phandle, "clock-frequency", &sc->sc_clkfreq)) 402 sc->sc_clkfreq = 100000; 403 404 sc->sc_dev = self; 405 sc->sc_bst = faa->faa_bst; 406 if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) { 407 aprint_error(": couldn't map registers\n"); 408 return; 409 } 410 411 aprint_naive("\n"); 412 aprint_normal(": Rockchip I2C (%u Hz)\n", sc->sc_clkfreq); 413 414 fdtbus_clock_assign(phandle); 415 416 rk_i2c_init(sc); 417 418 iic_tag_init(&sc->sc_ic); 419 sc->sc_ic.ic_cookie = sc; 420 sc->sc_ic.ic_exec = rk_i2c_exec; 421 422 fdtbus_register_i2c_controller(self, phandle, &rk_i2c_funcs); 423 424 fdtbus_attach_i2cbus(self, phandle, &sc->sc_ic, iicbus_print); 425 } 426 427 CFATTACH_DECL_NEW(rk_i2c, sizeof(struct rk_i2c_softc), 428 rk_i2c_match, rk_i2c_attach, NULL, NULL); 429
Indexes created Tue Sep 30 20:09:53 GMT 2025