rk_i2s.c revision 1.1
1 /* $NetBSD: rk_i2s.c,v 1.1 2019/11/16 13:24:03 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2019 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: rk_i2s.c,v 1.1 2019/11/16 13:24:03 jmcneill Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/bus.h> 34 #include <sys/cpu.h> 35 #include <sys/device.h> 36 #include <sys/kmem.h> 37 38 #include <sys/audioio.h> 39 #include <dev/audio/audio_if.h> 40 #include <dev/audio/linear.h> 41 42 #include <dev/fdt/fdtvar.h> 43 #include <dev/fdt/syscon.h> 44 45 #define RK_I2S_FIFO_DEPTH 32 46 #define RK_I2S_SAMPLE_RATE 48000 47 48 #define I2S_TXCR 0x00 49 #define TXCR_RCNT __BITS(22,17) 50 #define TXCR_TCSR __BITS(16,15) 51 #define TXCR_HWT __BIT(14) 52 #define TXCR_SJM __BIT(12) 53 #define TXCR_FBM __BIT(11) 54 #define TXCR_IBM __BITS(10,9) 55 #define TXCR_PBM __BITS(8,7) 56 #define TXCR_TFS __BIT(5) 57 #define TXCR_VDW __BITS(4,0) 58 #define I2S_RXCR 0x04 59 #define RXCR_RCSR __BITS(16,15) 60 #define RXCR_HWT __BIT(14) 61 #define RXCR_SJM __BIT(12) 62 #define RXCR_FBM __BIT(11) 63 #define RXCR_IBM __BITS(10,9) 64 #define RXCR_PBM __BITS(8,7) 65 #define RXCR_TFS __BIT(5) 66 #define RXCR_VDW __BITS(4,0) 67 #define I2S_CKR 0x08 68 #define CKR_TRCM __BITS(29,28) 69 #define CKR_MSS __BIT(27) 70 #define CKR_CKP __BIT(26) 71 #define CKR_RLP __BIT(25) 72 #define CKR_TLP __BIT(24) 73 #define CKR_MDIV __BITS(23,16) 74 #define CKR_RSD __BITS(15,8) 75 #define CKR_TSD __BITS(7,0) 76 #define I2S_TXFIFOLR 0x0c 77 #define TXFIFOLR_TFL(n) __BITS((n) * 6 + 5, (n) * 6) 78 #define I2S_DMACR 0x10 79 #define DMACR_RDE __BIT(24) 80 #define DMACR_RDL __BITS(20,16) 81 #define DMACR_TDE __BIT(8) 82 #define DMACR_TDL __BITS(4,0) 83 #define I2S_INTCR 0x14 84 #define INTCR_RFT __BITS(24,20) 85 #define INTCR_RXOIC __BIT(18) 86 #define INTCR_RXOIE __BIT(17) 87 #define INTCR_RXFIE __BIT(16) 88 #define INTCR_TFT __BITS(8,4) 89 #define INTCR_TXUIC __BIT(2) 90 #define INTCR_TXUIE __BIT(1) 91 #define INTCR_TXEIE __BIT(0) 92 #define I2S_INTSR 0x18 93 #define INTSR_RXOI __BIT(17) 94 #define INTSR_RXFI __BIT(16) 95 #define INTSR_TXUI __BIT(1) 96 #define INTSR_TXEI __BIT(0) 97 #define I2S_XFER 0x1c 98 #define XFER_RXS __BIT(1) 99 #define XFER_TXS __BIT(0) 100 #define I2S_CLR 0x20 101 #define CLR_RXC __BIT(1) 102 #define CLR_TXC __BIT(0) 103 #define I2S_TXDR 0x24 104 #define I2S_RXDR 0x28 105 #define I2S_RXFIFOLR 0x2c 106 #define RXFIFOLR_RFL(n) __BITS((n) * 6 + 5, (n) * 6) 107 108 struct rk_i2s_config { 109 bus_size_t oe_reg; 110 u_int oe_mask; 111 u_int oe_val; 112 }; 113 114 static const struct rk_i2s_config rk3399_i2s_config = { 115 .oe_reg = 0x0e220, 116 .oe_mask = __BITS(13,11), 117 .oe_val = 0x7, 118 }; 119 120 static const struct of_compat_data compat_data[] = { 121 { "rockchip,rk3399-i2s", (uintptr_t)&rk3399_i2s_config }, 122 { NULL } 123 }; 124 125 struct rk_i2s_softc; 126 127 struct rk_i2s_chan { 128 uint32_t *ch_start; 129 uint32_t *ch_end; 130 uint32_t *ch_cur; 131 132 int ch_blksize; 133 int ch_resid; 134 135 void (*ch_intr)(void *); 136 void *ch_intrarg; 137 }; 138 139 struct rk_i2s_softc { 140 device_t sc_dev; 141 bus_space_tag_t sc_bst; 142 bus_space_handle_t sc_bsh; 143 int sc_phandle; 144 struct clk *sc_clk; 145 struct syscon *sc_grf; 146 const struct rk_i2s_config *sc_conf; 147 148 kmutex_t sc_lock; 149 kmutex_t sc_intr_lock; 150 151 struct audio_format sc_format; 152 153 struct rk_i2s_chan sc_pchan; 154 struct rk_i2s_chan sc_rchan; 155 156 u_int sc_active; 157 158 struct audio_dai_device sc_dai; 159 }; 160 161 #define RD4(sc, reg) \ 162 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg)) 163 #define WR4(sc, reg, val) \ 164 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)) 165 166 static int 167 rk_i2s_query_format(void *priv, audio_format_query_t *afp) 168 { 169 struct rk_i2s_softc * const sc = priv; 170 171 return audio_query_format(&sc->sc_format, 1, afp); 172 } 173 174 static int 175 rk_i2s_set_format(void *priv, int setmode, 176 const audio_params_t *play, const audio_params_t *rec, 177 audio_filter_reg_t *pfil, audio_filter_reg_t *rfil) 178 { 179 struct rk_i2s_softc * const sc = priv; 180 uint32_t ckr, txcr, rxcr; 181 182 ckr = RD4(sc, I2S_CKR); 183 if ((ckr & CKR_MSS) == 0) { 184 const u_int mclk_rate = clk_get_rate(sc->sc_clk); 185 device_printf(sc->sc_dev, "%s: sysclk rate %u Hz\n", __func__, mclk_rate); 186 const u_int bclk_rate = 2 * 32 * RK_I2S_SAMPLE_RATE; 187 const u_int bclk_div = mclk_rate / bclk_rate; 188 const u_int lrck_div = bclk_rate / RK_I2S_SAMPLE_RATE; 189 190 ckr &= ~CKR_MDIV; 191 ckr |= __SHIFTIN(bclk_div - 1, CKR_MDIV); 192 ckr &= ~CKR_TSD; 193 ckr |= __SHIFTIN(lrck_div - 1, CKR_TSD); 194 ckr &= ~CKR_RSD; 195 ckr |= __SHIFTIN(lrck_div - 1, CKR_RSD); 196 } 197 198 ckr &= ~CKR_TRCM; 199 ckr |= __SHIFTIN(0, CKR_TRCM); 200 WR4(sc, I2S_CKR, ckr); 201 202 if (play && (setmode & AUMODE_PLAY) != 0) { 203 if (play->channels & 1) 204 return EINVAL; 205 txcr = RD4(sc, I2S_TXCR); 206 txcr &= ~TXCR_VDW; 207 txcr |= __SHIFTIN(play->validbits - 1, TXCR_VDW); 208 txcr &= ~TXCR_TCSR; 209 txcr |= __SHIFTIN(play->channels / 2 - 1, TXCR_TCSR); 210 WR4(sc, I2S_TXCR, txcr); 211 } 212 213 if (rec && (setmode & AUMODE_RECORD) != 0) { 214 if (rec->channels & 1) 215 return EINVAL; 216 rxcr = RD4(sc, I2S_RXCR); 217 rxcr &= ~RXCR_VDW; 218 rxcr |= __SHIFTIN(rec->validbits - 1, RXCR_VDW); 219 rxcr &= ~RXCR_RCSR; 220 rxcr |= __SHIFTIN(rec->channels / 2 - 1, RXCR_RCSR); 221 WR4(sc, I2S_RXCR, rxcr); 222 } 223 224 return 0; 225 } 226 227 static int 228 rk_i2s_get_props(void *priv) 229 { 230 231 return AUDIO_PROP_PLAYBACK | AUDIO_PROP_CAPTURE | 232 AUDIO_PROP_FULLDUPLEX; 233 } 234 235 static int 236 rk_i2s_round_blocksize(void *priv, int bs, int mode, 237 const audio_params_t *params) 238 { 239 bs &= ~3; 240 if (bs == 0) 241 bs = 4; 242 return bs; 243 } 244 245 static void * 246 rk_i2s_allocm(void *priv, int dir, size_t size) 247 { 248 return kmem_zalloc(size, KM_SLEEP); 249 } 250 251 static void 252 rk_i2s_freem(void *priv, void *addr, size_t size) 253 { 254 kmem_free(addr, size); 255 } 256 257 static int 258 rk_i2s_trigger_output(void *priv, void *start, void *end, int blksize, 259 void (*intr)(void *), void *intrarg, const audio_params_t *params) 260 { 261 struct rk_i2s_softc * const sc = priv; 262 struct rk_i2s_chan *ch = &sc->sc_pchan; 263 uint32_t val; 264 265 if (sc->sc_active == 0) { 266 val = RD4(sc, I2S_XFER); 267 val |= (XFER_TXS | XFER_RXS); 268 WR4(sc, I2S_XFER, val); 269 } 270 271 sc->sc_active |= XFER_TXS; 272 273 val = RD4(sc, I2S_INTCR); 274 val |= INTCR_TXEIE; 275 val &= ~INTCR_TFT; 276 val |= __SHIFTIN(RK_I2S_FIFO_DEPTH / 2, INTCR_TFT); 277 WR4(sc, I2S_INTCR, val); 278 279 ch->ch_intr = intr; 280 ch->ch_intrarg = intrarg; 281 ch->ch_start = ch->ch_cur = start; 282 ch->ch_end = end; 283 ch->ch_blksize = blksize; 284 ch->ch_resid = blksize; 285 286 return 0; 287 } 288 289 static int 290 rk_i2s_trigger_input(void *priv, void *start, void *end, int blksize, 291 void (*intr)(void *), void *intrarg, const audio_params_t *params) 292 { 293 return EIO; 294 } 295 296 static int 297 rk_i2s_halt_output(void *priv) 298 { 299 struct rk_i2s_softc * const sc = priv; 300 struct rk_i2s_chan *ch = &sc->sc_pchan; 301 uint32_t val; 302 303 sc->sc_active &= ~XFER_TXS; 304 if (sc->sc_active == 0) { 305 val = RD4(sc, I2S_XFER); 306 val &= ~(XFER_TXS|XFER_RXS); 307 WR4(sc, I2S_XFER, val); 308 } 309 310 val = RD4(sc, I2S_INTCR); 311 val &= ~INTCR_TXEIE; 312 WR4(sc, I2S_INTCR, val); 313 314 val = RD4(sc, I2S_CLR); 315 val |= CLR_TXC; 316 WR4(sc, I2S_CLR, val); 317 318 while ((RD4(sc, I2S_CLR) & CLR_TXC) != 0) 319 delay(1); 320 321 ch->ch_intr = NULL; 322 ch->ch_intrarg = NULL; 323 324 return 0; 325 } 326 327 static int 328 rk_i2s_halt_input(void *priv) 329 { 330 struct rk_i2s_softc * const sc = priv; 331 struct rk_i2s_chan *ch = &sc->sc_rchan; 332 uint32_t val; 333 334 sc->sc_active &= ~XFER_RXS; 335 if (sc->sc_active == 0) { 336 val = RD4(sc, I2S_XFER); 337 val &= ~(XFER_TXS|XFER_RXS); 338 WR4(sc, I2S_XFER, val); 339 } 340 341 val = RD4(sc, I2S_INTCR); 342 val &= ~INTCR_RXFIE; 343 WR4(sc, I2S_INTCR, val); 344 345 ch->ch_intr = NULL; 346 ch->ch_intrarg = NULL; 347 348 return 0; 349 } 350 351 static void 352 rk_i2s_get_locks(void *priv, kmutex_t **intr, kmutex_t **thread) 353 { 354 struct rk_i2s_softc * const sc = priv; 355 356 *intr = &sc->sc_intr_lock; 357 *thread = &sc->sc_lock; 358 } 359 360 static const struct audio_hw_if rk_i2s_hw_if = { 361 .query_format = rk_i2s_query_format, 362 .set_format = rk_i2s_set_format, 363 .get_props = rk_i2s_get_props, 364 .round_blocksize = rk_i2s_round_blocksize, 365 .allocm = rk_i2s_allocm, 366 .freem = rk_i2s_freem, 367 .trigger_output = rk_i2s_trigger_output, 368 .trigger_input = rk_i2s_trigger_input, 369 .halt_output = rk_i2s_halt_output, 370 .halt_input = rk_i2s_halt_input, 371 .get_locks = rk_i2s_get_locks, 372 }; 373 374 static int 375 rk_i2s_intr(void *priv) 376 { 377 struct rk_i2s_softc * const sc = priv; 378 struct rk_i2s_chan * const pch = &sc->sc_pchan; 379 #if notyet 380 struct rk_i2s_chan * const rch = &sc->sc_rchan; 381 #endif 382 uint32_t sr, val; 383 int fifolr; 384 385 mutex_enter(&sc->sc_intr_lock); 386 387 sr = RD4(sc, I2S_INTSR); 388 389 if ((sr & INTSR_RXFI) != 0) { 390 #if notyet 391 val = RD4(sc, I2S_RXFIFOLR); 392 fifolr = __SHIFTOUT(val, RXFIFOLR_RFL(0)); 393 while (fifolr > 0) { 394 *rch->ch_data = RD4(sc, I2S_RXDR); 395 rch->ch_data++; 396 rch->ch_resid -= 4; 397 if (rch->ch_resid == 0) 398 rch->ch_intr(rch->ch_intrarg); 399 --fifolr; 400 } 401 #endif 402 } 403 404 if ((sr & INTSR_TXEI) != 0) { 405 val = RD4(sc, I2S_TXFIFOLR); 406 fifolr = __SHIFTOUT(val, TXFIFOLR_TFL(0)); 407 fifolr = uimin(fifolr, RK_I2S_FIFO_DEPTH); 408 while (fifolr < RK_I2S_FIFO_DEPTH - 1) { 409 WR4(sc, I2S_TXDR, *pch->ch_cur); 410 pch->ch_cur++; 411 if (pch->ch_cur == pch->ch_end) 412 pch->ch_cur = pch->ch_start; 413 pch->ch_resid -= 4; 414 if (pch->ch_resid == 0) { 415 pch->ch_intr(pch->ch_intrarg); 416 pch->ch_resid = pch->ch_blksize; 417 } 418 ++fifolr; 419 } 420 } 421 422 mutex_exit(&sc->sc_intr_lock); 423 424 return 0; 425 } 426 427 static int 428 rk_i2s_dai_set_sysclk(audio_dai_tag_t dai, u_int rate, int dir) 429 { 430 struct rk_i2s_softc * const sc = audio_dai_private(dai); 431 int error; 432 433 device_printf(sc->sc_dev, "set sysclk %u Hz\n", rate); 434 error = clk_set_rate(sc->sc_clk, rate); 435 if (error != 0) { 436 device_printf(sc->sc_dev, "failed to set sysclk to %u Hz: %d\n", 437 rate, error); 438 return error; 439 } 440 441 return 0; 442 } 443 444 static int 445 rk_i2s_dai_set_format(audio_dai_tag_t dai, u_int format) 446 { 447 struct rk_i2s_softc * const sc = audio_dai_private(dai); 448 uint32_t txcr, rxcr, ckr; 449 450 const u_int fmt = __SHIFTOUT(format, AUDIO_DAI_FORMAT_MASK); 451 const u_int pol = __SHIFTOUT(format, AUDIO_DAI_POLARITY_MASK); 452 const u_int clk = __SHIFTOUT(format, AUDIO_DAI_CLOCK_MASK); 453 454 txcr = RD4(sc, I2S_TXCR); 455 rxcr = RD4(sc, I2S_RXCR); 456 ckr = RD4(sc, I2S_CKR); 457 458 txcr &= ~(TXCR_IBM|TXCR_PBM|TXCR_TFS); 459 rxcr &= ~(RXCR_IBM|RXCR_PBM|RXCR_TFS); 460 switch (fmt) { 461 case AUDIO_DAI_FORMAT_I2S: 462 txcr |= __SHIFTIN(0, TXCR_IBM); 463 rxcr |= __SHIFTIN(0, RXCR_IBM); 464 break; 465 case AUDIO_DAI_FORMAT_LJ: 466 txcr |= __SHIFTIN(1, TXCR_IBM); 467 rxcr |= __SHIFTIN(1, RXCR_IBM); 468 break; 469 case AUDIO_DAI_FORMAT_RJ: 470 txcr |= __SHIFTIN(2, TXCR_IBM); 471 rxcr |= __SHIFTIN(2, RXCR_IBM); 472 break; 473 case AUDIO_DAI_FORMAT_DSPA: 474 txcr |= __SHIFTIN(0, TXCR_PBM); 475 txcr |= TXCR_TFS; 476 rxcr |= __SHIFTIN(0, RXCR_PBM); 477 txcr |= RXCR_TFS; 478 break; 479 case AUDIO_DAI_FORMAT_DSPB: 480 txcr |= __SHIFTIN(1, TXCR_PBM); 481 txcr |= TXCR_TFS; 482 rxcr |= __SHIFTIN(1, RXCR_PBM); 483 txcr |= RXCR_TFS; 484 break; 485 default: 486 return EINVAL; 487 } 488 489 WR4(sc, I2S_TXCR, txcr); 490 WR4(sc, I2S_RXCR, rxcr); 491 492 switch (pol) { 493 case AUDIO_DAI_POLARITY_IB_NF: 494 ckr |= CKR_CKP; 495 break; 496 case AUDIO_DAI_POLARITY_NB_NF: 497 ckr &= ~CKR_CKP; 498 break; 499 default: 500 return EINVAL; 501 } 502 503 switch (clk) { 504 case AUDIO_DAI_CLOCK_CBM_CFM: 505 ckr |= CKR_MSS; /* sclk input */ 506 break; 507 case AUDIO_DAI_CLOCK_CBS_CFS: 508 ckr &= ~CKR_MSS; /* sclk output */ 509 break; 510 default: 511 return EINVAL; 512 } 513 514 WR4(sc, I2S_CKR, ckr); 515 516 return 0; 517 } 518 519 static audio_dai_tag_t 520 rk_i2s_dai_get_tag(device_t dev, const void *data, size_t len) 521 { 522 struct rk_i2s_softc * const sc = device_private(dev); 523 524 if (len != 4) 525 return NULL; 526 527 return &sc->sc_dai; 528 } 529 530 static struct fdtbus_dai_controller_func rk_i2s_dai_funcs = { 531 .get_tag = rk_i2s_dai_get_tag 532 }; 533 534 static int 535 rk_i2s_clock_init(struct rk_i2s_softc *sc) 536 { 537 const int phandle = sc->sc_phandle; 538 int error; 539 540 sc->sc_clk = fdtbus_clock_get(phandle, "i2s_clk"); 541 if (sc->sc_clk == NULL) { 542 aprint_error(": couldn't find i2s_clk clock\n"); 543 return ENXIO; 544 } 545 error = clk_enable(sc->sc_clk); 546 if (error != 0) { 547 aprint_error(": couldn't enable i2s_clk clock: %d\n", error); 548 return error; 549 } 550 551 /* Enable bus clock */ 552 if (fdtbus_clock_enable(phandle, "i2s_hclk", true) != 0) { 553 aprint_error(": couldn't enable i2s_hclk clock: %d\n", error); 554 return error; 555 } 556 557 return 0; 558 } 559 560 static int 561 rk_i2s_match(device_t parent, cfdata_t cf, void *aux) 562 { 563 struct fdt_attach_args * const faa = aux; 564 565 return of_match_compat_data(faa->faa_phandle, compat_data); 566 } 567 568 static void 569 rk_i2s_attach(device_t parent, device_t self, void *aux) 570 { 571 struct rk_i2s_softc * const sc = device_private(self); 572 struct fdt_attach_args * const faa = aux; 573 const int phandle = faa->faa_phandle; 574 char intrstr[128]; 575 bus_addr_t addr; 576 bus_size_t size; 577 uint32_t val; 578 579 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 580 aprint_error(": couldn't get registers\n"); 581 return; 582 } 583 if (!fdtbus_intr_str(phandle, 0, intrstr, sizeof(intrstr))) { 584 aprint_error(": couldn't decode interrupt\n"); 585 return; 586 } 587 588 sc->sc_dev = self; 589 sc->sc_phandle = phandle; 590 sc->sc_bst = faa->faa_bst; 591 if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) { 592 aprint_error(": couldn't map registers\n"); 593 return; 594 } 595 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_NONE); 596 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_SCHED); 597 598 sc->sc_conf = (void *)of_search_compatible(phandle, compat_data)->data; 599 sc->sc_grf = fdtbus_syscon_acquire(phandle, "rockchip,grf"); 600 if (sc->sc_grf != NULL && sc->sc_conf->oe_mask != 0) { 601 syscon_lock(sc->sc_grf); 602 val = __SHIFTIN(sc->sc_conf->oe_val, sc->sc_conf->oe_mask); 603 val |= (sc->sc_conf->oe_mask << 16); 604 syscon_write_4(sc->sc_grf, sc->sc_conf->oe_reg, val); 605 syscon_unlock(sc->sc_grf); 606 } 607 608 if (rk_i2s_clock_init(sc) != 0) 609 return; 610 611 aprint_naive("\n"); 612 aprint_normal(": I2S/PCM controller\n"); 613 614 if (fdtbus_intr_establish(phandle, 0, IPL_AUDIO, FDT_INTR_MPSAFE, rk_i2s_intr, sc) == NULL) { 615 aprint_error_dev(self, "couldn't establish interrupt on %s\n", intrstr); 616 return; 617 } 618 aprint_normal_dev(self, "interrupting on %s\n", intrstr); 619 620 sc->sc_format.mode = AUMODE_PLAY|AUMODE_RECORD; 621 sc->sc_format.encoding = AUDIO_ENCODING_SLINEAR_LE; 622 sc->sc_format.validbits = 16; 623 sc->sc_format.precision = 16; 624 sc->sc_format.channels = 2; 625 sc->sc_format.channel_mask = AUFMT_STEREO; 626 sc->sc_format.frequency_type = 1; 627 sc->sc_format.frequency[0] = RK_I2S_SAMPLE_RATE; 628 629 sc->sc_dai.dai_set_sysclk = rk_i2s_dai_set_sysclk; 630 sc->sc_dai.dai_set_format = rk_i2s_dai_set_format; 631 sc->sc_dai.dai_hw_if = &rk_i2s_hw_if; 632 sc->sc_dai.dai_dev = self; 633 sc->sc_dai.dai_priv = sc; 634 fdtbus_register_dai_controller(self, phandle, &rk_i2s_dai_funcs); 635 } 636 637 CFATTACH_DECL_NEW(rk_i2s, sizeof(struct rk_i2s_softc), 638 rk_i2s_match, rk_i2s_attach, NULL, NULL); 639
Indexes created Mon Sep 29 21:09:56 GMT 2025